[linux.git] / arch / mips / pci / pci-ddb5477.c

/*
 * PCI code for DDB5477.
 *
 * Copyright (C) 2001 MontaVista Software Inc.
 * Author: Jun Sun, [email protected] or [email protected]
 *
 * Copyright (C) 2004 by Ralf Baechle ([email protected])
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>

#include <asm/bootinfo.h>
#include <asm/debug.h>

#include <asm/ddb5xxx/ddb5xxx.h>

static struct resource extpci_io_resource = {
	.start	= DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
	.end	= DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
	.name	= "ext pci IO space",
	.flags	= IORESOURCE_IO
};

static struct resource extpci_mem_resource = {
	.start	= DDB_PCI0_MEM_BASE + 0x100000,
	.end	= DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
	.name	= "ext pci memory space",
	.flags	= IORESOURCE_MEM
};

static struct resource iopci_io_resource = {
	.start	= DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
	.end	= DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
	.name	= "io pci IO space",
	.flags	= IORESOURCE_IO
};

static struct resource iopci_mem_resource = {
	.start	= DDB_PCI1_MEM_BASE,
	.end	= DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
	.name	= "ext pci memory space",
	.flags	= IORESOURCE_MEM
};

extern struct pci_ops ddb5477_ext_pci_ops;
extern struct pci_ops ddb5477_io_pci_ops;

struct pci_controller ddb5477_ext_controller = {
	.pci_ops	= &ddb5477_ext_pci_ops,
	.io_resource	= &extpci_io_resource,
	.mem_resource	= &extpci_mem_resource
};

struct pci_controller ddb5477_io_controller = {
	.pci_ops	= &ddb5477_io_pci_ops,
	.io_resource	= &iopci_io_resource,
	.mem_resource	= &iopci_mem_resource
};


/*
 * we fix up irqs based on the slot number.
 * The first entry is at AD:11.
 * Fortunately this works because, although we have two pci buses,
 * they all have different slot numbers (except for rockhopper slot 20
 * which is handled below).
 *
 */

/*
 * irq mapping : device -> pci int # -> vrc4377 irq# ,
 * ddb5477 board manual page 4  and vrc5477 manual page 46
 */

/*
 * based on ddb5477 manual page 11
 */
#define		MAX_SLOT_NUM		21
static unsigned char irq_map[MAX_SLOT_NUM] = {
	/* SLOT:  0, AD:11 */ 0xff,
	/* SLOT:  1, AD:12 */ 0xff,
	/* SLOT:  2, AD:13 */ 0xff,
	/* SLOT:  3, AD:14 */ 0xff,
	/* SLOT:  4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */
	/* SLOT:  5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */
	/* SLOT:  6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */
	/* SLOT:  7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */
	/* SLOT:  8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */
	/* SLOT:  9, AD:20 */ 0xff,
	/* SLOT: 10, AD:21 */ 0xff,
	/* SLOT: 11, AD:22 */ 0xff,
	/* SLOT: 12, AD:23 */ 0xff,
	/* SLOT: 13, AD:24 */ 0xff,
	/* SLOT: 14, AD:25 */ 0xff,
	/* SLOT: 15, AD:26 */ 0xff,
	/* SLOT: 16, AD:27 */ 0xff,
	/* SLOT: 17, AD:28 */ 0xff,
	/* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
	/* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
	/* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
};
static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
	/* SLOT:  0, AD:11 */ 0xff,
	/* SLOT:  1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */
	/* SLOT:  2, AD:13 */ 0xff,
	/* SLOT:  3, AD:14 */ 0xff,
	/* SLOT:  4, AD:15 */ 14, /* M5229 ide ISA irq */
	/* SLOT:  5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */
	/* SLOT:  6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */
	/* SLOT:  7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */
	/* SLOT:  8, AD:19 */ 0, /* M5457 modem nop */
	/* SLOT:  9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */
	/* SLOT: 10, AD:21 */ 0xff,
	/* SLOT: 11, AD:22 */ 0xff,
	/* SLOT: 12, AD:23 */ 0xff,
	/* SLOT: 13, AD:24 */ 0xff,
	/* SLOT: 14, AD:25 */ 0xff,
	/* SLOT: 15, AD:26 */ 0xff,
	/* SLOT: 16, AD:27 */ 0xff,
	/* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */
	/* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
	/* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
	/* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
};

int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int slot_num;
	unsigned char *slot_irq_map;
	unsigned char irq;

	/*
	 * We ignore the swizzled slot and pin values.  The original
	 * pci_fixup_irq() codes largely base irq number on the dev slot
	 * numbers because except for one case they are unique even
	 * though there are multiple pci buses.
	 */

	if (mips_machtype == MACH_NEC_ROCKHOPPERII)
		slot_irq_map = rockhopperII_irq_map;
	else
		slot_irq_map = irq_map;

	slot_num = PCI_SLOT(dev->devfn);
	irq = slot_irq_map[slot_num];

	db_assert(slot_num < MAX_SLOT_NUM);

	db_assert(irq != 0xff);

	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);

	if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
		/* hack to distinquish overlapping slot 20s, one
		 * on bus 0 (ALI USB on the M1535 on the backplane),
		 * and one on bus 2 (NEC USB controller on the CPU board)
		 * Make the M1535 USB - ISA IRQ number 9.
		 */
		if (slot_num == 20 && dev->bus->number == 0) {
			pci_write_config_byte(dev,
					      PCI_INTERRUPT_LINE,
					      9);
			irq = 9;
		}

	}

	return irq;
}

/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

void ddb_pci_reset_bus(void)
{
	u32 temp;

	/*
	 * I am not sure about the "official" procedure, the following
	 * steps work as far as I know:
	 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
	 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
	 * The same is true for both PCI channels.
	 */
	temp = ddb_in32(DDB_PCICTL0_H);
	temp |= 0x80000000;
	ddb_out32(DDB_PCICTL0_H, temp);
	temp &= ~0xc0000000;
	ddb_out32(DDB_PCICTL0_H, temp);

	temp = ddb_in32(DDB_PCICTL1_H);
	temp |= 0x80000000;
	ddb_out32(DDB_PCICTL1_H, temp);
	temp &= ~0xc0000000;
	ddb_out32(DDB_PCICTL1_H, temp);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* PCI code for DDB5477.
	3	*
	4	* Copyright (C) 2001 MontaVista Software Inc.
	5	* Author: Jun Sun, [email protected] or [email protected]
	6	*
	7	* Copyright (C) 2004 by Ralf Baechle ([email protected])
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/types.h>
	17	#include <linux/pci.h>
	18
	19	#include <asm/bootinfo.h>
	20	#include <asm/debug.h>
	21
	22	#include <asm/ddb5xxx/ddb5xxx.h>
	23
	24	static struct resource extpci_io_resource = {
5e46c3ae RB	25	.start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
	26	.end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
	27	.name = "ext pci IO space",
	28	.flags = IORESOURCE_IO
1da177e4 LT	29	};
	30
	31	static struct resource extpci_mem_resource = {
5e46c3ae RB	32	.start = DDB_PCI0_MEM_BASE + 0x100000,
	33	.end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
	34	.name = "ext pci memory space",
	35	.flags = IORESOURCE_MEM
1da177e4 LT	36	};
	37
	38	static struct resource iopci_io_resource = {
5e46c3ae RB	39	.start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
	40	.end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
	41	.name = "io pci IO space",
	42	.flags = IORESOURCE_IO
1da177e4 LT	43	};
	44
	45	static struct resource iopci_mem_resource = {
5e46c3ae RB	46	.start = DDB_PCI1_MEM_BASE,
	47	.end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
	48	.name = "ext pci memory space",
	49	.flags = IORESOURCE_MEM
1da177e4 LT	50	};
	51
	52	extern struct pci_ops ddb5477_ext_pci_ops;
	53	extern struct pci_ops ddb5477_io_pci_ops;
	54
	55	struct pci_controller ddb5477_ext_controller = {
	56	.pci_ops = &ddb5477_ext_pci_ops,
	57	.io_resource = &extpci_io_resource,
	58	.mem_resource = &extpci_mem_resource
	59	};
	60
	61	struct pci_controller ddb5477_io_controller = {
	62	.pci_ops = &ddb5477_io_pci_ops,
	63	.io_resource = &iopci_io_resource,
	64	.mem_resource = &iopci_mem_resource
	65	};
	66
	67
	68
	69	/*
	70	* we fix up irqs based on the slot number.
	71	* The first entry is at AD:11.
	72	* Fortunately this works because, although we have two pci buses,
	73	* they all have different slot numbers (except for rockhopper slot 20
	74	* which is handled below).
	75	*
	76	*/
	77
	78	/*
42a3b4f2	79	* irq mapping : device -> pci int # -> vrc4377 irq# ,
1da177e4 LT	80	* ddb5477 board manual page 4 and vrc5477 manual page 46
	81	*/
	82
	83	/*
	84	* based on ddb5477 manual page 11
	85	*/
	86	#define MAX_SLOT_NUM 21
	87	static unsigned char irq_map[MAX_SLOT_NUM] = {
	88	/* SLOT: 0, AD:11 */ 0xff,
	89	/* SLOT: 1, AD:12 */ 0xff,
	90	/* SLOT: 2, AD:13 */ 0xff,
	91	/* SLOT: 3, AD:14 */ 0xff,
	92	/* SLOT: 4, AD:15 / VRC5477_IRQ_INTA, / onboard tulip */
	93	/* SLOT: 5, AD:16 / VRC5477_IRQ_INTB, / slot 1 */
	94	/* SLOT: 6, AD:17 / VRC5477_IRQ_INTC, / slot 2 */
	95	/* SLOT: 7, AD:18 / VRC5477_IRQ_INTD, / slot 3 */
	96	/* SLOT: 8, AD:19 / VRC5477_IRQ_INTE, / slot 4 */
	97	/* SLOT: 9, AD:20 */ 0xff,
	98	/* SLOT: 10, AD:21 */ 0xff,
	99	/* SLOT: 11, AD:22 */ 0xff,
	100	/* SLOT: 12, AD:23 */ 0xff,
	101	/* SLOT: 13, AD:24 */ 0xff,
	102	/* SLOT: 14, AD:25 */ 0xff,
	103	/* SLOT: 15, AD:26 */ 0xff,
	104	/* SLOT: 16, AD:27 */ 0xff,
	105	/* SLOT: 17, AD:28 */ 0xff,
	106	/* SLOT: 18, AD:29 / VRC5477_IRQ_IOPCI_INTC, / vrc5477 ac97 */
	107	/* SLOT: 19, AD:30 / VRC5477_IRQ_IOPCI_INTB, / vrc5477 usb peri */
	108	/* SLOT: 20, AD:31 / VRC5477_IRQ_IOPCI_INTA, / vrc5477 usb host */
	109	};
	110	static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
	111	/* SLOT: 0, AD:11 */ 0xff,
	112	/* SLOT: 1, AD:12 / VRC5477_IRQ_INTB, / onboard AMD PCNET */
	113	/* SLOT: 2, AD:13 */ 0xff,
	114	/* SLOT: 3, AD:14 */ 0xff,
	115	/* SLOT: 4, AD:15 / 14, / M5229 ide ISA irq */
	116	/* SLOT: 5, AD:16 / VRC5477_IRQ_INTD, / slot 3 */
	117	/* SLOT: 6, AD:17 / VRC5477_IRQ_INTA, / slot 4 */
	118	/* SLOT: 7, AD:18 / VRC5477_IRQ_INTD, / slot 5 */
	119	/* SLOT: 8, AD:19 / 0, / M5457 modem nop */
	120	/* SLOT: 9, AD:20 / VRC5477_IRQ_INTA, / slot 2 */
	121	/* SLOT: 10, AD:21 */ 0xff,
	122	/* SLOT: 11, AD:22 */ 0xff,
	123	/* SLOT: 12, AD:23 */ 0xff,
	124	/* SLOT: 13, AD:24 */ 0xff,
	125	/* SLOT: 14, AD:25 */ 0xff,
	126	/* SLOT: 15, AD:26 */ 0xff,
	127	/* SLOT: 16, AD:27 */ 0xff,
	128	/* SLOT: 17, AD:28 / 0, / M7101 PMU nop */
	129	/* SLOT: 18, AD:29 / VRC5477_IRQ_IOPCI_INTC, / vrc5477 ac97 */
	130	/* SLOT: 19, AD:30 / VRC5477_IRQ_IOPCI_INTB, / vrc5477 usb peri */
	131	/* SLOT: 20, AD:31 / VRC5477_IRQ_IOPCI_INTA, / vrc5477 usb host */
	132	};
	133
	134	int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	135	{
	136	int slot_num;
	137	unsigned char *slot_irq_map;
	138	unsigned char irq;
	139
42a3b4f2	140	/*
1da177e4	141	* We ignore the swizzled slot and pin values. The original
42a3b4f2	142	* pci_fixup_irq() codes largely base irq number on the dev slot
1da177e4 LT	143	* numbers because except for one case they are unique even
	144	* though there are multiple pci buses.
	145	*/
	146
	147	if (mips_machtype == MACH_NEC_ROCKHOPPERII)
	148	slot_irq_map = rockhopperII_irq_map;
	149	else
	150	slot_irq_map = irq_map;
	151
	152	slot_num = PCI_SLOT(dev->devfn);
	153	irq = slot_irq_map[slot_num];
	154
	155	db_assert(slot_num < MAX_SLOT_NUM);
	156
	157	db_assert(irq != 0xff);
	158
	159	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	160
	161	if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
	162	/* hack to distinquish overlapping slot 20s, one
42a3b4f2	163	* on bus 0 (ALI USB on the M1535 on the backplane),
1da177e4 LT	164	* and one on bus 2 (NEC USB controller on the CPU board)
	165	* Make the M1535 USB - ISA IRQ number 9.
	166	*/
	167	if (slot_num == 20 && dev->bus->number == 0) {
	168	pci_write_config_byte(dev,
	169	PCI_INTERRUPT_LINE,
	170	9);
	171	irq = 9;
	172	}
	173
	174	}
	175
	176	return irq;
	177	}
	178
	179	/* Do platform specific device initialization at pci_enable_device() time */
	180	int pcibios_plat_dev_init(struct pci_dev *dev)
	181	{
	182	return 0;
	183	}
	184
	185	void ddb_pci_reset_bus(void)
	186	{
	187	u32 temp;
	188
	189	/*
	190	* I am not sure about the "official" procedure, the following
	191	* steps work as far as I know:
	192	* We first set PCI cold reset bit (bit 31) in PCICTRL-H.
	193	* Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
	194	* The same is true for both PCI channels.
	195	*/
	196	temp = ddb_in32(DDB_PCICTL0_H);
	197	temp \|= 0x80000000;
	198	ddb_out32(DDB_PCICTL0_H, temp);
	199	temp &= ~0xc0000000;
	200	ddb_out32(DDB_PCICTL0_H, temp);
	201
	202	temp = ddb_in32(DDB_PCICTL1_H);
	203	temp \|= 0x80000000;
	204	ddb_out32(DDB_PCICTL1_H, temp);
	205	temp &= ~0xc0000000;
	206	ddb_out32(DDB_PCICTL1_H, temp);
	207	}