[linux.git] / arch / mips / rb532 / setup.c

/*
 * setup.c - boot time setup code
 */

#include <linux/init.h>
#include <linux/export.h>

#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <linux/ioport.h>

#include <asm/mach-rc32434/rb.h>
#include <asm/mach-rc32434/pci.h>

struct pci_reg __iomem *pci_reg;
EXPORT_SYMBOL(pci_reg);

static struct resource pci0_res[] = {
	{
		.name = "pci_reg0",
		.start = PCI0_BASE_ADDR,
		.end = PCI0_BASE_ADDR + sizeof(struct pci_reg),
		.flags = IORESOURCE_MEM,
	}
};

static void rb_machine_restart(char *command)
{
	/* just jump to the reset vector */
	writel(0x80000001, IDT434_REG_BASE + RST);
	((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
}

static void rb_machine_halt(void)
{
	for (;;)
		continue;
}

void __init plat_mem_setup(void)
{
	u32 val;

	_machine_restart = rb_machine_restart;
	_machine_halt = rb_machine_halt;
	pm_power_off = rb_machine_halt;

	set_io_port_base(KSEG1);

	pci_reg = ioremap_nocache(pci0_res[0].start,
				pci0_res[0].end - pci0_res[0].start);
	if (!pci_reg) {
		printk(KERN_ERR "Could not remap PCI registers\n");
		return;
	}

	val = __raw_readl(&pci_reg->pcic);
	val &= 0xFFFFFF7;
	__raw_writel(val, (void *)&pci_reg->pcic);

#ifdef CONFIG_PCI
	/* Enable PCI interrupts in EPLD Mask register */
	*epld_mask = 0x0;
	*(epld_mask + 1) = 0x0;
#endif
	write_c0_wired(0);
}

const char *get_system_type(void)
{
	switch (mips_machtype) {
	case MACH_MIKROTIK_RB532A:
		return "Mikrotik RB532A";
		break;
	default:
		return "Mikrotik RB532";
		break;
	}
}
Commit	Line	Data
73b4390f RB	1	/*
	2	* setup.c - boot time setup code
	3	*/
	4
	5	#include <linux/init.h>
cae39d13	6	#include <linux/export.h>
73b4390f RB	7
	8	#include <asm/bootinfo.h>
	9	#include <asm/reboot.h>
	10	#include <asm/time.h>
	11	#include <linux/ioport.h>
	12
606a083b	13	#include <asm/mach-rc32434/rb.h>
73b4390f RB	14	#include <asm/mach-rc32434/pci.h>
	15
	16	struct pci_reg __iomem *pci_reg;
	17	EXPORT_SYMBOL(pci_reg);
	18
	19	static struct resource pci0_res[] = {
	20	{
	21	.name = "pci_reg0",
	22	.start = PCI0_BASE_ADDR,
	23	.end = PCI0_BASE_ADDR + sizeof(struct pci_reg),
	24	.flags = IORESOURCE_MEM,
	25	}
	26	};
	27
	28	static void rb_machine_restart(char *command)
	29	{
	30	/* just jump to the reset vector */
606a083b	31	writel(0x80000001, IDT434_REG_BASE + RST);
73b4390f RB	32	((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
	33	}
	34
	35	static void rb_machine_halt(void)
	36	{
	37	for (;;)
	38	continue;
	39	}
	40
	41	void __init plat_mem_setup(void)
	42	{
	43	u32 val;
	44
	45	_machine_restart = rb_machine_restart;
	46	_machine_halt = rb_machine_halt;
	47	pm_power_off = rb_machine_halt;
	48
	49	set_io_port_base(KSEG1);
	50
	51	pci_reg = ioremap_nocache(pci0_res[0].start,
	52	pci0_res[0].end - pci0_res[0].start);
	53	if (!pci_reg) {
	54	printk(KERN_ERR "Could not remap PCI registers\n");
	55	return;
	56	}
	57
	58	val = __raw_readl(&pci_reg->pcic);
	59	val &= 0xFFFFFF7;
	60	__raw_writel(val, (void *)&pci_reg->pcic);
	61
	62	#ifdef CONFIG_PCI
	63	/* Enable PCI interrupts in EPLD Mask register */
	64	*epld_mask = 0x0;
	65	*(epld_mask + 1) = 0x0;
	66	#endif
	67	write_c0_wired(0);
	68	}
	69
	70	const char *get_system_type(void)
	71	{
	72	switch (mips_machtype) {
	73	case MACH_MIKROTIK_RB532A:
	74	return "Mikrotik RB532A";
	75	break;
	76	default:
	77	return "Mikrotik RB532";
	78	break;
	79	}
	80	}