[linux.git] / drivers / bcma / driver_mips.c

/*
 * Broadcom specific AMBA
 * Broadcom MIPS32 74K core driver
 *
 * Copyright 2009, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <[email protected]>
 * Copyright 2010, Bernhard Loos <[email protected]>
 * Copyright 2011, Hauke Mehrtens <[email protected]>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"

#include <linux/bcma/bcma.h>

#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/time.h>
#ifdef CONFIG_BCM47XX
#include <linux/bcm47xx_nvram.h>
#endif

enum bcma_boot_dev {
	BCMA_BOOT_DEV_UNK = 0,
	BCMA_BOOT_DEV_ROM,
	BCMA_BOOT_DEV_PARALLEL,
	BCMA_BOOT_DEV_SERIAL,
	BCMA_BOOT_DEV_NAND,
};

static const char * const part_probes[] = { "bcm47xxpart", NULL };

static struct physmap_flash_data bcma_pflash_data = {
	.part_probe_types	= part_probes,
};

static struct resource bcma_pflash_resource = {
	.name	= "bcma_pflash",
	.flags  = IORESOURCE_MEM,
};

struct platform_device bcma_pflash_dev = {
	.name		= "physmap-flash",
	.dev		= {
		.platform_data  = &bcma_pflash_data,
	},
	.resource	= &bcma_pflash_resource,
	.num_resources	= 1,
};

/* The 47162a0 hangs when reading MIPS DMP registers registers */
static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
{
	return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
	       dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
}

/* The 5357b0 hangs when reading USB20H DMP registers */
static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
{
	return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
		dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
	       dev->bus->chipinfo.pkg == 11 &&
	       dev->id.id == BCMA_CORE_USB20_HOST;
}

static inline u32 mips_read32(struct bcma_drv_mips *mcore,
			      u16 offset)
{
	return bcma_read32(mcore->core, offset);
}

static inline void mips_write32(struct bcma_drv_mips *mcore,
				u16 offset,
				u32 value)
{
	bcma_write32(mcore->core, offset, value);
}

static const u32 ipsflag_irq_mask[] = {
	0,
	BCMA_MIPS_IPSFLAG_IRQ1,
	BCMA_MIPS_IPSFLAG_IRQ2,
	BCMA_MIPS_IPSFLAG_IRQ3,
	BCMA_MIPS_IPSFLAG_IRQ4,
};

static const u32 ipsflag_irq_shift[] = {
	0,
	BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
	BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
	BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
	BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
};

static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
{
	u32 flag;

	if (bcma_core_mips_bcm47162a0_quirk(dev))
		return dev->core_index;
	if (bcma_core_mips_bcm5357b0_quirk(dev))
		return dev->core_index;
	flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);

	if (flag)
		return flag & 0x1F;
	else
		return 0x3f;
}

/* Get the MIPS IRQ assignment for a specified device.
 * If unassigned, 0 is returned.
 * If disabled, 5 is returned.
 * If not supported, 6 is returned.
 */
unsigned int bcma_core_mips_irq(struct bcma_device *dev)
{
	struct bcma_device *mdev = dev->bus->drv_mips.core;
	u32 irqflag;
	unsigned int irq;

	irqflag = bcma_core_mips_irqflag(dev);
	if (irqflag == 0x3f)
		return 6;

	for (irq = 0; irq <= 4; irq++)
		if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
		    (1 << irqflag))
			return irq;

	return 5;
}

static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
{
	unsigned int oldirq = bcma_core_mips_irq(dev);
	struct bcma_bus *bus = dev->bus;
	struct bcma_device *mdev = bus->drv_mips.core;
	u32 irqflag;

	irqflag = bcma_core_mips_irqflag(dev);
	BUG_ON(oldirq == 6);

	dev->irq = irq + 2;

	/* clear the old irq */
	if (oldirq == 0)
		bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
			    bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
			    ~(1 << irqflag));
	else if (oldirq != 5)
		bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);

	/* assign the new one */
	if (irq == 0) {
		bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
			    bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
			    (1 << irqflag));
	} else {
		u32 irqinitmask = bcma_read32(mdev,
					      BCMA_MIPS_MIPS74K_INTMASK(irq));
		if (irqinitmask) {
			struct bcma_device *core;

			/* backplane irq line is in use, find out who uses
			 * it and set user to irq 0
			 */
			list_for_each_entry(core, &bus->cores, list) {
				if ((1 << bcma_core_mips_irqflag(core)) ==
				    irqinitmask) {
					bcma_core_mips_set_irq(core, 0);
					break;
				}
			}
		}
		bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
			     1 << irqflag);
	}

	bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
		   dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
}

static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
					u16 coreid, u8 unit)
{
	struct bcma_device *core;

	core = bcma_find_core_unit(bus, coreid, unit);
	if (!core) {
		bcma_warn(bus,
			  "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
			  coreid, unit);
		return;
	}

	bcma_core_mips_set_irq(core, irq);
}

static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
{
	int i;
	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
	printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
	for (i = 0; i <= 6; i++)
		printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
	printk("\n");
}

static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
{
	struct bcma_device *core;

	list_for_each_entry(core, &bus->cores, list) {
		bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
	}
}

u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
{
	struct bcma_bus *bus = mcore->core->bus;

	if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
		return bcma_pmu_get_cpu_clock(&bus->drv_cc);

	bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
	return 0;
}
EXPORT_SYMBOL(bcma_cpu_clock);

static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
{
	struct bcma_drv_cc *cc = &bus->drv_cc;
	u8 cc_rev = cc->core->id.rev;

	if (cc_rev == 42) {
		struct bcma_device *core;

		core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
		if (core) {
			switch (bcma_aread32(core, BCMA_IOST) &
				BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
			case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
				return BCMA_BOOT_DEV_SERIAL;
			case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
				return BCMA_BOOT_DEV_NAND;
			case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
			default:
				return BCMA_BOOT_DEV_ROM;
			}
		}
	} else {
		if (cc_rev == 38) {
			if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
				return BCMA_BOOT_DEV_NAND;
			else if (cc->status & BIT(5))
				return BCMA_BOOT_DEV_ROM;
		}

		if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
		    BCMA_CC_FLASHT_PARA)
			return BCMA_BOOT_DEV_PARALLEL;
		else
			return BCMA_BOOT_DEV_SERIAL;
	}

	return BCMA_BOOT_DEV_SERIAL;
}

static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
{
	struct bcma_bus *bus = mcore->core->bus;
	struct bcma_drv_cc *cc = &bus->drv_cc;
	struct bcma_pflash *pflash = &cc->pflash;
	enum bcma_boot_dev boot_dev;

	switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
	case BCMA_CC_FLASHT_STSER:
	case BCMA_CC_FLASHT_ATSER:
		bcma_debug(bus, "Found serial flash\n");
		bcma_sflash_init(cc);
		break;
	case BCMA_CC_FLASHT_PARA:
		bcma_debug(bus, "Found parallel flash\n");
		pflash->present = true;
		pflash->window = BCMA_SOC_FLASH2;
		pflash->window_size = BCMA_SOC_FLASH2_SZ;

		if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
		     BCMA_CC_FLASH_CFG_DS) == 0)
			pflash->buswidth = 1;
		else
			pflash->buswidth = 2;

		bcma_pflash_data.width = pflash->buswidth;
		bcma_pflash_resource.start = pflash->window;
		bcma_pflash_resource.end = pflash->window + pflash->window_size;

		break;
	default:
		bcma_err(bus, "Flash type not supported\n");
	}

	if (cc->core->id.rev == 38 ||
	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
		if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
			bcma_debug(bus, "Found NAND flash\n");
			bcma_nflash_init(cc);
		}
	}

	/* Determine flash type this SoC boots from */
	boot_dev = bcma_boot_dev(bus);
	switch (boot_dev) {
	case BCMA_BOOT_DEV_PARALLEL:
	case BCMA_BOOT_DEV_SERIAL:
#ifdef CONFIG_BCM47XX
		bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH2,
					    BCMA_SOC_FLASH2_SZ);
#endif
		break;
	case BCMA_BOOT_DEV_NAND:
#ifdef CONFIG_BCM47XX
		bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH1,
					    BCMA_SOC_FLASH1_SZ);
#endif
		break;
	default:
		break;
	}
}

void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
{
	struct bcma_bus *bus = mcore->core->bus;

	if (mcore->early_setup_done)
		return;

	bcma_chipco_serial_init(&bus->drv_cc);
	bcma_core_mips_flash_detect(mcore);

	mcore->early_setup_done = true;
}

static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
{
	struct bcma_device *cpu, *pcie, *i2s;

	/* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
	 * (IRQ flags > 7 are ignored when setting the interrupt masks)
	 */
	if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
	    bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
		return;

	cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
	pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
	i2s = bcma_find_core(bus, BCMA_CORE_I2S);
	if (cpu && pcie && i2s &&
	    bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
	    bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
	    bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
		bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
		bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
		bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
		bcma_debug(bus,
			   "Moved i2s interrupt to oob line 7 instead of 8\n");
	}
}

void bcma_core_mips_init(struct bcma_drv_mips *mcore)
{
	struct bcma_bus *bus;
	struct bcma_device *core;
	bus = mcore->core->bus;

	if (mcore->setup_done)
		return;

	bcma_debug(bus, "Initializing MIPS core...\n");

	bcma_core_mips_early_init(mcore);

	bcma_fix_i2s_irqflag(bus);

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4716:
	case BCMA_CHIP_ID_BCM4748:
		bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
		bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
		bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
		bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
		bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
		bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
		break;
	case BCMA_CHIP_ID_BCM5356:
	case BCMA_CHIP_ID_BCM47162:
	case BCMA_CHIP_ID_BCM53572:
		bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
		bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
		bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
		break;
	case BCMA_CHIP_ID_BCM5357:
	case BCMA_CHIP_ID_BCM4749:
		bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
		bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
		bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
		bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
		bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
		break;
	case BCMA_CHIP_ID_BCM4706:
		bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
		bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
					    0);
		bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
		bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
		bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
					    0);
		break;
	default:
		list_for_each_entry(core, &bus->cores, list) {
			core->irq = bcma_core_irq(core, 0);
		}
		bcma_err(bus,
			 "Unknown device (0x%x) found, can not configure IRQs\n",
			 bus->chipinfo.id);
	}
	bcma_debug(bus, "IRQ reconfiguration done\n");
	bcma_core_mips_dump_irq(bus);

	mcore->setup_done = true;
}
Commit	Line	Data
21e0534a HM	1	/*
	2	* Broadcom specific AMBA
	3	* Broadcom MIPS32 74K core driver
	4	*
	5	* Copyright 2009, Broadcom Corporation
	6	* Copyright 2006, 2007, Michael Buesch <[email protected]>
	7	* Copyright 2010, Bernhard Loos <[email protected]>
	8	* Copyright 2011, Hauke Mehrtens <[email protected]>
	9	*
	10	* Licensed under the GNU/GPL. See COPYING for details.
	11	*/
	12
	13	#include "bcma_private.h"
	14
	15	#include <linux/bcma/bcma.h>
	16
73e4dbe4 RM	17	#include <linux/mtd/physmap.h>
73e4dbe4 RM	18	#include <linux/platform_device.h>
21e0534a HM	19	#include <linux/serial.h>
	20	#include <linux/serial_core.h>
	21	#include <linux/serial_reg.h>
	22	#include <linux/time.h>
7177efc5	23	#ifdef CONFIG_BCM47XX
138173d4	24	#include <linux/bcm47xx_nvram.h>
7177efc5	25	#endif
21e0534a	26
87fed556 RM	27	enum bcma_boot_dev {
	28	BCMA_BOOT_DEV_UNK = 0,
	29	BCMA_BOOT_DEV_ROM,
	30	BCMA_BOOT_DEV_PARALLEL,
	31	BCMA_BOOT_DEV_SERIAL,
	32	BCMA_BOOT_DEV_NAND,
	33	};
	34
f1faa69d	35	static const char * const part_probes[] = { "bcm47xxpart", NULL };
73e4dbe4 RM	36
	37	static struct physmap_flash_data bcma_pflash_data = {
	38	.part_probe_types = part_probes,
	39	};
	40
	41	static struct resource bcma_pflash_resource = {
	42	.name = "bcma_pflash",
	43	.flags = IORESOURCE_MEM,
	44	};
	45
	46	struct platform_device bcma_pflash_dev = {
	47	.name = "physmap-flash",
	48	.dev = {
	49	.platform_data = &bcma_pflash_data,
	50	},
	51	.resource = &bcma_pflash_resource,
	52	.num_resources = 1,
	53	};
	54
21e0534a HM	55	/* The 47162a0 hangs when reading MIPS DMP registers registers */
	56	static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
	57	{
4b4f5be2 HM	58	return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
4b4f5be2 HM	59	dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
21e0534a HM	60	}
	61
	62	/* The 5357b0 hangs when reading USB20H DMP registers */
	63	static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
	64	{
4b4f5be2 HM	65	return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
4b4f5be2 HM	66	dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
21e0534a HM	67	dev->bus->chipinfo.pkg == 11 &&
	68	dev->id.id == BCMA_CORE_USB20_HOST;
	69	}
	70
	71	static inline u32 mips_read32(struct bcma_drv_mips *mcore,
	72	u16 offset)
	73	{
	74	return bcma_read32(mcore->core, offset);
	75	}
	76
	77	static inline void mips_write32(struct bcma_drv_mips *mcore,
	78	u16 offset,
	79	u32 value)
	80	{
	81	bcma_write32(mcore->core, offset, value);
	82	}
	83
	84	static const u32 ipsflag_irq_mask[] = {
	85	0,
	86	BCMA_MIPS_IPSFLAG_IRQ1,
	87	BCMA_MIPS_IPSFLAG_IRQ2,
	88	BCMA_MIPS_IPSFLAG_IRQ3,
	89	BCMA_MIPS_IPSFLAG_IRQ4,
	90	};
	91
	92	static const u32 ipsflag_irq_shift[] = {
	93	0,
	94	BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
	95	BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
	96	BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
	97	BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
	98	};
	99
	100	static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
	101	{
	102	u32 flag;
	103
	104	if (bcma_core_mips_bcm47162a0_quirk(dev))
	105	return dev->core_index;
	106	if (bcma_core_mips_bcm5357b0_quirk(dev))
	107	return dev->core_index;
	108	flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
	109
db5230d1 HM	110	if (flag)
	111	return flag & 0x1F;
	112	else
	113	return 0x3f;
21e0534a HM	114	}
	115
	116	/* Get the MIPS IRQ assignment for a specified device.
	117	* If unassigned, 0 is returned.
db5230d1 HM	118	* If disabled, 5 is returned.
db5230d1 HM	119	* If not supported, 6 is returned.
21e0534a	120	*/
85eb92e8	121	unsigned int bcma_core_mips_irq(struct bcma_device *dev)
21e0534a HM	122	{
	123	struct bcma_device *mdev = dev->bus->drv_mips.core;
	124	u32 irqflag;
	125	unsigned int irq;
	126
	127	irqflag = bcma_core_mips_irqflag(dev);
db5230d1 HM	128	if (irqflag == 0x3f)
db5230d1 HM	129	return 6;
21e0534a	130
db5230d1	131	for (irq = 0; irq <= 4; irq++)
21e0534a HM	132	if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
	133	(1 << irqflag))
	134	return irq;
	135
db5230d1	136	return 5;
21e0534a	137	}
e2aa19fa	138
21e0534a HM	139	static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
	140	{
	141	unsigned int oldirq = bcma_core_mips_irq(dev);
	142	struct bcma_bus *bus = dev->bus;
	143	struct bcma_device *mdev = bus->drv_mips.core;
	144	u32 irqflag;
	145
	146	irqflag = bcma_core_mips_irqflag(dev);
	147	BUG_ON(oldirq == 6);
	148
	149	dev->irq = irq + 2;
	150
	151	/* clear the old irq */
	152	if (oldirq == 0)
	153	bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
	154	bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
	155	~(1 << irqflag));
db5230d1	156	else if (oldirq != 5)
cbbc0138	157	bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
21e0534a HM	158
	159	/* assign the new one */
	160	if (irq == 0) {
	161	bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
	162	bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) \|
	163	(1 << irqflag));
	164	} else {
6ba1eafe HM	165	u32 irqinitmask = bcma_read32(mdev,
	166	BCMA_MIPS_MIPS74K_INTMASK(irq));
	167	if (irqinitmask) {
21e0534a HM	168	struct bcma_device *core;
	169
	170	/* backplane irq line is in use, find out who uses
	171	* it and set user to irq 0
	172	*/
d8f1bd2f	173	list_for_each_entry(core, &bus->cores, list) {
21e0534a	174	if ((1 << bcma_core_mips_irqflag(core)) ==
6ba1eafe	175	irqinitmask) {
21e0534a HM	176	bcma_core_mips_set_irq(core, 0);
	177	break;
	178	}
	179	}
	180	}
	181	bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
	182	1 << irqflag);
	183	}
	184
7401cb63	185	bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
db5230d1	186	dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
21e0534a HM	187	}
21e0534a HM	188
e3f05a42 HM	189	static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
	190	u16 coreid, u8 unit)
	191	{
	192	struct bcma_device *core;
	193
	194	core = bcma_find_core_unit(bus, coreid, unit);
	195	if (!core) {
	196	bcma_warn(bus,
	197	"Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
	198	coreid, unit);
	199	return;
	200	}
	201
	202	bcma_core_mips_set_irq(core, irq);
	203	}
	204
21e0534a HM	205	static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
	206	{
	207	int i;
	208	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
7401cb63	209	printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
21e0534a HM	210	for (i = 0; i <= 6; i++)
	211	printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
	212	printk("\n");
	213	}
	214
	215	static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
	216	{
	217	struct bcma_device *core;
	218
d8f1bd2f	219	list_for_each_entry(core, &bus->cores, list) {
21e0534a HM	220	bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
	221	}
	222	}
	223
908debc8 HM	224	u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
	225	{
	226	struct bcma_bus *bus = mcore->core->bus;
	227
	228	if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
5b5ac414	229	return bcma_pmu_get_cpu_clock(&bus->drv_cc);
908debc8	230
3d9d8af3	231	bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
908debc8 HM	232	return 0;
	233	}
	234	EXPORT_SYMBOL(bcma_cpu_clock);
	235
87fed556 RM	236	static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
	237	{
	238	struct bcma_drv_cc *cc = &bus->drv_cc;
	239	u8 cc_rev = cc->core->id.rev;
	240
	241	if (cc_rev == 42) {
	242	struct bcma_device *core;
	243
	244	core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
	245	if (core) {
	246	switch (bcma_aread32(core, BCMA_IOST) &
	247	BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
	248	case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
	249	return BCMA_BOOT_DEV_SERIAL;
	250	case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
	251	return BCMA_BOOT_DEV_NAND;
	252	case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
	253	default:
	254	return BCMA_BOOT_DEV_ROM;
	255	}
	256	}
	257	} else {
	258	if (cc_rev == 38) {
	259	if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
	260	return BCMA_BOOT_DEV_NAND;
	261	else if (cc->status & BIT(5))
	262	return BCMA_BOOT_DEV_ROM;
	263	}
	264
	265	if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
	266	BCMA_CC_FLASHT_PARA)
	267	return BCMA_BOOT_DEV_PARALLEL;
	268	else
	269	return BCMA_BOOT_DEV_SERIAL;
	270	}
	271
	272	return BCMA_BOOT_DEV_SERIAL;
	273	}
	274
21e0534a HM	275	static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
	276	{
	277	struct bcma_bus *bus = mcore->core->bus;
3c25ddd9	278	struct bcma_drv_cc *cc = &bus->drv_cc;
73e4dbe4	279	struct bcma_pflash *pflash = &cc->pflash;
87fed556	280	enum bcma_boot_dev boot_dev;
21e0534a	281
3c25ddd9	282	switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
21e0534a HM	283	case BCMA_CC_FLASHT_STSER:
21e0534a HM	284	case BCMA_CC_FLASHT_ATSER:
23cb3b21	285	bcma_debug(bus, "Found serial flash\n");
3c25ddd9	286	bcma_sflash_init(cc);
21e0534a HM	287	break;
21e0534a HM	288	case BCMA_CC_FLASHT_PARA:
23cb3b21	289	bcma_debug(bus, "Found parallel flash\n");
73e4dbe4 RM	290	pflash->present = true;
	291	pflash->window = BCMA_SOC_FLASH2;
	292	pflash->window_size = BCMA_SOC_FLASH2_SZ;
21e0534a	293
3c25ddd9	294	if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
21e0534a	295	BCMA_CC_FLASH_CFG_DS) == 0)
73e4dbe4	296	pflash->buswidth = 1;
21e0534a	297	else
73e4dbe4 RM	298	pflash->buswidth = 2;
	299
	300	bcma_pflash_data.width = pflash->buswidth;
	301	bcma_pflash_resource.start = pflash->window;
	302	bcma_pflash_resource.end = pflash->window + pflash->window_size;
	303
21e0534a HM	304	break;
21e0534a HM	305	default:
23cb3b21 RM	306	bcma_err(bus, "Flash type not supported\n");
	307	}
	308
3c25ddd9	309	if (cc->core->id.rev == 38 \|\|
23cb3b21	310	bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
3c25ddd9	311	if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
23cb3b21	312	bcma_debug(bus, "Found NAND flash\n");
3c25ddd9	313	bcma_nflash_init(cc);
23cb3b21	314	}
21e0534a	315	}
87fed556 RM	316
	317	/* Determine flash type this SoC boots from */
	318	boot_dev = bcma_boot_dev(bus);
	319	switch (boot_dev) {
	320	case BCMA_BOOT_DEV_PARALLEL:
	321	case BCMA_BOOT_DEV_SERIAL:
7177efc5 RM	322	#ifdef CONFIG_BCM47XX
	323	bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH2,
	324	BCMA_SOC_FLASH2_SZ);
	325	#endif
87fed556 RM	326	break;
87fed556 RM	327	case BCMA_BOOT_DEV_NAND:
7177efc5 RM	328	#ifdef CONFIG_BCM47XX
	329	bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH1,
	330	BCMA_SOC_FLASH1_SZ);
	331	#endif
87fed556 RM	332	break;
	333	default:
	334	break;
	335	}
21e0534a HM	336	}
21e0534a HM	337
49655bb8 HM	338	void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
	339	{
	340	struct bcma_bus *bus = mcore->core->bus;
	341
	342	if (mcore->early_setup_done)
	343	return;
	344
	345	bcma_chipco_serial_init(&bus->drv_cc);
	346	bcma_core_mips_flash_detect(mcore);
	347
	348	mcore->early_setup_done = true;
	349	}
	350
6bf2e546 NH	351	static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
	352	{
	353	struct bcma_device cpu, pcie, *i2s;
	354
	355	/* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
	356	* (IRQ flags > 7 are ignored when setting the interrupt masks)
	357	*/
	358	if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
	359	bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
	360	return;
	361
	362	cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
	363	pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
	364	i2s = bcma_find_core(bus, BCMA_CORE_I2S);
	365	if (cpu && pcie && i2s &&
	366	bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
	367	bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
	368	bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
	369	bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
	370	bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
	371	bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
	372	bcma_debug(bus,
	373	"Moved i2s interrupt to oob line 7 instead of 8\n");
	374	}
	375	}
	376
21e0534a HM	377	void bcma_core_mips_init(struct bcma_drv_mips *mcore)
	378	{
	379	struct bcma_bus *bus;
	380	struct bcma_device *core;
	381	bus = mcore->core->bus;
	382
49655bb8 HM	383	if (mcore->setup_done)
	384	return;
	385
7401cb63	386	bcma_debug(bus, "Initializing MIPS core...\n");
21e0534a	387
49655bb8 HM	388	bcma_core_mips_early_init(mcore);
49655bb8 HM	389
6bf2e546 NH	390	bcma_fix_i2s_irqflag(bus);
6bf2e546 NH	391
e3f05a42 HM	392	switch (bus->chipinfo.id) {
	393	case BCMA_CHIP_ID_BCM4716:
	394	case BCMA_CHIP_ID_BCM4748:
	395	bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
	396	bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
	397	bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
	398	bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
	399	bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
	400	bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
	401	break;
	402	case BCMA_CHIP_ID_BCM5356:
	403	case BCMA_CHIP_ID_BCM47162:
	404	case BCMA_CHIP_ID_BCM53572:
	405	bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
	406	bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
	407	bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
	408	break;
	409	case BCMA_CHIP_ID_BCM5357:
	410	case BCMA_CHIP_ID_BCM4749:
	411	bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
	412	bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
	413	bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
	414	bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
	415	bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
	416	break;
	417	case BCMA_CHIP_ID_BCM4706:
	418	bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
	419	bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
	420	0);
	421	bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
	422	bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
	423	bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
	424	0);
	425	break;
	426	default:
	427	list_for_each_entry(core, &bus->cores, list) {
85eb92e8	428	core->irq = bcma_core_irq(core, 0);
21e0534a	429	}
e3f05a42 HM	430	bcma_err(bus,
	431	"Unknown device (0x%x) found, can not configure IRQs\n",
	432	bus->chipinfo.id);
21e0534a	433	}
7401cb63	434	bcma_debug(bus, "IRQ reconfiguration done\n");
21e0534a HM	435	bcma_core_mips_dump_irq(bus);
21e0534a HM	436
21e0534a HM	437	mcore->setup_done = true;
21e0534a HM	438	}