[linux.git] / drivers / char / xilinx_hwicap / xilinx_hwicap.h

/*****************************************************************************
 *
 *     Author: Xilinx, Inc.
 *
 *     This program is free software; you can redistribute it and/or modify it
 *     under the terms of the GNU General Public License as published by the
 *     Free Software Foundation; either version 2 of the License, or (at your
 *     option) any later version.
 *
 *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
 *     AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
 *     SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
 *     OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
 *     APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
 *     THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
 *     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
 *     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
 *     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
 *     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 *     FOR A PARTICULAR PURPOSE.
 *
 *     (c) Copyright 2003-2007 Xilinx Inc.
 *     All rights reserved.
 *
 *     You should have received a copy of the GNU General Public License along
 *     with this program; if not, write to the Free Software Foundation, Inc.,
 *     675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *****************************************************************************/

#ifndef XILINX_HWICAP_H_	/* prevent circular inclusions */
#define XILINX_HWICAP_H_	/* by using protection macros */

#include <linux/types.h>
#include <linux/cdev.h>
#include <linux/platform_device.h>

#include <asm/io.h>

struct hwicap_drvdata {
	u32 write_buffer_in_use;  /* Always in [0,3] */
	u8 write_buffer[4];
	u32 read_buffer_in_use;	  /* Always in [0,3] */
	u8 read_buffer[4];
	resource_size_t mem_start;/* phys. address of the control registers */
	resource_size_t mem_end;  /* phys. address of the control registers */
	resource_size_t mem_size;
	void __iomem *base_address;/* virt. address of the control registers */

	struct device *dev;
	struct cdev cdev;	/* Char device structure */
	dev_t devt;

	const struct hwicap_driver_config *config;
	const struct config_registers *config_regs;
	void *private_data;
	bool is_open;
	struct mutex sem;
};

struct hwicap_driver_config {
	/* Read configuration data given by size into the data buffer.
	   Return 0 if successful. */
	int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
			u32 size);
	/* Write configuration data given by size from the data buffer.
	   Return 0 if successful. */
	int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
			u32 size);
	/* Get the status register, bit pattern given by:
	 * D8 - 0 = configuration error
	 * D7 - 1 = alignment found
	 * D6 - 1 = readback in progress
	 * D5 - 0 = abort in progress
	 * D4 - Always 1
	 * D3 - Always 1
	 * D2 - Always 1
	 * D1 - Always 1
	 * D0 - 1 = operation completed
	 */
	u32 (*get_status)(struct hwicap_drvdata *drvdata);
	/* Reset the hw */
	void (*reset)(struct hwicap_drvdata *drvdata);
};

/* Number of times to poll the done regsiter */
#define XHI_MAX_RETRIES     10

/************ Constant Definitions *************/

#define XHI_PAD_FRAMES              0x1

/* Mask for calculating configuration packet headers */
#define XHI_WORD_COUNT_MASK_TYPE_1  0x7FFUL
#define XHI_WORD_COUNT_MASK_TYPE_2  0x1FFFFFUL
#define XHI_TYPE_MASK               0x7
#define XHI_REGISTER_MASK           0xF
#define XHI_OP_MASK                 0x3

#define XHI_TYPE_SHIFT              29
#define XHI_REGISTER_SHIFT          13
#define XHI_OP_SHIFT                27

#define XHI_TYPE_1                  1
#define XHI_TYPE_2                  2
#define XHI_OP_WRITE                2
#define XHI_OP_READ                 1

/* Address Block Types */
#define XHI_FAR_CLB_BLOCK           0
#define XHI_FAR_BRAM_BLOCK          1
#define XHI_FAR_BRAM_INT_BLOCK      2

struct config_registers {
	u32 CRC;
	u32 FAR;
	u32 FDRI;
	u32 FDRO;
	u32 CMD;
	u32 CTL;
	u32 MASK;
	u32 STAT;
	u32 LOUT;
	u32 COR;
	u32 MFWR;
	u32 FLR;
	u32 KEY;
	u32 CBC;
	u32 IDCODE;
	u32 AXSS;
	u32 C0R_1;
	u32 CSOB;
	u32 WBSTAR;
	u32 TIMER;
	u32 BOOTSTS;
	u32 CTL_1;
};

/* Configuration Commands */
#define XHI_CMD_NULL                0
#define XHI_CMD_WCFG                1
#define XHI_CMD_MFW                 2
#define XHI_CMD_DGHIGH              3
#define XHI_CMD_RCFG                4
#define XHI_CMD_START               5
#define XHI_CMD_RCAP                6
#define XHI_CMD_RCRC                7
#define XHI_CMD_AGHIGH              8
#define XHI_CMD_SWITCH              9
#define XHI_CMD_GRESTORE            10
#define XHI_CMD_SHUTDOWN            11
#define XHI_CMD_GCAPTURE            12
#define XHI_CMD_DESYNCH             13
#define XHI_CMD_IPROG               15 /* Only in Virtex5 */
#define XHI_CMD_CRCC                16 /* Only in Virtex5 */
#define XHI_CMD_LTIMER              17 /* Only in Virtex5 */

/* Packet constants */
#define XHI_SYNC_PACKET             0xAA995566UL
#define XHI_DUMMY_PACKET            0xFFFFFFFFUL
#define XHI_NOOP_PACKET             (XHI_TYPE_1 << XHI_TYPE_SHIFT)
#define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
			(XHI_OP_READ << XHI_OP_SHIFT))

#define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
			(XHI_OP_WRITE << XHI_OP_SHIFT))

#define XHI_TYPE2_CNT_MASK          0x07FFFFFF

#define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL
#define XHI_TYPE_1_HEADER_BYTES     4
#define XHI_TYPE_2_HEADER_BYTES     8

/* Constant to use for CRC check when CRC has been disabled */
#define XHI_DISABLED_AUTO_CRC       0x0000DEFCUL

/* Meanings of the bits returned by get_status */
#define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */
#define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */
#define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */
#define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */
#define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask  */

/**
 * hwicap_type_1_read - Generates a Type 1 read packet header.
 * @reg: is the address of the register to be read back.
 *
 * Generates a Type 1 read packet header, which is used to indirectly
 * read registers in the configuration logic.  This packet must then
 * be sent through the icap device, and a return packet received with
 * the information.
 **/
static inline u32 hwicap_type_1_read(u32 reg)
{
	return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
		(reg << XHI_REGISTER_SHIFT) |
		(XHI_OP_READ << XHI_OP_SHIFT);
}

/**
 * hwicap_type_1_write - Generates a Type 1 write packet header
 * @reg: is the address of the register to be read back.
 **/
static inline u32 hwicap_type_1_write(u32 reg)
{
	return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
		(reg << XHI_REGISTER_SHIFT) |
		(XHI_OP_WRITE << XHI_OP_SHIFT);
}

#endif
Commit	Line	Data
ef141a0b SN	1	/*****************************************************************************
	2	*
	3	* Author: Xilinx, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
	11	* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
	12	* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
	13	* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
	14	* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
	15	* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
	16	* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
	17	* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
	18	* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
	19	* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
	20	* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
	21	* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
	22	* FOR A PARTICULAR PURPOSE.
	23	*
ef141a0b SN	24	* (c) Copyright 2003-2007 Xilinx Inc.
	25	* All rights reserved.
	26	*
	27	* You should have received a copy of the GNU General Public License along
	28	* with this program; if not, write to the Free Software Foundation, Inc.,
	29	* 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*
	31	*****************************************************************************/
	32
	33	#ifndef XILINX_HWICAP_H_ /* prevent circular inclusions */
	34	#define XILINX_HWICAP_H_ /* by using protection macros */
	35
	36	#include <linux/types.h>
	37	#include <linux/cdev.h>
ef141a0b SN	38	#include <linux/platform_device.h>
	39
	40	#include <asm/io.h>
	41
	42	struct hwicap_drvdata {
	43	u32 write_buffer_in_use; /* Always in [0,3] */
	44	u8 write_buffer[4];
	45	u32 read_buffer_in_use; /* Always in [0,3] */
	46	u8 read_buffer[4];
f62f2fdd SN	47	resource_size_t mem_start;/* phys. address of the control registers */
	48	resource_size_t mem_end; /* phys. address of the control registers */
	49	resource_size_t mem_size;
ef141a0b SN	50	void __iomem base_address;/ virt. address of the control registers */
	51
	52	struct device *dev;
	53	struct cdev cdev; /* Char device structure */
	54	dev_t devt;
	55
	56	const struct hwicap_driver_config *config;
	57	const struct config_registers *config_regs;
	58	void *private_data;
	59	bool is_open;
f62f2fdd	60	struct mutex sem;
ef141a0b SN	61	};
	62
	63	struct hwicap_driver_config {
6b06fdba SN	64	/* Read configuration data given by size into the data buffer.
6b06fdba SN	65	Return 0 if successful. */
ef141a0b SN	66	int (get_configuration)(struct hwicap_drvdata drvdata, u32 *data,
ef141a0b SN	67	u32 size);
6b06fdba SN	68	/* Write configuration data given by size from the data buffer.
6b06fdba SN	69	Return 0 if successful. */
ef141a0b SN	70	int (set_configuration)(struct hwicap_drvdata drvdata, u32 *data,
ef141a0b SN	71	u32 size);
6b06fdba SN	72	/* Get the status register, bit pattern given by:
	73	* D8 - 0 = configuration error
	74	* D7 - 1 = alignment found
	75	* D6 - 1 = readback in progress
	76	* D5 - 0 = abort in progress
	77	* D4 - Always 1
	78	* D3 - Always 1
	79	* D2 - Always 1
	80	* D1 - Always 1
	81	* D0 - 1 = operation completed
	82	*/
	83	u32 (get_status)(struct hwicap_drvdata drvdata);
	84	/* Reset the hw */
ef141a0b SN	85	void (reset)(struct hwicap_drvdata drvdata);
	86	};
	87
	88	/* Number of times to poll the done regsiter */
	89	#define XHI_MAX_RETRIES 10
	90
	91	/********** Constant Definitions ***********/
	92
	93	#define XHI_PAD_FRAMES 0x1
	94
	95	/* Mask for calculating configuration packet headers */
	96	#define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL
	97	#define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL
	98	#define XHI_TYPE_MASK 0x7
	99	#define XHI_REGISTER_MASK 0xF
	100	#define XHI_OP_MASK 0x3
	101
	102	#define XHI_TYPE_SHIFT 29
	103	#define XHI_REGISTER_SHIFT 13
	104	#define XHI_OP_SHIFT 27
	105
	106	#define XHI_TYPE_1 1
	107	#define XHI_TYPE_2 2
	108	#define XHI_OP_WRITE 2
	109	#define XHI_OP_READ 1
	110
	111	/* Address Block Types */
	112	#define XHI_FAR_CLB_BLOCK 0
	113	#define XHI_FAR_BRAM_BLOCK 1
	114	#define XHI_FAR_BRAM_INT_BLOCK 2
	115
	116	struct config_registers {
	117	u32 CRC;
	118	u32 FAR;
	119	u32 FDRI;
	120	u32 FDRO;
	121	u32 CMD;
	122	u32 CTL;
	123	u32 MASK;
	124	u32 STAT;
	125	u32 LOUT;
	126	u32 COR;
	127	u32 MFWR;
	128	u32 FLR;
	129	u32 KEY;
	130	u32 CBC;
	131	u32 IDCODE;
	132	u32 AXSS;
	133	u32 C0R_1;
	134	u32 CSOB;
	135	u32 WBSTAR;
	136	u32 TIMER;
	137	u32 BOOTSTS;
	138	u32 CTL_1;
	139	};
	140
	141	/* Configuration Commands */
	142	#define XHI_CMD_NULL 0
	143	#define XHI_CMD_WCFG 1
	144	#define XHI_CMD_MFW 2
	145	#define XHI_CMD_DGHIGH 3
	146	#define XHI_CMD_RCFG 4
	147	#define XHI_CMD_START 5
	148	#define XHI_CMD_RCAP 6
149	#define XHI_CMD_RCRC 7
150	#define XHI_CMD_AGHIGH 8
151	#define XHI_CMD_SWITCH 9
152	#define XHI_CMD_GRESTORE 10
153	#define XHI_CMD_SHUTDOWN 11
154	#define XHI_CMD_GCAPTURE 12
155	#define XHI_CMD_DESYNCH 13
156	#define XHI_CMD_IPROG 15 /* Only in Virtex5 */
157	#define XHI_CMD_CRCC 16 /* Only in Virtex5 */
158	#define XHI_CMD_LTIMER 17 /* Only in Virtex5 */
159
160	/* Packet constants */
161	#define XHI_SYNC_PACKET 0xAA995566UL
162	#define XHI_DUMMY_PACKET 0xFFFFFFFFUL
163	#define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT)
164	#define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) \| \
165	(XHI_OP_READ << XHI_OP_SHIFT))
166
167	#define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) \| \
168	(XHI_OP_WRITE << XHI_OP_SHIFT))
169
170	#define XHI_TYPE2_CNT_MASK 0x07FFFFFF
171
172	#define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL
173	#define XHI_TYPE_1_HEADER_BYTES 4
174	#define XHI_TYPE_2_HEADER_BYTES 8
175
176	/* Constant to use for CRC check when CRC has been disabled */
177	#define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL
178
6b06fdba SN	179	/* Meanings of the bits returned by get_status */
	180	#define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */
	181	#define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */
	182	#define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */
	183	#define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */
	184	#define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask */
	185
ef141a0b	186	/**
f62f2fdd SN	187	* hwicap_type_1_read - Generates a Type 1 read packet header.
f62f2fdd SN	188	* @reg: is the address of the register to be read back.
ef141a0b SN	189	*
	190	* Generates a Type 1 read packet header, which is used to indirectly
	191	* read registers in the configuration logic. This packet must then
	192	* be sent through the icap device, and a return packet received with
	193	* the information.
	194	**/
f62f2fdd	195	static inline u32 hwicap_type_1_read(u32 reg)
ef141a0b SN	196	{
ef141a0b SN	197	return (XHI_TYPE_1 << XHI_TYPE_SHIFT) \|
f62f2fdd	198	(reg << XHI_REGISTER_SHIFT) \|
ef141a0b SN	199	(XHI_OP_READ << XHI_OP_SHIFT);
	200	}
	201
	202	/**
f62f2fdd SN	203	* hwicap_type_1_write - Generates a Type 1 write packet header
f62f2fdd SN	204	* @reg: is the address of the register to be read back.
ef141a0b	205	**/
f62f2fdd	206	static inline u32 hwicap_type_1_write(u32 reg)
ef141a0b SN	207	{
ef141a0b SN	208	return (XHI_TYPE_1 << XHI_TYPE_SHIFT) \|
f62f2fdd	209	(reg << XHI_REGISTER_SHIFT) \|
ef141a0b SN	210	(XHI_OP_WRITE << XHI_OP_SHIFT);
	211	}
	212
	213	#endif