[linux.git] / drivers / rtc / rtc-x1205.c

/*
 * An i2c driver for the Xicor/Intersil X1205 RTC
 * Copyright 2004 Karen Spearel
 * Copyright 2005 Alessandro Zummo
 *
 * please send all reports to:
 * 	Karen Spearel <kas111 at gmail dot com>
 *	Alessandro Zummo <[email protected]>
 *
 * based on a lot of other RTC drivers.
 *
 * Information and datasheet:
 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/delay.h>
#include <linux/module.h>

#define DRV_VERSION "1.0.8"

/* offsets into CCR area */

#define CCR_SEC			0
#define CCR_MIN			1
#define CCR_HOUR		2
#define CCR_MDAY		3
#define CCR_MONTH		4
#define CCR_YEAR		5
#define CCR_WDAY		6
#define CCR_Y2K			7

#define X1205_REG_SR		0x3F	/* status register */
#define X1205_REG_Y2K		0x37
#define X1205_REG_DW		0x36
#define X1205_REG_YR		0x35
#define X1205_REG_MO		0x34
#define X1205_REG_DT		0x33
#define X1205_REG_HR		0x32
#define X1205_REG_MN		0x31
#define X1205_REG_SC		0x30
#define X1205_REG_DTR		0x13
#define X1205_REG_ATR		0x12
#define X1205_REG_INT		0x11
#define X1205_REG_0		0x10
#define X1205_REG_Y2K1		0x0F
#define X1205_REG_DWA1		0x0E
#define X1205_REG_YRA1		0x0D
#define X1205_REG_MOA1		0x0C
#define X1205_REG_DTA1		0x0B
#define X1205_REG_HRA1		0x0A
#define X1205_REG_MNA1		0x09
#define X1205_REG_SCA1		0x08
#define X1205_REG_Y2K0		0x07
#define X1205_REG_DWA0		0x06
#define X1205_REG_YRA0		0x05
#define X1205_REG_MOA0		0x04
#define X1205_REG_DTA0		0x03
#define X1205_REG_HRA0		0x02
#define X1205_REG_MNA0		0x01
#define X1205_REG_SCA0		0x00

#define X1205_CCR_BASE		0x30	/* Base address of CCR */
#define X1205_ALM0_BASE		0x00	/* Base address of ALARM0 */

#define X1205_SR_RTCF		0x01	/* Clock failure */
#define X1205_SR_WEL		0x02	/* Write Enable Latch */
#define X1205_SR_RWEL		0x04	/* Register Write Enable */
#define X1205_SR_AL0		0x20	/* Alarm 0 match */

#define X1205_DTR_DTR0		0x01
#define X1205_DTR_DTR1		0x02
#define X1205_DTR_DTR2		0x04

#define X1205_HR_MIL		0x80	/* Set in ccr.hour for 24 hr mode */

#define X1205_INT_AL0E		0x20	/* Alarm 0 enable */

static struct i2c_driver x1205_driver;

/*
 * In the routines that deal directly with the x1205 hardware, we use
 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
 * Epoch is initialized as 2000. Time is set to UTC.
 */
static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm,
				unsigned char reg_base)
{
	unsigned char dt_addr[2] = { 0, reg_base };
	unsigned char buf[8];
	int i;

	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, dt_addr },	/* setup read ptr */
		{ client->addr, I2C_M_RD, 8, buf },	/* read date */
	};

	/* read date registers */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev,
		"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
		"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
		__func__,
		buf[0], buf[1], buf[2], buf[3],
		buf[4], buf[5], buf[6], buf[7]);

	/* Mask out the enable bits if these are alarm registers */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] &= 0x7F;

	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	tm->tm_year = bcd2bin(buf[CCR_YEAR])
			+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
	tm->tm_wday = buf[CCR_WDAY];

	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
		"mday=%d, mon=%d, year=%d, wday=%d\n",
		__func__,
		tm->tm_sec, tm->tm_min, tm->tm_hour,
		tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return 0;
}

static int x1205_get_status(struct i2c_client *client, unsigned char *sr)
{
	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };

	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, sr_addr },	/* setup read ptr */
		{ client->addr, I2C_M_RD, 1, sr },	/* read status */
	};

	/* read status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	return 0;
}

static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm,
			u8 reg_base, unsigned char alm_enable)
{
	int i, xfer;
	unsigned char rdata[10] = { 0, reg_base };
	unsigned char *buf = rdata + 2;

	static const unsigned char wel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL };

	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL | X1205_SR_RWEL };

	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };

	dev_dbg(&client->dev,
		"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
		__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
		tm->tm_mon, tm->tm_year, tm->tm_wday);

	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
	buf[CCR_MIN] = bin2bcd(tm->tm_min);

	/* set hour and 24hr bit */
	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;

	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);

	/* month, 1 - 12 */
	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);

	/* year, since the rtc epoch*/
	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);

	/* If writing alarm registers, set compare bits on registers 0-4 */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] |= 0x80;

	/* this sequence is required to unlock the chip */
	if ((xfer = i2c_master_send(client, wel, 3)) != 3) {
		dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
		return -EIO;
	}

	if ((xfer = i2c_master_send(client, rwel, 3)) != 3) {
		dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
		return -EIO;
	}

	xfer = i2c_master_send(client, rdata, sizeof(rdata));
	if (xfer != sizeof(rdata)) {
		dev_err(&client->dev,
			"%s: result=%d addr=%02x, data=%02x\n",
			__func__,
			 xfer, rdata[1], rdata[2]);
		return -EIO;
	}

	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	if (reg_base < X1205_CCR_BASE) {
		unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };

		msleep(10);

		/* ...and set or clear the AL0E bit in the INT register */

		/* Need to set RWEL again as the write has cleared it */
		xfer = i2c_master_send(client, rwel, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: aloe rwel - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		if (alm_enable)
			al0e[2] = X1205_INT_AL0E;

		xfer = i2c_master_send(client, al0e, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: al0e - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		/* and wait 10msec again for this write to complete */
		msleep(10);
	}

	/* disable further writes */
	if ((xfer = i2c_master_send(client, diswe, 3)) != 3) {
		dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
		return -EIO;
	}

	return 0;
}

static int x1205_fix_osc(struct i2c_client *client)
{
	int err;
	struct rtc_time tm;

	memset(&tm, 0, sizeof(tm));

	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
	if (err < 0)
		dev_err(&client->dev, "unable to restart the oscillator\n");

	return err;
}

static int x1205_get_dtrim(struct i2c_client *client, int *trim)
{
	unsigned char dtr;
	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };

	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, dtr_addr },	/* setup read ptr */
		{ client->addr, I2C_M_RD, 1, &dtr }, 	/* read dtr */
	};

	/* read dtr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);

	*trim = 0;

	if (dtr & X1205_DTR_DTR0)
		*trim += 20;

	if (dtr & X1205_DTR_DTR1)
		*trim += 10;

	if (dtr & X1205_DTR_DTR2)
		*trim = -*trim;

	return 0;
}

static int x1205_get_atrim(struct i2c_client *client, int *trim)
{
	s8 atr;
	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };

	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, atr_addr },	/* setup read ptr */
		{ client->addr, I2C_M_RD, 1, &atr }, 	/* read atr */
	};

	/* read atr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);

	/* atr is a two's complement value on 6 bits,
	 * perform sign extension. The formula is
	 * Catr = (atr * 0.25pF) + 11.00pF.
	 */
	if (atr & 0x20)
		atr |= 0xC0;

	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);

	*trim = (atr * 250) + 11000;

	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);

	return 0;
}

struct x1205_limit
{
	unsigned char reg, mask, min, max;
};

static int x1205_validate_client(struct i2c_client *client)
{
	int i, xfer;

	/* Probe array. We will read the register at the specified
	 * address and check if the given bits are zero.
	 */
	static const unsigned char probe_zero_pattern[] = {
		/* register, mask */
		X1205_REG_SR,	0x18,
		X1205_REG_DTR,	0xF8,
		X1205_REG_ATR,	0xC0,
		X1205_REG_INT,	0x18,
		X1205_REG_0,	0xFF,
	};

	static const struct x1205_limit probe_limits_pattern[] = {
		/* register, mask, min, max */
		{ X1205_REG_Y2K,	0xFF,	19,	20	},
		{ X1205_REG_DW,		0xFF,	0,	6	},
		{ X1205_REG_YR,		0xFF,	0,	99	},
		{ X1205_REG_MO,		0xFF,	0,	12	},
		{ X1205_REG_DT,		0xFF,	0,	31	},
		{ X1205_REG_HR,		0x7F,	0,	23	},
		{ X1205_REG_MN,		0xFF,	0,	59	},
		{ X1205_REG_SC,		0xFF,	0,	59	},
		{ X1205_REG_Y2K1,	0xFF,	19,	20	},
		{ X1205_REG_Y2K0,	0xFF,	19,	20	},
	};

	/* check that registers have bits a 0 where expected */
	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
		unsigned char buf;

		unsigned char addr[2] = { 0, probe_zero_pattern[i] };

		struct i2c_msg msgs[2] = {
			{ client->addr, 0, 2, addr },
			{ client->addr, I2C_M_RD, 1, &buf },
		};

		if ((xfer = i2c_transfer(client->adapter, msgs, 2)) != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_zero_pattern[i]);

			return -EIO;
		}

		if ((buf & probe_zero_pattern[i+1]) != 0) {
			dev_err(&client->dev,
				"%s: register=%02x, zero pattern=%d, value=%x\n",
				__func__, probe_zero_pattern[i], i, buf);

			return -ENODEV;
		}
	}

	/* check limits (only registers with bcd values) */
	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
		unsigned char reg, value;

		unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };

		struct i2c_msg msgs[2] = {
			{ client->addr, 0, 2, addr },
			{ client->addr, I2C_M_RD, 1, &reg },
		};

		if ((xfer = i2c_transfer(client->adapter, msgs, 2)) != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_limits_pattern[i].reg);

			return -EIO;
		}

		value = bcd2bin(reg & probe_limits_pattern[i].mask);

		if (value > probe_limits_pattern[i].max ||
			value < probe_limits_pattern[i].min) {
			dev_dbg(&client->dev,
				"%s: register=%x, lim pattern=%d, value=%d\n",
				__func__, probe_limits_pattern[i].reg,
				i, value);

			return -ENODEV;
		}
	}

	return 0;
}

static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int err;
	unsigned char intreg, status;
	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	struct i2c_client *client = to_i2c_client(dev);
	struct i2c_msg msgs[] = {
		{ client->addr, 0, 2, int_addr },        /* setup read ptr */
		{ client->addr, I2C_M_RD, 1, &intreg },  /* read INT register */
	};

	/* read interrupt register and status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}
	err = x1205_get_status(client, &status);
	if (err == 0) {
		alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
		alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
		err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	}
	return err;
}

static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		&alrm->time, X1205_ALM0_BASE, alrm->enabled);
}

static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_get_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE);
}

static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE, 0);
}

static int x1205_rtc_proc(struct device *dev, struct seq_file *seq)
{
	int err, dtrim, atrim;

	if ((err = x1205_get_dtrim(to_i2c_client(dev), &dtrim)) == 0)
		seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);

	if ((err = x1205_get_atrim(to_i2c_client(dev), &atrim)) == 0)
		seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
			atrim / 1000, atrim % 1000);
	return 0;
}

static const struct rtc_class_ops x1205_rtc_ops = {
	.proc		= x1205_rtc_proc,
	.read_time	= x1205_rtc_read_time,
	.set_time	= x1205_rtc_set_time,
	.read_alarm	= x1205_rtc_read_alarm,
	.set_alarm	= x1205_rtc_set_alarm,
};

static ssize_t x1205_sysfs_show_atrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, atrim;

	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	if (err)
		return err;

	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
}
static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);

static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, dtrim;

	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	if (err)
		return err;

	return sprintf(buf, "%d ppm\n", dtrim);
}
static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);

static int x1205_sysfs_register(struct device *dev)
{
	int err;

	err = device_create_file(dev, &dev_attr_atrim);
	if (err)
		return err;

	err = device_create_file(dev, &dev_attr_dtrim);
	if (err)
		device_remove_file(dev, &dev_attr_atrim);

	return err;
}

static void x1205_sysfs_unregister(struct device *dev)
{
	device_remove_file(dev, &dev_attr_atrim);
	device_remove_file(dev, &dev_attr_dtrim);
}


static int x1205_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	int err = 0;
	unsigned char sr;
	struct rtc_device *rtc;

	dev_dbg(&client->dev, "%s\n", __func__);

	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
		return -ENODEV;

	if (x1205_validate_client(client) < 0)
		return -ENODEV;

	dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n");

	rtc = rtc_device_register(x1205_driver.driver.name, &client->dev,
				&x1205_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	i2c_set_clientdata(client, rtc);

	/* Check for power failures and eventually enable the osc */
	if ((err = x1205_get_status(client, &sr)) == 0) {
		if (sr & X1205_SR_RTCF) {
			dev_err(&client->dev,
				"power failure detected, "
				"please set the clock\n");
			udelay(50);
			x1205_fix_osc(client);
		}
	}
	else
		dev_err(&client->dev, "couldn't read status\n");

	err = x1205_sysfs_register(&client->dev);
	if (err)
		goto exit_devreg;

	return 0;

exit_devreg:
	rtc_device_unregister(rtc);

	return err;
}

static int x1205_remove(struct i2c_client *client)
{
	struct rtc_device *rtc = i2c_get_clientdata(client);

	rtc_device_unregister(rtc);
	x1205_sysfs_unregister(&client->dev);
	return 0;
}

static const struct i2c_device_id x1205_id[] = {
	{ "x1205", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, x1205_id);

static struct i2c_driver x1205_driver = {
	.driver		= {
		.name	= "rtc-x1205",
	},
	.probe		= x1205_probe,
	.remove		= x1205_remove,
	.id_table	= x1205_id,
};

module_i2c_driver(x1205_driver);

MODULE_AUTHOR(
	"Karen Spearel <kas111 at gmail dot com>, "
	"Alessandro Zummo <[email protected]>");
MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
1fec7c66 AZ	1	/*
	2	* An i2c driver for the Xicor/Intersil X1205 RTC
	3	* Copyright 2004 Karen Spearel
	4	* Copyright 2005 Alessandro Zummo
	5	*
	6	* please send all reports to:
	7	* Karen Spearel <kas111 at gmail dot com>
	8	* Alessandro Zummo <[email protected]>
	9	*
	10	* based on a lot of other RTC drivers.
	11	*
890e0375 JD	12	* Information and datasheet:
	13	* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
	14	*
1fec7c66 AZ	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include <linux/i2c.h>
	21	#include <linux/bcd.h>
	22	#include <linux/rtc.h>
	23	#include <linux/delay.h>
2113852b	24	#include <linux/module.h>
1fec7c66	25
4edac2b4	26	#define DRV_VERSION "1.0.8"
1fec7c66 AZ	27
	28	/* offsets into CCR area */
	29
	30	#define CCR_SEC 0
	31	#define CCR_MIN 1
	32	#define CCR_HOUR 2
	33	#define CCR_MDAY 3
	34	#define CCR_MONTH 4
	35	#define CCR_YEAR 5
	36	#define CCR_WDAY 6
	37	#define CCR_Y2K 7
	38
	39	#define X1205_REG_SR 0x3F /* status register */
	40	#define X1205_REG_Y2K 0x37
	41	#define X1205_REG_DW 0x36
	42	#define X1205_REG_YR 0x35
	43	#define X1205_REG_MO 0x34
	44	#define X1205_REG_DT 0x33
	45	#define X1205_REG_HR 0x32
	46	#define X1205_REG_MN 0x31
	47	#define X1205_REG_SC 0x30
	48	#define X1205_REG_DTR 0x13
	49	#define X1205_REG_ATR 0x12
	50	#define X1205_REG_INT 0x11
	51	#define X1205_REG_0 0x10
	52	#define X1205_REG_Y2K1 0x0F
	53	#define X1205_REG_DWA1 0x0E
	54	#define X1205_REG_YRA1 0x0D
	55	#define X1205_REG_MOA1 0x0C
	56	#define X1205_REG_DTA1 0x0B
	57	#define X1205_REG_HRA1 0x0A
	58	#define X1205_REG_MNA1 0x09
	59	#define X1205_REG_SCA1 0x08
	60	#define X1205_REG_Y2K0 0x07
	61	#define X1205_REG_DWA0 0x06
	62	#define X1205_REG_YRA0 0x05
	63	#define X1205_REG_MOA0 0x04
	64	#define X1205_REG_DTA0 0x03
	65	#define X1205_REG_HRA0 0x02
	66	#define X1205_REG_MNA0 0x01
	67	#define X1205_REG_SCA0 0x00
	68
	69	#define X1205_CCR_BASE 0x30 /* Base address of CCR */
	70	#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
	71
	72	#define X1205_SR_RTCF 0x01 /* Clock failure */
	73	#define X1205_SR_WEL 0x02 /* Write Enable Latch */
	74	#define X1205_SR_RWEL 0x04 /* Register Write Enable */
471d47e3	75	#define X1205_SR_AL0 0x20 /* Alarm 0 match */
1fec7c66 AZ	76
	77	#define X1205_DTR_DTR0 0x01
	78	#define X1205_DTR_DTR1 0x02
	79	#define X1205_DTR_DTR2 0x04
	80
	81	#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
	82
471d47e3 MH	83	#define X1205_INT_AL0E 0x20 /* Alarm 0 enable */
471d47e3 MH	84
4edac2b4	85	static struct i2c_driver x1205_driver;
1fec7c66 AZ	86
	87	/*
	88	* In the routines that deal directly with the x1205 hardware, we use
	89	* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
	90	* Epoch is initialized as 2000. Time is set to UTC.
	91	*/
	92	static int x1205_get_datetime(struct i2c_client client, struct rtc_time tm,
	93	unsigned char reg_base)
	94	{
	95	unsigned char dt_addr[2] = { 0, reg_base };
1fec7c66	96	unsigned char buf[8];
471d47e3	97	int i;
1fec7c66 AZ	98
	99	struct i2c_msg msgs[] = {
	100	{ client->addr, 0, 2, dt_addr }, /* setup read ptr */
	101	{ client->addr, I2C_M_RD, 8, buf }, /* read date */
	102	};
	103
	104	/* read date registers */
471d47e3	105	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	106	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	107	return -EIO;
	108	}
	109
	110	dev_dbg(&client->dev,
	111	"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	112	"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
2a4e2b87	113	__func__,
1fec7c66 AZ	114	buf[0], buf[1], buf[2], buf[3],
	115	buf[4], buf[5], buf[6], buf[7]);
	116
471d47e3 MH	117	/* Mask out the enable bits if these are alarm registers */
	118	if (reg_base < X1205_CCR_BASE)
	119	for (i = 0; i <= 4; i++)
	120	buf[i] &= 0x7F;
	121
fe20ba70 AB	122	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	123	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	124	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	125	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	126	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	127	tm->tm_year = bcd2bin(buf[CCR_YEAR])
	128	+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
1fec7c66 AZ	129	tm->tm_wday = buf[CCR_WDAY];
	130
	131	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	132	"mday=%d, mon=%d, year=%d, wday=%d\n",
2a4e2b87	133	__func__,
1fec7c66 AZ	134	tm->tm_sec, tm->tm_min, tm->tm_hour,
	135	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	136
	137	return 0;
	138	}
	139
	140	static int x1205_get_status(struct i2c_client client, unsigned char sr)
	141	{
	142	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };
	143
	144	struct i2c_msg msgs[] = {
	145	{ client->addr, 0, 2, sr_addr }, /* setup read ptr */
	146	{ client->addr, I2C_M_RD, 1, sr }, /* read status */
	147	};
	148
	149	/* read status register */
471d47e3	150	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	151	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	152	return -EIO;
	153	}
	154
	155	return 0;
	156	}
	157
	158	static int x1205_set_datetime(struct i2c_client client, struct rtc_time tm,
d973b632	159	u8 reg_base, unsigned char alm_enable)
1fec7c66	160	{
d973b632	161	int i, xfer;
471d47e3	162	unsigned char rdata[10] = { 0, reg_base };
d973b632	163	unsigned char *buf = rdata + 2;
1fec7c66 AZ	164
	165	static const unsigned char wel[3] = { 0, X1205_REG_SR,
	166	X1205_SR_WEL };
	167
	168	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
	169	X1205_SR_WEL \| X1205_SR_RWEL };
	170
	171	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };
	172
	173	dev_dbg(&client->dev,
d973b632 JW	174	"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
	175	__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
	176	tm->tm_mon, tm->tm_year, tm->tm_wday);
1fec7c66	177
fe20ba70 AB	178	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
fe20ba70 AB	179	buf[CCR_MIN] = bin2bcd(tm->tm_min);
1fec7c66 AZ	180
1fec7c66 AZ	181	/* set hour and 24hr bit */
fe20ba70	182	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) \| X1205_HR_MIL;
1fec7c66	183
d973b632	184	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
1fec7c66	185
d973b632 JW	186	/* month, 1 - 12 */
d973b632 JW	187	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);
1fec7c66	188
d973b632 JW	189	/* year, since the rtc epoch*/
	190	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	191	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	192	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);
1fec7c66	193
471d47e3 MH	194	/* If writing alarm registers, set compare bits on registers 0-4 */
	195	if (reg_base < X1205_CCR_BASE)
	196	for (i = 0; i <= 4; i++)
	197	buf[i] \|= 0x80;
	198
1fec7c66 AZ	199	/* this sequence is required to unlock the chip */
1fec7c66 AZ	200	if ((xfer = i2c_master_send(client, wel, 3)) != 3) {
2a4e2b87	201	dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
1fec7c66 AZ	202	return -EIO;
	203	}
	204
	205	if ((xfer = i2c_master_send(client, rwel, 3)) != 3) {
2a4e2b87	206	dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
1fec7c66 AZ	207	return -EIO;
	208	}
	209
d973b632 JW	210	xfer = i2c_master_send(client, rdata, sizeof(rdata));
d973b632 JW	211	if (xfer != sizeof(rdata)) {
471d47e3 MH	212	dev_err(&client->dev,
	213	"%s: result=%d addr=%02x, data=%02x\n",
	214	__func__,
	215	xfer, rdata[1], rdata[2]);
	216	return -EIO;
	217	}
	218
	219	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	220	if (reg_base < X1205_CCR_BASE) {
	221	unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };
	222
	223	msleep(10);
	224
	225	/* ...and set or clear the AL0E bit in the INT register */
1fec7c66	226
471d47e3 MH	227	/* Need to set RWEL again as the write has cleared it */
471d47e3 MH	228	xfer = i2c_master_send(client, rwel, 3);
1fec7c66 AZ	229	if (xfer != 3) {
1fec7c66 AZ	230	dev_err(&client->dev,
471d47e3	231	"%s: aloe rwel - %d\n",
2a4e2b87	232	__func__,
471d47e3 MH	233	xfer);
	234	return -EIO;
	235	}
	236
	237	if (alm_enable)
	238	al0e[2] = X1205_INT_AL0E;
	239
	240	xfer = i2c_master_send(client, al0e, 3);
	241	if (xfer != 3) {
	242	dev_err(&client->dev,
	243	"%s: al0e - %d\n",
	244	__func__,
	245	xfer);
1fec7c66 AZ	246	return -EIO;
1fec7c66 AZ	247	}
471d47e3 MH	248
	249	/* and wait 10msec again for this write to complete */
	250	msleep(10);
	251	}
1fec7c66 AZ	252
	253	/* disable further writes */
	254	if ((xfer = i2c_master_send(client, diswe, 3)) != 3) {
2a4e2b87	255	dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
1fec7c66 AZ	256	return -EIO;
	257	}
	258
	259	return 0;
	260	}
	261
	262	static int x1205_fix_osc(struct i2c_client *client)
	263	{
	264	int err;
	265	struct rtc_time tm;
	266
cb8799ee	267	memset(&tm, 0, sizeof(tm));
1fec7c66	268
d973b632	269	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
471d47e3 MH	270	if (err < 0)
471d47e3 MH	271	dev_err(&client->dev, "unable to restart the oscillator\n");
1fec7c66 AZ	272
	273	return err;
	274	}
	275
	276	static int x1205_get_dtrim(struct i2c_client client, int trim)
	277	{
	278	unsigned char dtr;
	279	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };
	280
	281	struct i2c_msg msgs[] = {
	282	{ client->addr, 0, 2, dtr_addr }, /* setup read ptr */
	283	{ client->addr, I2C_M_RD, 1, &dtr }, /* read dtr */
	284	};
	285
	286	/* read dtr register */
471d47e3	287	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	288	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	289	return -EIO;
	290	}
	291
2a4e2b87	292	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);
1fec7c66 AZ	293
	294	*trim = 0;
	295
	296	if (dtr & X1205_DTR_DTR0)
	297	*trim += 20;
	298
	299	if (dtr & X1205_DTR_DTR1)
	300	*trim += 10;
	301
	302	if (dtr & X1205_DTR_DTR2)
	303	trim = -trim;
	304
	305	return 0;
	306	}
	307
	308	static int x1205_get_atrim(struct i2c_client client, int trim)
	309	{
	310	s8 atr;
	311	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };
	312
	313	struct i2c_msg msgs[] = {
	314	{ client->addr, 0, 2, atr_addr }, /* setup read ptr */
	315	{ client->addr, I2C_M_RD, 1, &atr }, /* read atr */
	316	};
	317
	318	/* read atr register */
471d47e3	319	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	320	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	321	return -EIO;
	322	}
	323
2a4e2b87	324	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);
1fec7c66 AZ	325
	326	/* atr is a two's complement value on 6 bits,
	327	* perform sign extension. The formula is
	328	* Catr = (atr * 0.25pF) + 11.00pF.
	329	*/
	330	if (atr & 0x20)
	331	atr \|= 0xC0;
	332
2a4e2b87	333	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);
1fec7c66 AZ	334
	335	trim = (atr 250) + 11000;
	336
2a4e2b87	337	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);
1fec7c66 AZ	338
	339	return 0;
	340	}
	341
	342	struct x1205_limit
	343	{
	344	unsigned char reg, mask, min, max;
	345	};
	346
	347	static int x1205_validate_client(struct i2c_client *client)
	348	{
	349	int i, xfer;
	350
	351	/* Probe array. We will read the register at the specified
	352	* address and check if the given bits are zero.
	353	*/
	354	static const unsigned char probe_zero_pattern[] = {
	355	/* register, mask */
	356	X1205_REG_SR, 0x18,
	357	X1205_REG_DTR, 0xF8,
	358	X1205_REG_ATR, 0xC0,
	359	X1205_REG_INT, 0x18,
	360	X1205_REG_0, 0xFF,
	361	};
	362
	363	static const struct x1205_limit probe_limits_pattern[] = {
	364	/* register, mask, min, max */
	365	{ X1205_REG_Y2K, 0xFF, 19, 20 },
	366	{ X1205_REG_DW, 0xFF, 0, 6 },
	367	{ X1205_REG_YR, 0xFF, 0, 99 },
	368	{ X1205_REG_MO, 0xFF, 0, 12 },
	369	{ X1205_REG_DT, 0xFF, 0, 31 },
	370	{ X1205_REG_HR, 0x7F, 0, 23 },
	371	{ X1205_REG_MN, 0xFF, 0, 59 },
	372	{ X1205_REG_SC, 0xFF, 0, 59 },
	373	{ X1205_REG_Y2K1, 0xFF, 19, 20 },
	374	{ X1205_REG_Y2K0, 0xFF, 19, 20 },
	375	};
	376
	377	/* check that registers have bits a 0 where expected */
	378	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
	379	unsigned char buf;
	380
	381	unsigned char addr[2] = { 0, probe_zero_pattern[i] };
	382
	383	struct i2c_msg msgs[2] = {
	384	{ client->addr, 0, 2, addr },
	385	{ client->addr, I2C_M_RD, 1, &buf },
	386	};
	387
	388	if ((xfer = i2c_transfer(client->adapter, msgs, 2)) != 2) {
a14e1893	389	dev_err(&client->dev,
1fec7c66	390	"%s: could not read register %x\n",
2a4e2b87	391	__func__, probe_zero_pattern[i]);
1fec7c66 AZ	392
	393	return -EIO;
	394	}
	395
	396	if ((buf & probe_zero_pattern[i+1]) != 0) {
a14e1893	397	dev_err(&client->dev,
1fec7c66	398	"%s: register=%02x, zero pattern=%d, value=%x\n",
2a4e2b87	399	__func__, probe_zero_pattern[i], i, buf);
1fec7c66 AZ	400
	401	return -ENODEV;
	402	}
	403	}
	404
	405	/* check limits (only registers with bcd values) */
	406	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
	407	unsigned char reg, value;
	408
	409	unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };
	410
	411	struct i2c_msg msgs[2] = {
	412	{ client->addr, 0, 2, addr },
	413	{ client->addr, I2C_M_RD, 1, &reg },
	414	};
	415
	416	if ((xfer = i2c_transfer(client->adapter, msgs, 2)) != 2) {
a14e1893	417	dev_err(&client->dev,
1fec7c66	418	"%s: could not read register %x\n",
2a4e2b87	419	__func__, probe_limits_pattern[i].reg);
1fec7c66 AZ	420
	421	return -EIO;
	422	}
	423
fe20ba70	424	value = bcd2bin(reg & probe_limits_pattern[i].mask);
1fec7c66 AZ	425
	426	if (value > probe_limits_pattern[i].max \|\|
	427	value < probe_limits_pattern[i].min) {
a14e1893	428	dev_dbg(&client->dev,
1fec7c66	429	"%s: register=%x, lim pattern=%d, value=%d\n",
2a4e2b87	430	__func__, probe_limits_pattern[i].reg,
1fec7c66 AZ	431	i, value);
	432
	433	return -ENODEV;
	434	}
	435	}
	436
	437	return 0;
	438	}
	439
	440	static int x1205_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	441	{
471d47e3 MH	442	int err;
	443	unsigned char intreg, status;
	444	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	445	struct i2c_client *client = to_i2c_client(dev);
	446	struct i2c_msg msgs[] = {
	447	{ client->addr, 0, 2, int_addr }, /* setup read ptr */
	448	{ client->addr, I2C_M_RD, 1, &intreg }, /* read INT register */
	449	};
	450
	451	/* read interrupt register and status register */
	452	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
	453	dev_err(&client->dev, "%s: read error\n", __func__);
	454	return -EIO;
	455	}
	456	err = x1205_get_status(client, &status);
	457	if (err == 0) {
	458	alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
	459	alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
	460	err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	461	}
	462	return err;
1fec7c66 AZ	463	}
	464
	465	static int x1205_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	466	{
	467	return x1205_set_datetime(to_i2c_client(dev),
d973b632	468	&alrm->time, X1205_ALM0_BASE, alrm->enabled);
1fec7c66 AZ	469	}
	470
	471	static int x1205_rtc_read_time(struct device dev, struct rtc_time tm)
	472	{
	473	return x1205_get_datetime(to_i2c_client(dev),
	474	tm, X1205_CCR_BASE);
	475	}
	476
	477	static int x1205_rtc_set_time(struct device dev, struct rtc_time tm)
	478	{
	479	return x1205_set_datetime(to_i2c_client(dev),
d973b632	480	tm, X1205_CCR_BASE, 0);
1fec7c66 AZ	481	}
	482
	483	static int x1205_rtc_proc(struct device dev, struct seq_file seq)
	484	{
	485	int err, dtrim, atrim;
	486
1fec7c66 AZ	487	if ((err = x1205_get_dtrim(to_i2c_client(dev), &dtrim)) == 0)
	488	seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);
	489
	490	if ((err = x1205_get_atrim(to_i2c_client(dev), &atrim)) == 0)
	491	seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
	492	atrim / 1000, atrim % 1000);
	493	return 0;
	494	}
	495
ff8371ac	496	static const struct rtc_class_ops x1205_rtc_ops = {
1fec7c66 AZ	497	.proc = x1205_rtc_proc,
	498	.read_time = x1205_rtc_read_time,
	499	.set_time = x1205_rtc_set_time,
	500	.read_alarm = x1205_rtc_read_alarm,
	501	.set_alarm = x1205_rtc_set_alarm,
	502	};
	503
	504	static ssize_t x1205_sysfs_show_atrim(struct device *dev,
	505	struct device_attribute attr, char buf)
	506	{
015aefbb	507	int err, atrim;
1fec7c66	508
015aefbb AZ	509	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	510	if (err)
	511	return err;
	512
	513	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
1fec7c66 AZ	514	}
	515	static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);
	516
	517	static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
	518	struct device_attribute attr, char buf)
	519	{
015aefbb	520	int err, dtrim;
1fec7c66	521
015aefbb AZ	522	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	523	if (err)
	524	return err;
1fec7c66	525
015aefbb	526	return sprintf(buf, "%d ppm\n", dtrim);
1fec7c66 AZ	527	}
	528	static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);
	529
4edac2b4 AZ	530	static int x1205_sysfs_register(struct device *dev)
	531	{
	532	int err;
	533
	534	err = device_create_file(dev, &dev_attr_atrim);
	535	if (err)
	536	return err;
	537
	538	err = device_create_file(dev, &dev_attr_dtrim);
	539	if (err)
	540	device_remove_file(dev, &dev_attr_atrim);
	541
	542	return err;
	543	}
	544
	545	static void x1205_sysfs_unregister(struct device *dev)
1fec7c66	546	{
4edac2b4 AZ	547	device_remove_file(dev, &dev_attr_atrim);
4edac2b4 AZ	548	device_remove_file(dev, &dev_attr_dtrim);
1fec7c66 AZ	549	}
1fec7c66 AZ	550
4edac2b4	551
d2653e92 JD	552	static int x1205_probe(struct i2c_client *client,
d2653e92 JD	553	const struct i2c_device_id *id)
1fec7c66 AZ	554	{
	555	int err = 0;
	556	unsigned char sr;
1fec7c66 AZ	557	struct rtc_device *rtc;
1fec7c66 AZ	558
4edac2b4	559	dev_dbg(&client->dev, "%s\n", __func__);
1fec7c66	560
4edac2b4 AZ	561	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
4edac2b4 AZ	562	return -ENODEV;
1fec7c66	563
4edac2b4 AZ	564	if (x1205_validate_client(client) < 0)
4edac2b4 AZ	565	return -ENODEV;
1fec7c66 AZ	566
	567	dev_info(&client->dev, "chip found, driver version " DRV_VERSION "\n");
	568
	569	rtc = rtc_device_register(x1205_driver.driver.name, &client->dev,
	570	&x1205_rtc_ops, THIS_MODULE);
	571
4edac2b4 AZ	572	if (IS_ERR(rtc))
4edac2b4 AZ	573	return PTR_ERR(rtc);
1fec7c66 AZ	574
	575	i2c_set_clientdata(client, rtc);
	576
25985edc	577	/* Check for power failures and eventually enable the osc */
1fec7c66 AZ	578	if ((err = x1205_get_status(client, &sr)) == 0) {
	579	if (sr & X1205_SR_RTCF) {
	580	dev_err(&client->dev,
	581	"power failure detected, "
	582	"please set the clock\n");
	583	udelay(50);
	584	x1205_fix_osc(client);
	585	}
	586	}
	587	else
	588	dev_err(&client->dev, "couldn't read status\n");
	589
4edac2b4 AZ	590	err = x1205_sysfs_register(&client->dev);
	591	if (err)
	592	goto exit_devreg;
1fec7c66 AZ	593
	594	return 0;
	595
91046a8a JG	596	exit_devreg:
	597	rtc_device_unregister(rtc);
	598
1fec7c66 AZ	599	return err;
	600	}
	601
4edac2b4	602	static int x1205_remove(struct i2c_client *client)
1fec7c66	603	{
1fec7c66 AZ	604	struct rtc_device *rtc = i2c_get_clientdata(client);
1fec7c66 AZ	605
4edac2b4 AZ	606	rtc_device_unregister(rtc);
4edac2b4 AZ	607	x1205_sysfs_unregister(&client->dev);
1fec7c66 AZ	608	return 0;
	609	}
	610
3760f736 JD	611	static const struct i2c_device_id x1205_id[] = {
	612	{ "x1205", 0 },
	613	{ }
	614	};
	615	MODULE_DEVICE_TABLE(i2c, x1205_id);
	616
4edac2b4 AZ	617	static struct i2c_driver x1205_driver = {
	618	.driver = {
	619	.name = "rtc-x1205",
	620	},
	621	.probe = x1205_probe,
	622	.remove = x1205_remove,
3760f736	623	.id_table = x1205_id,
4edac2b4 AZ	624	};
4edac2b4 AZ	625
0abc9201	626	module_i2c_driver(x1205_driver);
1fec7c66 AZ	627
	628	MODULE_AUTHOR(
	629	"Karen Spearel <kas111 at gmail dot com>, "
	630	"Alessandro Zummo <[email protected]>");
	631	MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
	632	MODULE_LICENSE("GPL");
	633	MODULE_VERSION(DRV_VERSION);