[linux.git] / drivers / clk / clk-axi-clkgen.c

/*
 * AXI clkgen driver
 *
 * Copyright 2012-2013 Analog Devices Inc.
 *  Author: Lars-Peter Clausen <[email protected]>
 *
 * Licensed under the GPL-2.
 *
 */

#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/err.h>

#define AXI_CLKGEN_V2_REG_RESET		0x40
#define AXI_CLKGEN_V2_REG_CLKSEL	0x44
#define AXI_CLKGEN_V2_REG_DRP_CNTRL	0x70
#define AXI_CLKGEN_V2_REG_DRP_STATUS	0x74

#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE	BIT(1)
#define AXI_CLKGEN_V2_RESET_ENABLE	BIT(0)

#define AXI_CLKGEN_V2_DRP_CNTRL_SEL	BIT(29)
#define AXI_CLKGEN_V2_DRP_CNTRL_READ	BIT(28)

#define AXI_CLKGEN_V2_DRP_STATUS_BUSY	BIT(16)

#define MMCM_REG_CLKOUT0_1	0x08
#define MMCM_REG_CLKOUT0_2	0x09
#define MMCM_REG_CLK_FB1	0x14
#define MMCM_REG_CLK_FB2	0x15
#define MMCM_REG_CLK_DIV	0x16
#define MMCM_REG_LOCK1		0x18
#define MMCM_REG_LOCK2		0x19
#define MMCM_REG_LOCK3		0x1a
#define MMCM_REG_FILTER1	0x4e
#define MMCM_REG_FILTER2	0x4f

#define MMCM_CLKOUT_NOCOUNT	BIT(6)

#define MMCM_CLK_DIV_NOCOUNT	BIT(12)

struct axi_clkgen {
	void __iomem *base;
	struct clk_hw clk_hw;
};

static uint32_t axi_clkgen_lookup_filter(unsigned int m)
{
	switch (m) {
	case 0:
		return 0x01001990;
	case 1:
		return 0x01001190;
	case 2:
		return 0x01009890;
	case 3:
		return 0x01001890;
	case 4:
		return 0x01008890;
	case 5 ... 8:
		return 0x01009090;
	case 9 ... 11:
		return 0x01000890;
	case 12:
		return 0x08009090;
	case 13 ... 22:
		return 0x01001090;
	case 23 ... 36:
		return 0x01008090;
	case 37 ... 46:
		return 0x08001090;
	default:
		return 0x08008090;
	}
}

static const uint32_t axi_clkgen_lock_table[] = {
	0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
	0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
	0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
	0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
	0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
	0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
	0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
	0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
	0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
};

static uint32_t axi_clkgen_lookup_lock(unsigned int m)
{
	if (m < ARRAY_SIZE(axi_clkgen_lock_table))
		return axi_clkgen_lock_table[m];
	return 0x1f1f00fa;
}

static const unsigned int fpfd_min = 10000;
static const unsigned int fpfd_max = 300000;
static const unsigned int fvco_min = 600000;
static const unsigned int fvco_max = 1200000;

static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
	unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
{
	unsigned long d, d_min, d_max, _d_min, _d_max;
	unsigned long m, m_min, m_max;
	unsigned long f, dout, best_f, fvco;

	fin /= 1000;
	fout /= 1000;

	best_f = ULONG_MAX;
	*best_d = 0;
	*best_m = 0;
	*best_dout = 0;

	d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
	d_max = min_t(unsigned long, fin / fpfd_min, 80);

	m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1);
	m_max = min_t(unsigned long, fvco_max * d_max / fin, 64);

	for (m = m_min; m <= m_max; m++) {
		_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max));
		_d_max = min(d_max, fin * m / fvco_min);

		for (d = _d_min; d <= _d_max; d++) {
			fvco = fin * m / d;

			dout = DIV_ROUND_CLOSEST(fvco, fout);
			dout = clamp_t(unsigned long, dout, 1, 128);
			f = fvco / dout;
			if (abs(f - fout) < abs(best_f - fout)) {
				best_f = f;
				*best_d = d;
				*best_m = m;
				*best_dout = dout;
				if (best_f == fout)
					return;
			}
		}
	}
}

static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low,
	unsigned int *high, unsigned int *edge, unsigned int *nocount)
{
	if (divider == 1)
		*nocount = 1;
	else
		*nocount = 0;

	*high = divider / 2;
	*edge = divider % 2;
	*low = divider - *high;
}

static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int val)
{
	writel(val, axi_clkgen->base + reg);
}

static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int *val)
{
	*val = readl(axi_clkgen->base + reg);
}

static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
{
	unsigned int timeout = 10000;
	unsigned int val;

	do {
		axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);

	if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
		return -EIO;

	return val & 0xffff;
}

static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int *val)
{
	unsigned int reg_val;
	int ret;

	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	if (ret < 0)
		return ret;

	reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
	reg_val |= (reg << 16);

	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);

	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	if (ret < 0)
		return ret;

	*val = ret;

	return 0;
}

static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
	unsigned int reg, unsigned int val, unsigned int mask)
{
	unsigned int reg_val = 0;
	int ret;

	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	if (ret < 0)
		return ret;

	if (mask != 0xffff) {
		axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
		reg_val &= ~mask;
	}

	reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);

	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);

	return 0;
}

static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
	bool enable)
{
	unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;

	if (enable)
		val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;

	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
}

static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
{
	return container_of(clk_hw, struct axi_clkgen, clk_hw);
}

static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
	unsigned long rate, unsigned long parent_rate)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	unsigned int d, m, dout;
	unsigned int nocount;
	unsigned int high;
	unsigned int edge;
	unsigned int low;
	uint32_t filter;
	uint32_t lock;

	if (parent_rate == 0 || rate == 0)
		return -EINVAL;

	axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);

	if (d == 0 || dout == 0 || m == 0)
		return -EINVAL;

	filter = axi_clkgen_lookup_filter(m - 1);
	lock = axi_clkgen_lookup_lock(m - 1);

	axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_1,
		(high << 6) | low, 0xefff);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_2,
		(edge << 7) | (nocount << 6), 0x03ff);

	axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
		(edge << 13) | (nocount << 12) | (high << 6) | low, 0x3fff);

	axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB1,
		(high << 6) | low, 0xefff);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB2,
		(edge << 7) | (nocount << 6), 0x03ff);

	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
		(((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
		(((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);

	return 0;
}

static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
	unsigned long *parent_rate)
{
	unsigned int d, m, dout;
	unsigned long long tmp;

	axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);

	if (d == 0 || dout == 0 || m == 0)
		return -EINVAL;

	tmp = (unsigned long long)*parent_rate * m;
	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);

	return min_t(unsigned long long, tmp, LONG_MAX);
}

static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
	unsigned long parent_rate)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	unsigned int d, m, dout;
	unsigned int reg;
	unsigned long long tmp;

	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, &reg);
	if (reg & MMCM_CLKOUT_NOCOUNT) {
		dout = 1;
	} else {
		axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, &reg);
		dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
	}

	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &reg);
	if (reg & MMCM_CLK_DIV_NOCOUNT)
		d = 1;
	else
		d = (reg & 0x3f) + ((reg >> 6) & 0x3f);

	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, &reg);
	if (reg & MMCM_CLKOUT_NOCOUNT) {
		m = 1;
	} else {
		axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, &reg);
		m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
	}

	if (d == 0 || dout == 0)
		return 0;

	tmp = (unsigned long long)parent_rate * m;
	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);

	return min_t(unsigned long long, tmp, ULONG_MAX);
}

static int axi_clkgen_enable(struct clk_hw *clk_hw)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);

	axi_clkgen_mmcm_enable(axi_clkgen, true);

	return 0;
}

static void axi_clkgen_disable(struct clk_hw *clk_hw)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);

	axi_clkgen_mmcm_enable(axi_clkgen, false);
}

static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);

	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);

	return 0;
}

static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
{
	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	unsigned int parent;

	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);

	return parent;
}

static const struct clk_ops axi_clkgen_ops = {
	.recalc_rate = axi_clkgen_recalc_rate,
	.round_rate = axi_clkgen_round_rate,
	.set_rate = axi_clkgen_set_rate,
	.enable = axi_clkgen_enable,
	.disable = axi_clkgen_disable,
	.set_parent = axi_clkgen_set_parent,
	.get_parent = axi_clkgen_get_parent,
};

static const struct of_device_id axi_clkgen_ids[] = {
	{
		.compatible = "adi,axi-clkgen-2.00.a",
	},
	{ },
};
MODULE_DEVICE_TABLE(of, axi_clkgen_ids);

static int axi_clkgen_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	struct axi_clkgen *axi_clkgen;
	struct clk_init_data init;
	const char *parent_names[2];
	const char *clk_name;
	struct resource *mem;
	unsigned int i;
	int ret;

	if (!pdev->dev.of_node)
		return -ENODEV;

	id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
	if (!id)
		return -ENODEV;

	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
	if (!axi_clkgen)
		return -ENOMEM;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(axi_clkgen->base))
		return PTR_ERR(axi_clkgen->base);

	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
	if (init.num_parents < 1 || init.num_parents > 2)
		return -EINVAL;

	for (i = 0; i < init.num_parents; i++) {
		parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
		if (!parent_names[i])
			return -EINVAL;
	}

	clk_name = pdev->dev.of_node->name;
	of_property_read_string(pdev->dev.of_node, "clock-output-names",
		&clk_name);

	init.name = clk_name;
	init.ops = &axi_clkgen_ops;
	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
	init.parent_names = parent_names;

	axi_clkgen_mmcm_enable(axi_clkgen, false);

	axi_clkgen->clk_hw.init = &init;
	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
	if (ret)
		return ret;

	return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
				      &axi_clkgen->clk_hw);
}

static int axi_clkgen_remove(struct platform_device *pdev)
{
	of_clk_del_provider(pdev->dev.of_node);

	return 0;
}

static struct platform_driver axi_clkgen_driver = {
	.driver = {
		.name = "adi-axi-clkgen",
		.of_match_table = axi_clkgen_ids,
	},
	.probe = axi_clkgen_probe,
	.remove = axi_clkgen_remove,
};
module_platform_driver(axi_clkgen_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
Commit	Line	Data
0e646c52 LPC	1	/*
	2	* AXI clkgen driver
	3	*
	4	* Copyright 2012-2013 Analog Devices Inc.
	5	* Author: Lars-Peter Clausen <[email protected]>
	6	*
	7	* Licensed under the GPL-2.
	8	*
	9	*/
	10
	11	#include <linux/platform_device.h>
	12	#include <linux/clk-provider.h>
0e646c52 LPC	13	#include <linux/slab.h>
	14	#include <linux/io.h>
	15	#include <linux/of.h>
	16	#include <linux/module.h>
	17	#include <linux/err.h>
	18
1887c3a6	19	#define AXI_CLKGEN_V2_REG_RESET 0x40
62d1e782	20	#define AXI_CLKGEN_V2_REG_CLKSEL 0x44
1887c3a6 LPC	21	#define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
	22	#define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
	23
	24	#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
	25	#define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
	26
	27	#define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
	28	#define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
	29
	30	#define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
	31
	32	#define MMCM_REG_CLKOUT0_1 0x08
	33	#define MMCM_REG_CLKOUT0_2 0x09
	34	#define MMCM_REG_CLK_FB1 0x14
	35	#define MMCM_REG_CLK_FB2 0x15
	36	#define MMCM_REG_CLK_DIV 0x16
	37	#define MMCM_REG_LOCK1 0x18
	38	#define MMCM_REG_LOCK2 0x19
	39	#define MMCM_REG_LOCK3 0x1a
	40	#define MMCM_REG_FILTER1 0x4e
	41	#define MMCM_REG_FILTER2 0x4f
	42
063578dc LPC	43	#define MMCM_CLKOUT_NOCOUNT BIT(6)
	44
	45	#define MMCM_CLK_DIV_NOCOUNT BIT(12)
	46
0e646c52 LPC	47	struct axi_clkgen {
	48	void __iomem *base;
	49	struct clk_hw clk_hw;
	50	};
	51
	52	static uint32_t axi_clkgen_lookup_filter(unsigned int m)
	53	{
	54	switch (m) {
	55	case 0:
	56	return 0x01001990;
	57	case 1:
	58	return 0x01001190;
	59	case 2:
	60	return 0x01009890;
	61	case 3:
	62	return 0x01001890;
	63	case 4:
	64	return 0x01008890;
	65	case 5 ... 8:
	66	return 0x01009090;
	67	case 9 ... 11:
	68	return 0x01000890;
	69	case 12:
	70	return 0x08009090;
	71	case 13 ... 22:
	72	return 0x01001090;
	73	case 23 ... 36:
	74	return 0x01008090;
	75	case 37 ... 46:
	76	return 0x08001090;
	77	default:
	78	return 0x08008090;
	79	}
	80	}
	81
	82	static const uint32_t axi_clkgen_lock_table[] = {
	83	0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
	84	0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
	85	0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
	86	0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
	87	0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
	88	0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
	89	0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
	90	0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
	91	0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
	92	};
	93
	94	static uint32_t axi_clkgen_lookup_lock(unsigned int m)
	95	{
	96	if (m < ARRAY_SIZE(axi_clkgen_lock_table))
	97	return axi_clkgen_lock_table[m];
	98	return 0x1f1f00fa;
	99	}
	100
	101	static const unsigned int fpfd_min = 10000;
	102	static const unsigned int fpfd_max = 300000;
	103	static const unsigned int fvco_min = 600000;
	104	static const unsigned int fvco_max = 1200000;
	105
	106	static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
	107	unsigned int best_d, unsigned int best_m, unsigned int *best_dout)
	108	{
	109	unsigned long d, d_min, d_max, _d_min, _d_max;
	110	unsigned long m, m_min, m_max;
111	unsigned long f, dout, best_f, fvco;
112
113	fin /= 1000;
114	fout /= 1000;
115
116	best_f = ULONG_MAX;
117	*best_d = 0;
118	*best_m = 0;
119	*best_dout = 0;
120
121	d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
122	d_max = min_t(unsigned long, fin / fpfd_min, 80);
123
124	m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1);
125	m_max = min_t(unsigned long, fvco_max * d_max / fin, 64);
126
127	for (m = m_min; m <= m_max; m++) {
128	_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max));
129	_d_max = min(d_max, fin * m / fvco_min);
130
131	for (d = _d_min; d <= _d_max; d++) {
132	fvco = fin * m / d;
133
134	dout = DIV_ROUND_CLOSEST(fvco, fout);
135	dout = clamp_t(unsigned long, dout, 1, 128);
136	f = fvco / dout;
137	if (abs(f - fout) < abs(best_f - fout)) {
138	best_f = f;
139	*best_d = d;
140	*best_m = m;
141	*best_dout = dout;
142	if (best_f == fout)
143	return;
144	}
145	}
146	}
147	}
148
149	static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low,
150	unsigned int high, unsigned int edge, unsigned int *nocount)
151	{
152	if (divider == 1)
153	*nocount = 1;
154	else
155	*nocount = 0;
156
157	*high = divider / 2;
158	*edge = divider % 2;
159	low = divider - high;
160	}
161
162	static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
163	unsigned int reg, unsigned int val)
164	{
165	writel(val, axi_clkgen->base + reg);
166	}
167
168	static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
169	unsigned int reg, unsigned int *val)
170	{
171	*val = readl(axi_clkgen->base + reg);
172	}
173
1887c3a6 LPC	174	static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
	175	{
	176	unsigned int timeout = 10000;
	177	unsigned int val;
	178
	179	do {
	180	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
	181	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
	182
	183	if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
	184	return -EIO;
	185
	186	return val & 0xffff;
	187	}
	188
d95b599c	189	static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
1887c3a6 LPC	190	unsigned int reg, unsigned int *val)
	191	{
	192	unsigned int reg_val;
	193	int ret;
	194
	195	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	196	if (ret < 0)
	197	return ret;
	198
	199	reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL \| AXI_CLKGEN_V2_DRP_CNTRL_READ;
	200	reg_val \|= (reg << 16);
	201
	202	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
	203
	204	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	205	if (ret < 0)
	206	return ret;
	207
	208	*val = ret;
	209
	210	return 0;
	211	}
	212
d95b599c	213	static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
1887c3a6 LPC	214	unsigned int reg, unsigned int val, unsigned int mask)
	215	{
	216	unsigned int reg_val = 0;
	217	int ret;
	218
	219	ret = axi_clkgen_wait_non_busy(axi_clkgen);
	220	if (ret < 0)
	221	return ret;
	222
	223	if (mask != 0xffff) {
d95b599c	224	axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
1887c3a6 LPC	225	reg_val &= ~mask;
	226	}
	227
	228	reg_val \|= AXI_CLKGEN_V2_DRP_CNTRL_SEL \| (reg << 16) \| (val & mask);
	229
	230	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
	231
	232	return 0;
	233	}
	234
d95b599c	235	static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
1887c3a6 LPC	236	bool enable)
	237	{
	238	unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
	239
	240	if (enable)
	241	val \|= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
	242
	243	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
	244	}
	245
0e646c52 LPC	246	static struct axi_clkgen clk_hw_to_axi_clkgen(struct clk_hw clk_hw)
	247	{
	248	return container_of(clk_hw, struct axi_clkgen, clk_hw);
	249	}
	250
	251	static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
	252	unsigned long rate, unsigned long parent_rate)
	253	{
	254	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	255	unsigned int d, m, dout;
	256	unsigned int nocount;
	257	unsigned int high;
	258	unsigned int edge;
	259	unsigned int low;
	260	uint32_t filter;
	261	uint32_t lock;
	262
	263	if (parent_rate == 0 \|\| rate == 0)
	264	return -EINVAL;
	265
	266	axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
	267
	268	if (d == 0 \|\| dout == 0 \|\| m == 0)
	269	return -EINVAL;
	270
	271	filter = axi_clkgen_lookup_filter(m - 1);
	272	lock = axi_clkgen_lookup_lock(m - 1);
	273
0e646c52	274	axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount);
1887c3a6 LPC	275	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_1,
	276	(high << 6) \| low, 0xefff);
	277	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_2,
	278	(edge << 7) \| (nocount << 6), 0x03ff);
0e646c52 LPC	279
0e646c52 LPC	280	axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount);
1887c3a6 LPC	281	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
1887c3a6 LPC	282	(edge << 13) \| (nocount << 12) \| (high << 6) \| low, 0x3fff);
0e646c52 LPC	283
0e646c52 LPC	284	axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount);
1887c3a6 LPC	285	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB1,
	286	(high << 6) \| low, 0xefff);
	287	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB2,
	288	(edge << 7) \| (nocount << 6), 0x03ff);
	289
	290	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
	291	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
	292	(((lock >> 16) & 0x1f) << 10) \| 0x1, 0x7fff);
	293	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
	294	(((lock >> 24) & 0x1f) << 10) \| 0x3e9, 0x7fff);
	295	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
	296	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
0e646c52 LPC	297
	298	return 0;
	299	}
	300
	301	static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
	302	unsigned long *parent_rate)
	303	{
	304	unsigned int d, m, dout;
448c3c05	305	unsigned long long tmp;
0e646c52 LPC	306
	307	axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
	308
	309	if (d == 0 \|\| dout == 0 \|\| m == 0)
	310	return -EINVAL;
	311
448c3c05 LPC	312	tmp = (unsigned long long)parent_rate m;
	313	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
	314
	315	return min_t(unsigned long long, tmp, LONG_MAX);
0e646c52 LPC	316	}
	317
	318	static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
	319	unsigned long parent_rate)
	320	{
	321	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	322	unsigned int d, m, dout;
	323	unsigned int reg;
	324	unsigned long long tmp;
	325
063578dc LPC	326	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, &reg);
	327	if (reg & MMCM_CLKOUT_NOCOUNT) {
	328	dout = 1;
	329	} else {
	330	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, &reg);
	331	dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
	332	}
	333
1887c3a6	334	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &reg);
063578dc LPC	335	if (reg & MMCM_CLK_DIV_NOCOUNT)
	336	d = 1;
	337	else
	338	d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
	339
	340	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, &reg);
	341	if (reg & MMCM_CLKOUT_NOCOUNT) {
	342	m = 1;
	343	} else {
	344	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, &reg);
	345	m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
	346	}
0e646c52 LPC	347
	348	if (d == 0 \|\| dout == 0)
	349	return 0;
	350
448c3c05 LPC	351	tmp = (unsigned long long)parent_rate * m;
448c3c05 LPC	352	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
0e646c52	353
3d6f1c72	354	return min_t(unsigned long long, tmp, ULONG_MAX);
0e646c52 LPC	355	}
0e646c52 LPC	356
1887c3a6 LPC	357	static int axi_clkgen_enable(struct clk_hw *clk_hw)
	358	{
	359	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	360
	361	axi_clkgen_mmcm_enable(axi_clkgen, true);
	362
	363	return 0;
	364	}
	365
	366	static void axi_clkgen_disable(struct clk_hw *clk_hw)
	367	{
	368	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	369
	370	axi_clkgen_mmcm_enable(axi_clkgen, false);
	371	}
	372
62d1e782 LPC	373	static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
	374	{
	375	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	376
	377	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
	378
	379	return 0;
	380	}
	381
	382	static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
	383	{
	384	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
	385	unsigned int parent;
	386
	387	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
	388
	389	return parent;
	390	}
	391
0e646c52 LPC	392	static const struct clk_ops axi_clkgen_ops = {
	393	.recalc_rate = axi_clkgen_recalc_rate,
	394	.round_rate = axi_clkgen_round_rate,
	395	.set_rate = axi_clkgen_set_rate,
1887c3a6 LPC	396	.enable = axi_clkgen_enable,
1887c3a6 LPC	397	.disable = axi_clkgen_disable,
62d1e782 LPC	398	.set_parent = axi_clkgen_set_parent,
62d1e782 LPC	399	.get_parent = axi_clkgen_get_parent,
0e646c52 LPC	400	};
0e646c52 LPC	401
1887c3a6 LPC	402	static const struct of_device_id axi_clkgen_ids[] = {
1887c3a6 LPC	403	{
1887c3a6	404	.compatible = "adi,axi-clkgen-2.00.a",
1887c3a6 LPC	405	},
	406	{ },
	407	};
	408	MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
	409
0e646c52 LPC	410	static int axi_clkgen_probe(struct platform_device *pdev)
0e646c52 LPC	411	{
1887c3a6	412	const struct of_device_id *id;
0e646c52 LPC	413	struct axi_clkgen *axi_clkgen;
0e646c52 LPC	414	struct clk_init_data init;
62d1e782	415	const char *parent_names[2];
0e646c52 LPC	416	const char *clk_name;
0e646c52 LPC	417	struct resource *mem;
62d1e782	418	unsigned int i;
e0d30bb9	419	int ret;
0e646c52	420
1887c3a6 LPC	421	if (!pdev->dev.of_node)
	422	return -ENODEV;
	423
	424	id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
	425	if (!id)
	426	return -ENODEV;
	427
0e646c52 LPC	428	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
	429	if (!axi_clkgen)
	430	return -ENOMEM;
	431
	432	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	433	axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
	434	if (IS_ERR(axi_clkgen->base))
	435	return PTR_ERR(axi_clkgen->base);
	436
62d1e782 LPC	437	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
62d1e782 LPC	438	if (init.num_parents < 1 \|\| init.num_parents > 2)
0e646c52 LPC	439	return -EINVAL;
0e646c52 LPC	440
62d1e782 LPC	441	for (i = 0; i < init.num_parents; i++) {
	442	parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
	443	if (!parent_names[i])
	444	return -EINVAL;
	445	}
	446
0e646c52 LPC	447	clk_name = pdev->dev.of_node->name;
	448	of_property_read_string(pdev->dev.of_node, "clock-output-names",
	449	&clk_name);
	450
	451	init.name = clk_name;
	452	init.ops = &axi_clkgen_ops;
62d1e782 LPC	453	init.flags = CLK_SET_RATE_GATE \| CLK_SET_PARENT_GATE;
62d1e782 LPC	454	init.parent_names = parent_names;
0e646c52	455
1887c3a6 LPC	456	axi_clkgen_mmcm_enable(axi_clkgen, false);
1887c3a6 LPC	457
0e646c52	458	axi_clkgen->clk_hw.init = &init;
e0d30bb9 SB	459	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
	460	if (ret)
	461	return ret;
0e646c52	462
e0d30bb9 SB	463	return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
e0d30bb9 SB	464	&axi_clkgen->clk_hw);
0e646c52 LPC	465	}
	466
	467	static int axi_clkgen_remove(struct platform_device *pdev)
	468	{
	469	of_clk_del_provider(pdev->dev.of_node);
	470
	471	return 0;
	472	}
	473
0e646c52 LPC	474	static struct platform_driver axi_clkgen_driver = {
	475	.driver = {
	476	.name = "adi-axi-clkgen",
0e646c52 LPC	477	.of_match_table = axi_clkgen_ids,
	478	},
	479	.probe = axi_clkgen_probe,
	480	.remove = axi_clkgen_remove,
	481	};
	482	module_platform_driver(axi_clkgen_driver);
	483
	484	MODULE_LICENSE("GPL v2");
	485	MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
	486	MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");