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e1bd55e5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9d9f78ed MT |
2 | /* |
3 | * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> | |
4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
5 | * | |
9d9f78ed MT |
6 | * Fixed rate clock implementation |
7 | */ | |
8 | ||
9 | #include <linux/clk-provider.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/err.h> | |
015ba402 | 14 | #include <linux/of.h> |
435779fe | 15 | #include <linux/platform_device.h> |
9d9f78ed MT |
16 | |
17 | /* | |
18 | * DOC: basic fixed-rate clock that cannot gate | |
19 | * | |
20 | * Traits of this clock: | |
21 | * prepare - clk_(un)prepare only ensures parents are prepared | |
22 | * enable - clk_enable only ensures parents are enabled | |
23 | * rate - rate is always a fixed value. No clk_set_rate support | |
24 | * parent - fixed parent. No clk_set_parent support | |
25 | */ | |
26 | ||
38d1e380 SB |
27 | #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) |
28 | ||
9d9f78ed MT |
29 | static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw, |
30 | unsigned long parent_rate) | |
31 | { | |
32 | return to_clk_fixed_rate(hw)->fixed_rate; | |
33 | } | |
9d9f78ed | 34 | |
0903ea60 BB |
35 | static unsigned long clk_fixed_rate_recalc_accuracy(struct clk_hw *hw, |
36 | unsigned long parent_accuracy) | |
37 | { | |
58f0c4ba SB |
38 | struct clk_fixed_rate *fixed = to_clk_fixed_rate(hw); |
39 | ||
40 | if (fixed->flags & CLK_FIXED_RATE_PARENT_ACCURACY) | |
41 | return parent_accuracy; | |
42 | ||
43 | return fixed->fixed_accuracy; | |
0903ea60 BB |
44 | } |
45 | ||
822c250e | 46 | const struct clk_ops clk_fixed_rate_ops = { |
9d9f78ed | 47 | .recalc_rate = clk_fixed_rate_recalc_rate, |
0903ea60 | 48 | .recalc_accuracy = clk_fixed_rate_recalc_accuracy, |
9d9f78ed MT |
49 | }; |
50 | EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); | |
51 | ||
2d34f09e SB |
52 | struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, |
53 | struct device_node *np, const char *name, | |
54 | const char *parent_name, const struct clk_hw *parent_hw, | |
55 | const struct clk_parent_data *parent_data, unsigned long flags, | |
56 | unsigned long fixed_rate, unsigned long fixed_accuracy, | |
57 | unsigned long clk_fixed_flags) | |
9d9f78ed MT |
58 | { |
59 | struct clk_fixed_rate *fixed; | |
26ef56be | 60 | struct clk_hw *hw; |
cc819cf8 | 61 | struct clk_init_data init = {}; |
2d34f09e | 62 | int ret = -EINVAL; |
9d9f78ed | 63 | |
27d54591 | 64 | /* allocate fixed-rate clock */ |
d122db7e SB |
65 | fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); |
66 | if (!fixed) | |
9d9f78ed | 67 | return ERR_PTR(-ENOMEM); |
9d9f78ed | 68 | |
0197b3ea SK |
69 | init.name = name; |
70 | init.ops = &clk_fixed_rate_ops; | |
90b6c5c7 | 71 | init.flags = flags; |
2d34f09e SB |
72 | init.parent_names = parent_name ? &parent_name : NULL; |
73 | init.parent_hws = parent_hw ? &parent_hw : NULL; | |
74 | init.parent_data = parent_data; | |
75 | if (parent_name || parent_hw || parent_data) | |
76 | init.num_parents = 1; | |
77 | else | |
78 | init.num_parents = 0; | |
0197b3ea | 79 | |
9d9f78ed | 80 | /* struct clk_fixed_rate assignments */ |
2d34f09e | 81 | fixed->flags = clk_fixed_flags; |
9d9f78ed | 82 | fixed->fixed_rate = fixed_rate; |
0903ea60 | 83 | fixed->fixed_accuracy = fixed_accuracy; |
0197b3ea | 84 | fixed->hw.init = &init; |
9d9f78ed | 85 | |
27d54591 | 86 | /* register the clock */ |
26ef56be | 87 | hw = &fixed->hw; |
2d34f09e SB |
88 | if (dev || !np) |
89 | ret = clk_hw_register(dev, hw); | |
90 | else if (np) | |
91 | ret = of_clk_hw_register(np, hw); | |
26ef56be | 92 | if (ret) { |
27d54591 | 93 | kfree(fixed); |
26ef56be SB |
94 | hw = ERR_PTR(ret); |
95 | } | |
27d54591 | 96 | |
26ef56be SB |
97 | return hw; |
98 | } | |
2d34f09e | 99 | EXPORT_SYMBOL_GPL(__clk_hw_register_fixed_rate); |
26ef56be | 100 | |
0903ea60 BB |
101 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
102 | const char *parent_name, unsigned long flags, | |
103 | unsigned long fixed_rate) | |
104 | { | |
576859df SB |
105 | struct clk_hw *hw; |
106 | ||
107 | hw = clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, | |
108 | flags, fixed_rate, 0); | |
109 | if (IS_ERR(hw)) | |
110 | return ERR_CAST(hw); | |
111 | return hw->clk; | |
0903ea60 | 112 | } |
389ae05f | 113 | EXPORT_SYMBOL_GPL(clk_register_fixed_rate); |
015ba402 | 114 | |
0b225e41 MY |
115 | void clk_unregister_fixed_rate(struct clk *clk) |
116 | { | |
117 | struct clk_hw *hw; | |
118 | ||
119 | hw = __clk_get_hw(clk); | |
120 | if (!hw) | |
121 | return; | |
122 | ||
123 | clk_unregister(clk); | |
124 | kfree(to_clk_fixed_rate(hw)); | |
125 | } | |
126 | EXPORT_SYMBOL_GPL(clk_unregister_fixed_rate); | |
127 | ||
52445637 MY |
128 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw) |
129 | { | |
130 | struct clk_fixed_rate *fixed; | |
131 | ||
132 | fixed = to_clk_fixed_rate(hw); | |
133 | ||
134 | clk_hw_unregister(hw); | |
135 | kfree(fixed); | |
136 | } | |
137 | EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_rate); | |
138 | ||
015ba402 | 139 | #ifdef CONFIG_OF |
34e01833 | 140 | static struct clk_hw *_of_fixed_clk_setup(struct device_node *node) |
015ba402 | 141 | { |
34e01833 | 142 | struct clk_hw *hw; |
015ba402 GL |
143 | const char *clk_name = node->name; |
144 | u32 rate; | |
0903ea60 | 145 | u32 accuracy = 0; |
435779fe | 146 | int ret; |
015ba402 GL |
147 | |
148 | if (of_property_read_u32(node, "clock-frequency", &rate)) | |
435779fe | 149 | return ERR_PTR(-EIO); |
015ba402 | 150 | |
0903ea60 BB |
151 | of_property_read_u32(node, "clock-accuracy", &accuracy); |
152 | ||
015ba402 GL |
153 | of_property_read_string(node, "clock-output-names", &clk_name); |
154 | ||
34e01833 | 155 | hw = clk_hw_register_fixed_rate_with_accuracy(NULL, clk_name, NULL, |
d3781a74 | 156 | 0, rate, accuracy); |
34e01833 SB |
157 | if (IS_ERR(hw)) |
158 | return hw; | |
435779fe | 159 | |
34e01833 | 160 | ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); |
435779fe | 161 | if (ret) { |
34e01833 | 162 | clk_hw_unregister_fixed_rate(hw); |
435779fe RR |
163 | return ERR_PTR(ret); |
164 | } | |
165 | ||
34e01833 | 166 | return hw; |
435779fe RR |
167 | } |
168 | ||
169 | /** | |
170 | * of_fixed_clk_setup() - Setup function for simple fixed rate clock | |
171 | */ | |
d336e9a7 | 172 | void __init of_fixed_clk_setup(struct device_node *node) |
435779fe RR |
173 | { |
174 | _of_fixed_clk_setup(node); | |
015ba402 | 175 | } |
f2f6c255 | 176 | CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup); |
435779fe RR |
177 | |
178 | static int of_fixed_clk_remove(struct platform_device *pdev) | |
179 | { | |
34e01833 | 180 | struct clk_hw *hw = platform_get_drvdata(pdev); |
435779fe | 181 | |
52091c25 | 182 | of_clk_del_provider(pdev->dev.of_node); |
34e01833 | 183 | clk_hw_unregister_fixed_rate(hw); |
435779fe RR |
184 | |
185 | return 0; | |
186 | } | |
187 | ||
188 | static int of_fixed_clk_probe(struct platform_device *pdev) | |
189 | { | |
34e01833 | 190 | struct clk_hw *hw; |
435779fe RR |
191 | |
192 | /* | |
193 | * This function is not executed when of_fixed_clk_setup | |
194 | * succeeded. | |
195 | */ | |
34e01833 SB |
196 | hw = _of_fixed_clk_setup(pdev->dev.of_node); |
197 | if (IS_ERR(hw)) | |
198 | return PTR_ERR(hw); | |
435779fe | 199 | |
34e01833 | 200 | platform_set_drvdata(pdev, hw); |
435779fe RR |
201 | |
202 | return 0; | |
203 | } | |
204 | ||
205 | static const struct of_device_id of_fixed_clk_ids[] = { | |
206 | { .compatible = "fixed-clock" }, | |
207 | { } | |
208 | }; | |
435779fe RR |
209 | |
210 | static struct platform_driver of_fixed_clk_driver = { | |
211 | .driver = { | |
212 | .name = "of_fixed_clk", | |
213 | .of_match_table = of_fixed_clk_ids, | |
214 | }, | |
215 | .probe = of_fixed_clk_probe, | |
216 | .remove = of_fixed_clk_remove, | |
217 | }; | |
218 | builtin_platform_driver(of_fixed_clk_driver); | |
015ba402 | 219 | #endif |