[linux.git] / drivers / edac / i82860_edac.c

/*
 * Intel 82860 Memory Controller kernel module
 * (C) 2005 Red Hat (http://www.redhat.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Ben Woodard <[email protected]>
 * shamelessly copied from and based upon the edac_i82875 driver
 * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_module.h"

#define EDAC_MOD_STR	"i82860_edac"

#define i82860_printk(level, fmt, arg...) \
	edac_printk(level, "i82860", fmt, ##arg)

#define i82860_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)

#ifndef PCI_DEVICE_ID_INTEL_82860_0
#define PCI_DEVICE_ID_INTEL_82860_0	0x2531
#endif				/* PCI_DEVICE_ID_INTEL_82860_0 */

#define I82860_MCHCFG 0x50
#define I82860_GBA 0x60
#define I82860_GBA_MASK 0x7FF
#define I82860_GBA_SHIFT 24
#define I82860_ERRSTS 0xC8
#define I82860_EAP 0xE4
#define I82860_DERRCTL_STS 0xE2

enum i82860_chips {
	I82860 = 0,
};

struct i82860_dev_info {
	const char *ctl_name;
};

struct i82860_error_info {
	u16 errsts;
	u32 eap;
	u16 derrsyn;
	u16 errsts2;
};

static const struct i82860_dev_info i82860_devs[] = {
	[I82860] = {
		.ctl_name = "i82860"},
};

static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code
					 * has already registered driver
					 */
static struct edac_pci_ctl_info *i82860_pci;

static void i82860_get_error_info(struct mem_ctl_info *mci,
				struct i82860_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);

	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);

	/*
	 * If the error is the same for both reads then the first set of reads
	 * is valid.  If there is a change then there is a CE no info and the
	 * second set of reads is valid and should be UE info.
	 */
	if (!(info->errsts2 & 0x0003))
		return;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		pci_read_config_dword(pdev, I82860_EAP, &info->eap);
		pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	}
}

static int i82860_process_error_info(struct mem_ctl_info *mci,
				struct i82860_error_info *info,
				int handle_errors)
{
	struct dimm_info *dimm;
	int row;

	if (!(info->errsts2 & 0x0003))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & 0x0003) {
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
				     -1, -1, -1, "UE overwrote CE", "");
		info->errsts = info->errsts2;
	}

	info->eap >>= PAGE_SHIFT;
	row = edac_mc_find_csrow_by_page(mci, info->eap);
	dimm = mci->csrows[row]->channels[0]->dimm;

	if (info->errsts & 0x0002)
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
				     info->eap, 0, 0,
				     dimm->location[0], dimm->location[1], -1,
				     "i82860 UE", "");
	else
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
				     info->eap, 0, info->derrsyn,
				     dimm->location[0], dimm->location[1], -1,
				     "i82860 CE", "");

	return 1;
}

static void i82860_check(struct mem_ctl_info *mci)
{
	struct i82860_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	i82860_get_error_info(mci, &info);
	i82860_process_error_info(mci, &info, 1);
}

static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
{
	unsigned long last_cumul_size;
	u16 mchcfg_ddim;	/* DRAM Data Integrity Mode 0=none, 2=edac */
	u16 value;
	u32 cumul_size;
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	int index;

	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
	mchcfg_ddim = mchcfg_ddim & 0x180;
	last_cumul_size = 0;

	/* The group row boundary (GRA) reg values are boundary address
	 * for each DRAM row with a granularity of 16MB.  GRA regs are
	 * cumulative; therefore GRA15 will contain the total memory contained
	 * in all eight rows.
	 */
	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = mci->csrows[index];
		dimm = csrow->channels[0]->dimm;

		pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
		cumul_size = (value & I82860_GBA_MASK) <<
			(I82860_GBA_SHIFT - PAGE_SHIFT);
		edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);

		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		dimm->nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;
		dimm->grain = 1 << 12;	/* I82860_EAP has 4KiB reolution */
		dimm->mtype = MEM_RMBS;
		dimm->dtype = DEV_UNKNOWN;
		dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
	}
}

static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
{
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[2];
	struct i82860_error_info discard;

	/*
	 * RDRAM has channels but these don't map onto the csrow abstraction.
	 * According with the datasheet, there are 2 Rambus channels, supporting
	 * up to 16 direct RDRAM devices.
	 * The device groups from the GRA registers seem to map reasonably
	 * well onto the notion of a chip select row.
	 * There are 16 GRA registers and since the name is associated with
	 * the channel and the GRA registers map to physical devices so we are
	 * going to make 1 channel for group.
	 */
	layers[0].type = EDAC_MC_LAYER_CHANNEL;
	layers[0].size = 2;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_SLOT;
	layers[1].size = 8;
	layers[1].is_virt_csrow = true;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
	if (!mci)
		return -ENOMEM;

	edac_dbg(3, "init mci\n");
	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	/* I"m not sure about this but I think that all RDRAM is SECDED */
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = EDAC_MOD_STR;
	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i82860_check;
	mci->ctl_page_to_phys = NULL;
	i82860_init_csrows(mci, pdev);
	i82860_get_error_info(mci, &discard);	/* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* allocating generic PCI control info */
	i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i82860_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	edac_dbg(3, "success\n");

	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int i82860_init_one(struct pci_dev *pdev,
			   const struct pci_device_id *ent)
{
	int rc;

	edac_dbg(0, "\n");
	i82860_printk(KERN_INFO, "i82860 init one\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i82860_probe1(pdev, ent->driver_data);

	if (rc == 0)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void i82860_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	if (i82860_pci)
		edac_pci_release_generic_ctl(i82860_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id i82860_pci_tbl[] = {
	{
	 PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I82860},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);

static struct pci_driver i82860_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82860_init_one,
	.remove = i82860_remove_one,
	.id_table = i82860_pci_tbl,
};

static int __init i82860_init(void)
{
	int pci_rc;

	edac_dbg(3, "\n");

       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
		goto fail0;

	if (!mci_pdev) {
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_82860_0, NULL);

		if (mci_pdev == NULL) {
			edac_dbg(0, "860 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);

		if (pci_rc < 0) {
			edac_dbg(0, "860 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i82860_driver);

fail0:
	pci_dev_put(mci_pdev);
	return pci_rc;
}

static void __exit i82860_exit(void)
{
	edac_dbg(3, "\n");
	pci_unregister_driver(&i82860_driver);
	pci_dev_put(mci_pdev);
}

module_init(i82860_init);
module_exit(i82860_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
		"Ben Woodard <[email protected]>");
MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
0d88a10e AC	1	/*
	2	* Intel 82860 Memory Controller kernel module
	3	* (C) 2005 Red Hat (http://www.redhat.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Ben Woodard <[email protected]>
	8	* shamelessly copied from and based upon the edac_i82875 driver
	9	* by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
	10	*/
	11
0d88a10e AC	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
c3c52bce	16	#include <linux/edac.h>
78d88e8a	17	#include "edac_module.h"
0d88a10e	18
929a40ec	19	#define EDAC_MOD_STR "i82860_edac"
37f04581	20
537fba28	21	#define i82860_printk(level, fmt, arg...) \
e7ecd891	22	edac_printk(level, "i82860", fmt, ##arg)
537fba28 DP	23
537fba28 DP	24	#define i82860_mc_printk(mci, level, fmt, arg...) \
e7ecd891	25	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
537fba28	26
0d88a10e AC	27	#ifndef PCI_DEVICE_ID_INTEL_82860_0
	28	#define PCI_DEVICE_ID_INTEL_82860_0 0x2531
	29	#endif /* PCI_DEVICE_ID_INTEL_82860_0 */
	30
	31	#define I82860_MCHCFG 0x50
	32	#define I82860_GBA 0x60
	33	#define I82860_GBA_MASK 0x7FF
	34	#define I82860_GBA_SHIFT 24
	35	#define I82860_ERRSTS 0xC8
	36	#define I82860_EAP 0xE4
	37	#define I82860_DERRCTL_STS 0xE2
	38
	39	enum i82860_chips {
	40	I82860 = 0,
	41	};
	42
	43	struct i82860_dev_info {
	44	const char *ctl_name;
	45	};
	46
	47	struct i82860_error_info {
	48	u16 errsts;
	49	u32 eap;
	50	u16 derrsyn;
	51	u16 errsts2;
	52	};
	53
	54	static const struct i82860_dev_info i82860_devs[] = {
	55	[I82860] = {
052dfb45	56	.ctl_name = "i82860"},
0d88a10e AC	57	};
0d88a10e AC	58
f044091c	59	static struct pci_dev mci_pdev; / init dev: in case that AGP code
e7ecd891 DP	60	* has already registered driver
e7ecd891 DP	61	*/
456a2f95	62	static struct edac_pci_ctl_info *i82860_pci;
0d88a10e	63
e7ecd891	64	static void i82860_get_error_info(struct mem_ctl_info *mci,
052dfb45	65	struct i82860_error_info *info)
0d88a10e	66	{
37f04581 DT	67	struct pci_dev *pdev;
37f04581 DT	68
fd687502	69	pdev = to_pci_dev(mci->pdev);
37f04581	70
0d88a10e AC	71	/*
	72	* This is a mess because there is no atomic way to read all the
	73	* registers at once and the registers can transition from CE being
	74	* overwritten by UE.
	75	*/
37f04581 DT	76	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
	77	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
	78	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
	79	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
0d88a10e	80
37f04581	81	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
0d88a10e AC	82
	83	/*
	84	* If the error is the same for both reads then the first set of reads
	85	* is valid. If there is a change then there is a CE no info and the
	86	* second set of reads is valid and should be UE info.
	87	*/
	88	if (!(info->errsts2 & 0x0003))
	89	return;
e7ecd891	90
0d88a10e	91	if ((info->errsts ^ info->errsts2) & 0x0003) {
37f04581	92	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
b4e8b372	93	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
0d88a10e AC	94	}
	95	}
	96
e7ecd891	97	static int i82860_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	98	struct i82860_error_info *info,
052dfb45 DT	99	int handle_errors)
0d88a10e	100	{
84c3a684	101	struct dimm_info *dimm;
0d88a10e AC	102	int row;
	103
	104	if (!(info->errsts2 & 0x0003))
	105	return 0;
	106
	107	if (!handle_errors)
	108	return 1;
	109
	110	if ((info->errsts ^ info->errsts2) & 0x0003) {
9eb07a7f	111	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
03f7eae8	112	-1, -1, -1, "UE overwrote CE", "");
0d88a10e AC	113	info->errsts = info->errsts2;
	114	}
	115
	116	info->eap >>= PAGE_SHIFT;
	117	row = edac_mc_find_csrow_by_page(mci, info->eap);
de3910eb	118	dimm = mci->csrows[row]->channels[0]->dimm;
0d88a10e AC	119
0d88a10e AC	120	if (info->errsts & 0x0002)
9eb07a7f	121	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
84c3a684 MCC	122	info->eap, 0, 0,
84c3a684 MCC	123	dimm->location[0], dimm->location[1], -1,
03f7eae8	124	"i82860 UE", "");
0d88a10e	125	else
ab0543de	126	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
84c3a684 MCC	127	info->eap, 0, info->derrsyn,
84c3a684 MCC	128	dimm->location[0], dimm->location[1], -1,
03f7eae8	129	"i82860 CE", "");
0d88a10e AC	130
	131	return 1;
	132	}
	133
	134	static void i82860_check(struct mem_ctl_info *mci)
	135	{
	136	struct i82860_error_info info;
	137
956b9ba1	138	edac_dbg(1, "MC%d\n", mci->mc_idx);
0d88a10e AC	139	i82860_get_error_info(mci, &info);
	140	i82860_process_error_info(mci, &info, 1);
	141	}
	142
13189525	143	static void i82860_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev)
0d88a10e	144	{
0d88a10e	145	unsigned long last_cumul_size;
b4e8b372	146	u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
13189525 DT	147	u16 value;
	148	u32 cumul_size;
	149	struct csrow_info *csrow;
084a4fcc	150	struct dimm_info *dimm;
13189525 DT	151	int index;
	152
	153	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
	154	mchcfg_ddim = mchcfg_ddim & 0x180;
	155	last_cumul_size = 0;
	156
	157	/* The group row boundary (GRA) reg values are boundary address
	158	* for each DRAM row with a granularity of 16MB. GRA regs are
	159	* cumulative; therefore GRA15 will contain the total memory contained
	160	* in all eight rows.
	161	*/
	162	for (index = 0; index < mci->nr_csrows; index++) {
de3910eb MCC	163	csrow = mci->csrows[index];
de3910eb MCC	164	dimm = csrow->channels[0]->dimm;
084a4fcc	165
13189525 DT	166	pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
13189525 DT	167	cumul_size = (value & I82860_GBA_MASK) <<
052dfb45	168	(I82860_GBA_SHIFT - PAGE_SHIFT);
956b9ba1	169	edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
0d88a10e	170
13189525 DT	171	if (cumul_size == last_cumul_size)
	172	continue; /* not populated */
	173
	174	csrow->first_page = last_cumul_size;
	175	csrow->last_page = cumul_size - 1;
a895bf8b	176	dimm->nr_pages = cumul_size - last_cumul_size;
13189525	177	last_cumul_size = cumul_size;
084a4fcc MCC	178	dimm->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
	179	dimm->mtype = MEM_RMBS;
	180	dimm->dtype = DEV_UNKNOWN;
	181	dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
13189525 DT	182	}
	183	}
	184
	185	static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
	186	{
	187	struct mem_ctl_info *mci;
84c3a684	188	struct edac_mc_layer layers[2];
13189525	189	struct i82860_error_info discard;
0d88a10e	190
84c3a684 MCC	191	/*
	192	* RDRAM has channels but these don't map onto the csrow abstraction.
	193	* According with the datasheet, there are 2 Rambus channels, supporting
	194	* up to 16 direct RDRAM devices.
	195	* The device groups from the GRA registers seem to map reasonably
	196	* well onto the notion of a chip select row.
	197	* There are 16 GRA registers and since the name is associated with
	198	* the channel and the GRA registers map to physical devices so we are
	199	* going to make 1 channel for group.
0d88a10e	200	*/
84c3a684 MCC	201	layers[0].type = EDAC_MC_LAYER_CHANNEL;
	202	layers[0].size = 2;
	203	layers[0].is_virt_csrow = true;
	204	layers[1].type = EDAC_MC_LAYER_SLOT;
	205	layers[1].size = 8;
	206	layers[1].is_virt_csrow = true;
ca0907b9	207	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
0d88a10e AC	208	if (!mci)
	209	return -ENOMEM;
	210
956b9ba1	211	edac_dbg(3, "init mci\n");
fd687502	212	mci->pdev = &pdev->dev;
0d88a10e	213	mci->mtype_cap = MEM_FLAG_DDR;
0d88a10e AC	214	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	215	/* I"m not sure about this but I think that all RDRAM is SECDED */
	216	mci->edac_cap = EDAC_FLAG_SECDED;
680cbbbb	217	mci->mod_name = EDAC_MOD_STR;
0d88a10e	218	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
c4192705	219	mci->dev_name = pci_name(pdev);
0d88a10e AC	220	mci->edac_check = i82860_check;
0d88a10e AC	221	mci->ctl_page_to_phys = NULL;
13189525	222	i82860_init_csrows(mci, pdev);
b4e8b372	223	i82860_get_error_info(mci, &discard); /* clear counters */
0d88a10e	224
2d7bbb91 DT	225	/* Here we assume that we will never see multiple instances of this
	226	* type of memory controller. The ID is therefore hardcoded to 0.
	227	*/
b8f6f975	228	if (edac_mc_add_mc(mci)) {
956b9ba1	229	edac_dbg(3, "failed edac_mc_add_mc()\n");
13189525	230	goto fail;
0d88a10e	231	}
e7ecd891	232
456a2f95 DJ	233	/* allocating generic PCI control info */
	234	i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	235	if (!i82860_pci) {
	236	printk(KERN_WARNING
	237	"%s(): Unable to create PCI control\n",
	238	__func__);
	239	printk(KERN_WARNING
	240	"%s(): PCI error report via EDAC not setup\n",
	241	__func__);
	242	}
	243
13189525	244	/* get this far and it's successful */
956b9ba1	245	edac_dbg(3, "success\n");
13189525 DT	246
	247	return 0;
	248
052dfb45	249	fail:
13189525 DT	250	edac_mc_free(mci);
13189525 DT	251	return -ENODEV;
0d88a10e AC	252	}
	253
	254	/* returns count (>= 0), or negative on error */
9b3c6e85 GKH	255	static int i82860_init_one(struct pci_dev *pdev,
9b3c6e85 GKH	256	const struct pci_device_id *ent)
0d88a10e AC	257	{
	258	int rc;
	259
956b9ba1	260	edac_dbg(0, "\n");
537fba28	261	i82860_printk(KERN_INFO, "i82860 init one\n");
e7ecd891 DP	262
e7ecd891 DP	263	if (pci_enable_device(pdev) < 0)
0d88a10e	264	return -EIO;
e7ecd891	265
0d88a10e	266	rc = i82860_probe1(pdev, ent->driver_data);
e7ecd891 DP	267
e7ecd891 DP	268	if (rc == 0)
0d88a10e	269	mci_pdev = pci_dev_get(pdev);
e7ecd891	270
0d88a10e AC	271	return rc;
	272	}
	273
9b3c6e85	274	static void i82860_remove_one(struct pci_dev *pdev)
0d88a10e AC	275	{
	276	struct mem_ctl_info *mci;
	277
956b9ba1	278	edac_dbg(0, "\n");
0d88a10e	279
456a2f95 DJ	280	if (i82860_pci)
	281	edac_pci_release_generic_ctl(i82860_pci);
	282
37f04581	283	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
18dbc337 DP	284	return;
	285
	286	edac_mc_free(mci);
0d88a10e AC	287	}
0d88a10e AC	288
ba935f40	289	static const struct pci_device_id i82860_pci_tbl[] = {
e7ecd891	290	{
b4e8b372 DJ	291	PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
b4e8b372 DJ	292	I82860},
e7ecd891	293	{
b4e8b372 DJ	294	0,
b4e8b372 DJ	295	} /* 0 terminated list. */
0d88a10e AC	296	};
	297
	298	MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
	299
	300	static struct pci_driver i82860_driver = {
680cbbbb	301	.name = EDAC_MOD_STR,
0d88a10e	302	.probe = i82860_init_one,
9b3c6e85	303	.remove = i82860_remove_one,
0d88a10e AC	304	.id_table = i82860_pci_tbl,
	305	};
	306
da9bb1d2	307	static int __init i82860_init(void)
0d88a10e AC	308	{
	309	int pci_rc;
	310
956b9ba1	311	edac_dbg(3, "\n");
e7ecd891	312
c3c52bce HM	313	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	314	opstate_init();
	315
0d88a10e	316	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
e8a491b4	317	goto fail0;
0d88a10e AC	318
0d88a10e AC	319	if (!mci_pdev) {
0d88a10e	320	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45	321	PCI_DEVICE_ID_INTEL_82860_0, NULL);
e7ecd891	322
0d88a10e	323	if (mci_pdev == NULL) {
956b9ba1	324	edac_dbg(0, "860 pci_get_device fail\n");
e8a491b4 DP	325	pci_rc = -ENODEV;
e8a491b4 DP	326	goto fail1;
0d88a10e	327	}
e7ecd891	328
0d88a10e	329	pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
e7ecd891	330
0d88a10e	331	if (pci_rc < 0) {
956b9ba1	332	edac_dbg(0, "860 init fail\n");
e8a491b4 DP	333	pci_rc = -ENODEV;
e8a491b4 DP	334	goto fail1;
0d88a10e AC	335	}
0d88a10e AC	336	}
e7ecd891	337
0d88a10e	338	return 0;
e8a491b4	339
052dfb45	340	fail1:
e8a491b4 DP	341	pci_unregister_driver(&i82860_driver);
e8a491b4 DP	342
052dfb45	343	fail0:
72601945	344	pci_dev_put(mci_pdev);
e8a491b4	345	return pci_rc;
0d88a10e AC	346	}
	347
	348	static void __exit i82860_exit(void)
	349	{
956b9ba1	350	edac_dbg(3, "\n");
0d88a10e	351	pci_unregister_driver(&i82860_driver);
72601945	352	pci_dev_put(mci_pdev);
0d88a10e AC	353	}
	354
	355	module_init(i82860_init);
	356	module_exit(i82860_exit);
	357
	358	MODULE_LICENSE("GPL");
e7ecd891	359	MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
052dfb45	360	"Ben Woodard <[email protected]>");
0d88a10e	361	MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
c3c52bce HM	362
	363	module_param(edac_op_state, int, 0444);
	364	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");