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f507cd22 GU |
1 | /* |
2 | * ps3vram - Use extra PS3 video ram as MTD block device. | |
3 | * | |
4 | * Copyright 2009 Sony Corporation | |
5 | * | |
6 | * Based on the MTD ps3vram driver, which is | |
7 | * Copyright (c) 2007-2008 Jim Paris <[email protected]> | |
8 | * Added support RSX DMA Vivien Chappelier <[email protected]> | |
9 | */ | |
10 | ||
11 | #include <linux/blkdev.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/proc_fs.h> | |
14 | #include <linux/seq_file.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
f507cd22 | 16 | |
9413c883 | 17 | #include <asm/cell-regs.h> |
f507cd22 GU |
18 | #include <asm/firmware.h> |
19 | #include <asm/lv1call.h> | |
20 | #include <asm/ps3.h> | |
d3352c9f | 21 | #include <asm/ps3gpu.h> |
f507cd22 GU |
22 | |
23 | ||
24 | #define DEVICE_NAME "ps3vram" | |
25 | ||
26 | ||
27 | #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */ | |
28 | #define XDR_IOIF 0x0c000000 | |
29 | ||
30 | #define FIFO_BASE XDR_IOIF | |
31 | #define FIFO_SIZE (64 * 1024) | |
32 | ||
33 | #define DMA_PAGE_SIZE (4 * 1024) | |
34 | ||
35 | #define CACHE_PAGE_SIZE (256 * 1024) | |
36 | #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE) | |
37 | ||
38 | #define CACHE_OFFSET CACHE_PAGE_SIZE | |
39 | #define FIFO_OFFSET 0 | |
40 | ||
41 | #define CTRL_PUT 0x10 | |
42 | #define CTRL_GET 0x11 | |
43 | #define CTRL_TOP 0x15 | |
44 | ||
45 | #define UPLOAD_SUBCH 1 | |
46 | #define DOWNLOAD_SUBCH 2 | |
47 | ||
48 | #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c | |
49 | #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 | |
50 | ||
f507cd22 GU |
51 | #define CACHE_PAGE_PRESENT 1 |
52 | #define CACHE_PAGE_DIRTY 2 | |
53 | ||
54 | struct ps3vram_tag { | |
55 | unsigned int address; | |
56 | unsigned int flags; | |
57 | }; | |
58 | ||
59 | struct ps3vram_cache { | |
60 | unsigned int page_count; | |
61 | unsigned int page_size; | |
62 | struct ps3vram_tag *tags; | |
63 | unsigned int hit; | |
64 | unsigned int miss; | |
65 | }; | |
66 | ||
67 | struct ps3vram_priv { | |
68 | struct request_queue *queue; | |
69 | struct gendisk *gendisk; | |
70 | ||
71 | u64 size; | |
72 | ||
73 | u64 memory_handle; | |
74 | u64 context_handle; | |
75 | u32 *ctrl; | |
1bd9784f | 76 | void *reports; |
f507cd22 GU |
77 | u8 *xdr_buf; |
78 | ||
79 | u32 *fifo_base; | |
80 | u32 *fifo_ptr; | |
81 | ||
82 | struct ps3vram_cache cache; | |
83 | ||
fb89e89d GU |
84 | spinlock_t lock; /* protecting list of bios */ |
85 | struct bio_list list; | |
f507cd22 GU |
86 | }; |
87 | ||
88 | ||
89 | static int ps3vram_major; | |
90 | ||
91 | ||
83d5cde4 | 92 | static const struct block_device_operations ps3vram_fops = { |
f507cd22 GU |
93 | .owner = THIS_MODULE, |
94 | }; | |
95 | ||
96 | ||
97 | #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */ | |
98 | #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */ | |
99 | #define DMA_NOTIFIER_SIZE 0x40 | |
100 | #define NOTIFIER 7 /* notifier used for completion report */ | |
101 | ||
102 | static char *size = "256M"; | |
103 | module_param(size, charp, 0); | |
104 | MODULE_PARM_DESC(size, "memory size"); | |
105 | ||
1bd9784f | 106 | static u32 *ps3vram_get_notifier(void *reports, int notifier) |
f507cd22 | 107 | { |
1bd9784f | 108 | return reports + DMA_NOTIFIER_OFFSET_BASE + |
f507cd22 GU |
109 | DMA_NOTIFIER_SIZE * notifier; |
110 | } | |
111 | ||
112 | static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev) | |
113 | { | |
03fa68c2 | 114 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
115 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); |
116 | int i; | |
117 | ||
118 | for (i = 0; i < 4; i++) | |
119 | notify[i] = 0xffffffff; | |
120 | } | |
121 | ||
122 | static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev, | |
123 | unsigned int timeout_ms) | |
124 | { | |
03fa68c2 | 125 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 | 126 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); |
f21121cd HS |
127 | unsigned long timeout; |
128 | ||
129 | for (timeout = 20; timeout; timeout--) { | |
130 | if (!notify[3]) | |
131 | return 0; | |
132 | udelay(10); | |
133 | } | |
134 | ||
135 | timeout = jiffies + msecs_to_jiffies(timeout_ms); | |
f507cd22 GU |
136 | |
137 | do { | |
138 | if (!notify[3]) | |
139 | return 0; | |
140 | msleep(1); | |
141 | } while (time_before(jiffies, timeout)); | |
142 | ||
143 | return -ETIMEDOUT; | |
144 | } | |
145 | ||
146 | static void ps3vram_init_ring(struct ps3_system_bus_device *dev) | |
147 | { | |
03fa68c2 | 148 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
149 | |
150 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | |
151 | priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET; | |
152 | } | |
153 | ||
154 | static int ps3vram_wait_ring(struct ps3_system_bus_device *dev, | |
155 | unsigned int timeout_ms) | |
156 | { | |
03fa68c2 | 157 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
158 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); |
159 | ||
160 | do { | |
161 | if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET]) | |
162 | return 0; | |
163 | msleep(1); | |
164 | } while (time_before(jiffies, timeout)); | |
165 | ||
166 | dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n", | |
167 | priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET], | |
168 | priv->ctrl[CTRL_TOP]); | |
169 | ||
170 | return -ETIMEDOUT; | |
171 | } | |
172 | ||
173 | static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data) | |
174 | { | |
175 | *(priv->fifo_ptr)++ = data; | |
176 | } | |
177 | ||
178 | static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag, | |
179 | u32 size) | |
180 | { | |
181 | ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag); | |
182 | } | |
183 | ||
184 | static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev) | |
185 | { | |
03fa68c2 | 186 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
187 | int status; |
188 | ||
189 | ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET)); | |
190 | ||
191 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | |
192 | ||
193 | /* asking the HV for a blit will kick the FIFO */ | |
d3352c9f | 194 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
f507cd22 | 195 | if (status) |
d3352c9f GU |
196 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", |
197 | __func__, status); | |
f507cd22 GU |
198 | |
199 | priv->fifo_ptr = priv->fifo_base; | |
200 | } | |
201 | ||
202 | static void ps3vram_fire_ring(struct ps3_system_bus_device *dev) | |
203 | { | |
03fa68c2 | 204 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
205 | int status; |
206 | ||
207 | mutex_lock(&ps3_gpu_mutex); | |
208 | ||
209 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET + | |
210 | (priv->fifo_ptr - priv->fifo_base) * sizeof(u32); | |
211 | ||
212 | /* asking the HV for a blit will kick the FIFO */ | |
d3352c9f | 213 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
f507cd22 | 214 | if (status) |
d3352c9f GU |
215 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", |
216 | __func__, status); | |
f507cd22 GU |
217 | |
218 | if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) > | |
219 | FIFO_SIZE - 1024) { | |
220 | dev_dbg(&dev->core, "FIFO full, rewinding\n"); | |
221 | ps3vram_wait_ring(dev, 200); | |
222 | ps3vram_rewind_ring(dev); | |
223 | } | |
224 | ||
225 | mutex_unlock(&ps3_gpu_mutex); | |
226 | } | |
227 | ||
228 | static void ps3vram_bind(struct ps3_system_bus_device *dev) | |
229 | { | |
03fa68c2 | 230 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
231 | |
232 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1); | |
233 | ps3vram_out_ring(priv, 0x31337303); | |
234 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3); | |
235 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | |
236 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | |
237 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | |
238 | ||
239 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1); | |
240 | ps3vram_out_ring(priv, 0x3137c0de); | |
241 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3); | |
242 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | |
243 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | |
244 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | |
245 | ||
246 | ps3vram_fire_ring(dev); | |
247 | } | |
248 | ||
249 | static int ps3vram_upload(struct ps3_system_bus_device *dev, | |
250 | unsigned int src_offset, unsigned int dst_offset, | |
251 | int len, int count) | |
252 | { | |
03fa68c2 | 253 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
254 | |
255 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | |
256 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
257 | ps3vram_out_ring(priv, XDR_IOIF + src_offset); | |
258 | ps3vram_out_ring(priv, dst_offset); | |
259 | ps3vram_out_ring(priv, len); | |
260 | ps3vram_out_ring(priv, len); | |
261 | ps3vram_out_ring(priv, len); | |
262 | ps3vram_out_ring(priv, count); | |
263 | ps3vram_out_ring(priv, (1 << 8) | 1); | |
264 | ps3vram_out_ring(priv, 0); | |
265 | ||
266 | ps3vram_notifier_reset(dev); | |
267 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | |
268 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | |
269 | ps3vram_out_ring(priv, 0); | |
270 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1); | |
271 | ps3vram_out_ring(priv, 0); | |
272 | ps3vram_fire_ring(dev); | |
273 | if (ps3vram_notifier_wait(dev, 200) < 0) { | |
274 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | |
275 | return -1; | |
276 | } | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
281 | static int ps3vram_download(struct ps3_system_bus_device *dev, | |
282 | unsigned int src_offset, unsigned int dst_offset, | |
283 | int len, int count) | |
284 | { | |
03fa68c2 | 285 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
286 | |
287 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | |
288 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
289 | ps3vram_out_ring(priv, src_offset); | |
290 | ps3vram_out_ring(priv, XDR_IOIF + dst_offset); | |
291 | ps3vram_out_ring(priv, len); | |
292 | ps3vram_out_ring(priv, len); | |
293 | ps3vram_out_ring(priv, len); | |
294 | ps3vram_out_ring(priv, count); | |
295 | ps3vram_out_ring(priv, (1 << 8) | 1); | |
296 | ps3vram_out_ring(priv, 0); | |
297 | ||
298 | ps3vram_notifier_reset(dev); | |
299 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | |
300 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | |
301 | ps3vram_out_ring(priv, 0); | |
302 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1); | |
303 | ps3vram_out_ring(priv, 0); | |
304 | ps3vram_fire_ring(dev); | |
305 | if (ps3vram_notifier_wait(dev, 200) < 0) { | |
306 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | |
307 | return -1; | |
308 | } | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry) | |
314 | { | |
03fa68c2 | 315 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
316 | struct ps3vram_cache *cache = &priv->cache; |
317 | ||
318 | if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY)) | |
319 | return; | |
320 | ||
321 | dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry, | |
322 | cache->tags[entry].address); | |
323 | if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size, | |
324 | cache->tags[entry].address, DMA_PAGE_SIZE, | |
325 | cache->page_size / DMA_PAGE_SIZE) < 0) { | |
326 | dev_err(&dev->core, | |
327 | "Failed to upload from 0x%x to " "0x%x size 0x%x\n", | |
328 | entry * cache->page_size, cache->tags[entry].address, | |
329 | cache->page_size); | |
330 | } | |
331 | cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; | |
332 | } | |
333 | ||
334 | static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry, | |
335 | unsigned int address) | |
336 | { | |
03fa68c2 | 337 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
338 | struct ps3vram_cache *cache = &priv->cache; |
339 | ||
340 | dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address); | |
341 | if (ps3vram_download(dev, address, | |
342 | CACHE_OFFSET + entry * cache->page_size, | |
343 | DMA_PAGE_SIZE, | |
344 | cache->page_size / DMA_PAGE_SIZE) < 0) { | |
345 | dev_err(&dev->core, | |
346 | "Failed to download from 0x%x to 0x%x size 0x%x\n", | |
347 | address, entry * cache->page_size, cache->page_size); | |
348 | } | |
349 | ||
350 | cache->tags[entry].address = address; | |
351 | cache->tags[entry].flags |= CACHE_PAGE_PRESENT; | |
352 | } | |
353 | ||
354 | ||
355 | static void ps3vram_cache_flush(struct ps3_system_bus_device *dev) | |
356 | { | |
03fa68c2 | 357 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
358 | struct ps3vram_cache *cache = &priv->cache; |
359 | int i; | |
360 | ||
361 | dev_dbg(&dev->core, "FLUSH\n"); | |
362 | for (i = 0; i < cache->page_count; i++) { | |
363 | ps3vram_cache_evict(dev, i); | |
364 | cache->tags[i].flags = 0; | |
365 | } | |
366 | } | |
367 | ||
368 | static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev, | |
369 | loff_t address) | |
370 | { | |
03fa68c2 | 371 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
372 | struct ps3vram_cache *cache = &priv->cache; |
373 | unsigned int base; | |
374 | unsigned int offset; | |
375 | int i; | |
376 | static int counter; | |
377 | ||
378 | offset = (unsigned int) (address & (cache->page_size - 1)); | |
379 | base = (unsigned int) (address - offset); | |
380 | ||
381 | /* fully associative check */ | |
382 | for (i = 0; i < cache->page_count; i++) { | |
383 | if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) && | |
384 | cache->tags[i].address == base) { | |
385 | cache->hit++; | |
386 | dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i, | |
387 | cache->tags[i].address); | |
388 | return i; | |
389 | } | |
390 | } | |
391 | ||
392 | /* choose a random entry */ | |
393 | i = (jiffies + (counter++)) % cache->page_count; | |
394 | dev_dbg(&dev->core, "Using entry %d\n", i); | |
395 | ||
396 | ps3vram_cache_evict(dev, i); | |
397 | ps3vram_cache_load(dev, i, base); | |
398 | ||
399 | cache->miss++; | |
400 | return i; | |
401 | } | |
402 | ||
403 | static int ps3vram_cache_init(struct ps3_system_bus_device *dev) | |
404 | { | |
03fa68c2 | 405 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
406 | |
407 | priv->cache.page_count = CACHE_PAGE_COUNT; | |
408 | priv->cache.page_size = CACHE_PAGE_SIZE; | |
409 | priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) * | |
410 | CACHE_PAGE_COUNT, GFP_KERNEL); | |
411 | if (priv->cache.tags == NULL) { | |
412 | dev_err(&dev->core, "Could not allocate cache tags\n"); | |
413 | return -ENOMEM; | |
414 | } | |
415 | ||
416 | dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n", | |
417 | CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024); | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev) | |
423 | { | |
03fa68c2 | 424 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
425 | |
426 | ps3vram_cache_flush(dev); | |
427 | kfree(priv->cache.tags); | |
428 | } | |
429 | ||
430 | static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from, | |
431 | size_t len, size_t *retlen, u_char *buf) | |
432 | { | |
03fa68c2 | 433 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
434 | unsigned int cached, count; |
435 | ||
436 | dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__, | |
437 | (unsigned int)from, len); | |
438 | ||
439 | if (from >= priv->size) | |
440 | return -EIO; | |
441 | ||
442 | if (len > priv->size - from) | |
443 | len = priv->size - from; | |
444 | ||
445 | /* Copy from vram to buf */ | |
446 | count = len; | |
447 | while (count) { | |
448 | unsigned int offset, avail; | |
449 | unsigned int entry; | |
450 | ||
451 | offset = (unsigned int) (from & (priv->cache.page_size - 1)); | |
452 | avail = priv->cache.page_size - offset; | |
453 | ||
f507cd22 GU |
454 | entry = ps3vram_cache_match(dev, from); |
455 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | |
456 | ||
457 | dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x " | |
458 | "avail=%08x count=%08x\n", __func__, | |
459 | (unsigned int)from, cached, offset, avail, count); | |
460 | ||
461 | if (avail > count) | |
462 | avail = count; | |
463 | memcpy(buf, priv->xdr_buf + cached, avail); | |
464 | ||
f507cd22 GU |
465 | buf += avail; |
466 | count -= avail; | |
467 | from += avail; | |
468 | } | |
469 | ||
470 | *retlen = len; | |
471 | return 0; | |
472 | } | |
473 | ||
474 | static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to, | |
475 | size_t len, size_t *retlen, const u_char *buf) | |
476 | { | |
03fa68c2 | 477 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
478 | unsigned int cached, count; |
479 | ||
480 | if (to >= priv->size) | |
481 | return -EIO; | |
482 | ||
483 | if (len > priv->size - to) | |
484 | len = priv->size - to; | |
485 | ||
486 | /* Copy from buf to vram */ | |
487 | count = len; | |
488 | while (count) { | |
489 | unsigned int offset, avail; | |
490 | unsigned int entry; | |
491 | ||
492 | offset = (unsigned int) (to & (priv->cache.page_size - 1)); | |
493 | avail = priv->cache.page_size - offset; | |
494 | ||
f507cd22 GU |
495 | entry = ps3vram_cache_match(dev, to); |
496 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | |
497 | ||
498 | dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x " | |
499 | "avail=%08x count=%08x\n", __func__, (unsigned int)to, | |
500 | cached, offset, avail, count); | |
501 | ||
502 | if (avail > count) | |
503 | avail = count; | |
504 | memcpy(priv->xdr_buf + cached, buf, avail); | |
505 | ||
506 | priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY; | |
507 | ||
f507cd22 GU |
508 | buf += avail; |
509 | count -= avail; | |
510 | to += avail; | |
511 | } | |
512 | ||
513 | *retlen = len; | |
514 | return 0; | |
515 | } | |
516 | ||
517 | static int ps3vram_proc_show(struct seq_file *m, void *v) | |
518 | { | |
519 | struct ps3vram_priv *priv = m->private; | |
520 | ||
521 | seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss); | |
522 | return 0; | |
523 | } | |
524 | ||
525 | static int ps3vram_proc_open(struct inode *inode, struct file *file) | |
526 | { | |
527 | return single_open(file, ps3vram_proc_show, PDE(inode)->data); | |
528 | } | |
529 | ||
530 | static const struct file_operations ps3vram_proc_fops = { | |
531 | .owner = THIS_MODULE, | |
532 | .open = ps3vram_proc_open, | |
533 | .read = seq_read, | |
534 | .llseek = seq_lseek, | |
535 | .release = single_release, | |
536 | }; | |
537 | ||
538 | static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev) | |
539 | { | |
03fa68c2 | 540 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
541 | struct proc_dir_entry *pde; |
542 | ||
3c20e2f2 GU |
543 | pde = proc_create_data(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops, |
544 | priv); | |
545 | if (!pde) | |
f507cd22 | 546 | dev_warn(&dev->core, "failed to create /proc entry\n"); |
f507cd22 GU |
547 | } |
548 | ||
fb89e89d GU |
549 | static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev, |
550 | struct bio *bio) | |
f507cd22 | 551 | { |
03fa68c2 | 552 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
553 | int write = bio_data_dir(bio) == WRITE; |
554 | const char *op = write ? "write" : "read"; | |
555 | loff_t offset = bio->bi_sector << 9; | |
556 | int error = 0; | |
557 | struct bio_vec *bvec; | |
558 | unsigned int i; | |
fb89e89d | 559 | struct bio *next; |
f507cd22 GU |
560 | |
561 | bio_for_each_segment(bvec, bio, i) { | |
562 | /* PS3 is ppc64, so we don't handle highmem */ | |
563 | char *ptr = page_address(bvec->bv_page) + bvec->bv_offset; | |
564 | size_t len = bvec->bv_len, retlen; | |
565 | ||
566 | dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op, | |
567 | len, offset); | |
568 | if (write) | |
569 | error = ps3vram_write(dev, offset, len, &retlen, ptr); | |
570 | else | |
571 | error = ps3vram_read(dev, offset, len, &retlen, ptr); | |
572 | ||
573 | if (error) { | |
574 | dev_err(&dev->core, "%s failed\n", op); | |
575 | goto out; | |
576 | } | |
577 | ||
578 | if (retlen != len) { | |
579 | dev_err(&dev->core, "Short %s\n", op); | |
734957c8 | 580 | error = -EIO; |
f507cd22 GU |
581 | goto out; |
582 | } | |
583 | ||
584 | offset += len; | |
585 | } | |
586 | ||
587 | dev_dbg(&dev->core, "%s completed\n", op); | |
588 | ||
589 | out: | |
fb89e89d GU |
590 | spin_lock_irq(&priv->lock); |
591 | bio_list_pop(&priv->list); | |
592 | next = bio_list_peek(&priv->list); | |
593 | spin_unlock_irq(&priv->lock); | |
594 | ||
f507cd22 | 595 | bio_endio(bio, error); |
fb89e89d GU |
596 | return next; |
597 | } | |
598 | ||
599 | static int ps3vram_make_request(struct request_queue *q, struct bio *bio) | |
600 | { | |
601 | struct ps3_system_bus_device *dev = q->queuedata; | |
03fa68c2 | 602 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
fb89e89d GU |
603 | int busy; |
604 | ||
605 | dev_dbg(&dev->core, "%s\n", __func__); | |
606 | ||
607 | spin_lock_irq(&priv->lock); | |
608 | busy = !bio_list_empty(&priv->list); | |
609 | bio_list_add(&priv->list, bio); | |
610 | spin_unlock_irq(&priv->lock); | |
611 | ||
612 | if (busy) | |
613 | return 0; | |
614 | ||
615 | do { | |
616 | bio = ps3vram_do_bio(dev, bio); | |
617 | } while (bio); | |
618 | ||
f507cd22 GU |
619 | return 0; |
620 | } | |
621 | ||
622 | static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev) | |
623 | { | |
624 | struct ps3vram_priv *priv; | |
625 | int error, status; | |
626 | struct request_queue *queue; | |
627 | struct gendisk *gendisk; | |
56ac72db GU |
628 | u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar, |
629 | reports_size, xdr_lpar; | |
f507cd22 GU |
630 | char *rest; |
631 | ||
632 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
633 | if (!priv) { | |
634 | error = -ENOMEM; | |
635 | goto fail; | |
636 | } | |
637 | ||
fb89e89d GU |
638 | spin_lock_init(&priv->lock); |
639 | bio_list_init(&priv->list); | |
03fa68c2 | 640 | ps3_system_bus_set_drvdata(dev, priv); |
f507cd22 GU |
641 | |
642 | /* Allocate XDR buffer (1MiB aligned) */ | |
643 | priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL, | |
644 | get_order(XDR_BUF_SIZE)); | |
645 | if (priv->xdr_buf == NULL) { | |
646 | dev_err(&dev->core, "Could not allocate XDR buffer\n"); | |
647 | error = -ENOMEM; | |
648 | goto fail_free_priv; | |
649 | } | |
650 | ||
651 | /* Put FIFO at begginning of XDR buffer */ | |
652 | priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET); | |
653 | priv->fifo_ptr = priv->fifo_base; | |
654 | ||
655 | /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */ | |
656 | if (ps3_open_hv_device(dev)) { | |
657 | dev_err(&dev->core, "ps3_open_hv_device failed\n"); | |
658 | error = -EAGAIN; | |
3273d877 | 659 | goto out_free_xdr_buf; |
f507cd22 GU |
660 | } |
661 | ||
662 | /* Request memory */ | |
663 | status = -1; | |
664 | ddr_size = ALIGN(memparse(size, &rest), 1024*1024); | |
665 | if (!ddr_size) { | |
666 | dev_err(&dev->core, "Specified size is too small\n"); | |
667 | error = -EINVAL; | |
668 | goto out_close_gpu; | |
669 | } | |
670 | ||
671 | while (ddr_size > 0) { | |
672 | status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0, | |
673 | &priv->memory_handle, | |
674 | &ddr_lpar); | |
675 | if (!status) | |
676 | break; | |
677 | ddr_size -= 1024*1024; | |
678 | } | |
679 | if (status) { | |
680 | dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n", | |
681 | status); | |
682 | error = -ENOMEM; | |
3273d877 | 683 | goto out_close_gpu; |
f507cd22 GU |
684 | } |
685 | ||
686 | /* Request context */ | |
687 | status = lv1_gpu_context_allocate(priv->memory_handle, 0, | |
688 | &priv->context_handle, &ctrl_lpar, | |
689 | &info_lpar, &reports_lpar, | |
690 | &reports_size); | |
691 | if (status) { | |
692 | dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n", | |
693 | status); | |
694 | error = -ENOMEM; | |
695 | goto out_free_memory; | |
696 | } | |
697 | ||
698 | /* Map XDR buffer to RSX */ | |
56ac72db | 699 | xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)); |
f507cd22 | 700 | status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
56ac72db GU |
701 | xdr_lpar, XDR_BUF_SIZE, |
702 | CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | | |
703 | CBE_IOPTE_M); | |
f507cd22 GU |
704 | if (status) { |
705 | dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n", | |
706 | status); | |
707 | error = -ENOMEM; | |
708 | goto out_free_context; | |
709 | } | |
710 | ||
f507cd22 GU |
711 | priv->ctrl = ioremap(ctrl_lpar, 64 * 1024); |
712 | if (!priv->ctrl) { | |
713 | dev_err(&dev->core, "ioremap CTRL failed\n"); | |
714 | error = -ENOMEM; | |
c3b94fd8 | 715 | goto out_unmap_context; |
f507cd22 GU |
716 | } |
717 | ||
718 | priv->reports = ioremap(reports_lpar, reports_size); | |
719 | if (!priv->reports) { | |
720 | dev_err(&dev->core, "ioremap REPORTS failed\n"); | |
721 | error = -ENOMEM; | |
722 | goto out_unmap_ctrl; | |
723 | } | |
724 | ||
725 | mutex_lock(&ps3_gpu_mutex); | |
726 | ps3vram_init_ring(dev); | |
727 | mutex_unlock(&ps3_gpu_mutex); | |
728 | ||
729 | priv->size = ddr_size; | |
730 | ||
731 | ps3vram_bind(dev); | |
732 | ||
733 | mutex_lock(&ps3_gpu_mutex); | |
734 | error = ps3vram_wait_ring(dev, 100); | |
735 | mutex_unlock(&ps3_gpu_mutex); | |
736 | if (error < 0) { | |
737 | dev_err(&dev->core, "Failed to initialize channels\n"); | |
738 | error = -ETIMEDOUT; | |
739 | goto out_unmap_reports; | |
740 | } | |
741 | ||
742 | ps3vram_cache_init(dev); | |
743 | ps3vram_proc_init(dev); | |
744 | ||
745 | queue = blk_alloc_queue(GFP_KERNEL); | |
746 | if (!queue) { | |
747 | dev_err(&dev->core, "blk_alloc_queue failed\n"); | |
748 | error = -ENOMEM; | |
749 | goto out_cache_cleanup; | |
750 | } | |
751 | ||
752 | priv->queue = queue; | |
753 | queue->queuedata = dev; | |
754 | blk_queue_make_request(queue, ps3vram_make_request); | |
91f63d0e | 755 | blk_queue_max_segments(queue, BLK_MAX_SEGMENTS); |
eb28d31b | 756 | blk_queue_max_segment_size(queue, BLK_MAX_SEGMENT_SIZE); |
086fa5ff | 757 | blk_queue_max_hw_sectors(queue, BLK_SAFE_MAX_SECTORS); |
f507cd22 GU |
758 | |
759 | gendisk = alloc_disk(1); | |
760 | if (!gendisk) { | |
761 | dev_err(&dev->core, "alloc_disk failed\n"); | |
762 | error = -ENOMEM; | |
763 | goto fail_cleanup_queue; | |
764 | } | |
765 | ||
766 | priv->gendisk = gendisk; | |
767 | gendisk->major = ps3vram_major; | |
768 | gendisk->first_minor = 0; | |
769 | gendisk->fops = &ps3vram_fops; | |
770 | gendisk->queue = queue; | |
771 | gendisk->private_data = dev; | |
772 | gendisk->driverfs_dev = &dev->core; | |
773 | strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name)); | |
774 | set_capacity(gendisk, priv->size >> 9); | |
775 | ||
776 | dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n", | |
777 | gendisk->disk_name, get_capacity(gendisk) >> 11); | |
778 | ||
779 | add_disk(gendisk); | |
780 | return 0; | |
781 | ||
782 | fail_cleanup_queue: | |
783 | blk_cleanup_queue(queue); | |
784 | out_cache_cleanup: | |
785 | remove_proc_entry(DEVICE_NAME, NULL); | |
786 | ps3vram_cache_cleanup(dev); | |
787 | out_unmap_reports: | |
788 | iounmap(priv->reports); | |
789 | out_unmap_ctrl: | |
790 | iounmap(priv->ctrl); | |
56ac72db GU |
791 | out_unmap_context: |
792 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar, | |
793 | XDR_BUF_SIZE, CBE_IOPTE_M); | |
f507cd22 GU |
794 | out_free_context: |
795 | lv1_gpu_context_free(priv->context_handle); | |
796 | out_free_memory: | |
797 | lv1_gpu_memory_free(priv->memory_handle); | |
798 | out_close_gpu: | |
799 | ps3_close_hv_device(dev); | |
800 | out_free_xdr_buf: | |
801 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | |
802 | fail_free_priv: | |
803 | kfree(priv); | |
03fa68c2 | 804 | ps3_system_bus_set_drvdata(dev, NULL); |
f507cd22 GU |
805 | fail: |
806 | return error; | |
807 | } | |
808 | ||
809 | static int ps3vram_remove(struct ps3_system_bus_device *dev) | |
810 | { | |
03fa68c2 | 811 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
812 | |
813 | del_gendisk(priv->gendisk); | |
814 | put_disk(priv->gendisk); | |
815 | blk_cleanup_queue(priv->queue); | |
816 | remove_proc_entry(DEVICE_NAME, NULL); | |
817 | ps3vram_cache_cleanup(dev); | |
818 | iounmap(priv->reports); | |
819 | iounmap(priv->ctrl); | |
56ac72db GU |
820 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
821 | ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)), | |
822 | XDR_BUF_SIZE, CBE_IOPTE_M); | |
f507cd22 GU |
823 | lv1_gpu_context_free(priv->context_handle); |
824 | lv1_gpu_memory_free(priv->memory_handle); | |
825 | ps3_close_hv_device(dev); | |
826 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | |
827 | kfree(priv); | |
03fa68c2 | 828 | ps3_system_bus_set_drvdata(dev, NULL); |
f507cd22 GU |
829 | return 0; |
830 | } | |
831 | ||
832 | static struct ps3_system_bus_driver ps3vram = { | |
833 | .match_id = PS3_MATCH_ID_GPU, | |
834 | .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK, | |
835 | .core.name = DEVICE_NAME, | |
836 | .core.owner = THIS_MODULE, | |
837 | .probe = ps3vram_probe, | |
838 | .remove = ps3vram_remove, | |
839 | .shutdown = ps3vram_remove, | |
840 | }; | |
841 | ||
842 | ||
843 | static int __init ps3vram_init(void) | |
844 | { | |
845 | int error; | |
846 | ||
847 | if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
848 | return -ENODEV; | |
849 | ||
850 | error = register_blkdev(0, DEVICE_NAME); | |
851 | if (error <= 0) { | |
852 | pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error); | |
853 | return error; | |
854 | } | |
855 | ps3vram_major = error; | |
856 | ||
857 | pr_info("%s: registered block device major %d\n", DEVICE_NAME, | |
858 | ps3vram_major); | |
859 | ||
860 | error = ps3_system_bus_driver_register(&ps3vram); | |
861 | if (error) | |
862 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | |
863 | ||
864 | return error; | |
865 | } | |
866 | ||
867 | static void __exit ps3vram_exit(void) | |
868 | { | |
869 | ps3_system_bus_driver_unregister(&ps3vram); | |
870 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | |
871 | } | |
872 | ||
873 | module_init(ps3vram_init); | |
874 | module_exit(ps3vram_exit); | |
875 | ||
876 | MODULE_LICENSE("GPL"); | |
877 | MODULE_DESCRIPTION("PS3 Video RAM Storage Driver"); | |
878 | MODULE_AUTHOR("Sony Corporation"); | |
879 | MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK); |