[linux.git] / arch / arm / mach-pxa / time.c

/*
 * arch/arm/mach-pxa/time.c
 *
 * PXA clocksource, clockevents, and OST interrupt handlers.
 * Copyright (c) 2007 by Bill Gatliff <[email protected]>.
 *
 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
 * by MontaVista Software, Inc.  (Nico, your code rocks!)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/sched.h>

#include <asm/div64.h>
#include <asm/cnt32_to_63.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>

/*
 * This is PXA's sched_clock implementation. This has a resolution
 * of at least 308 ns and a maximum value of 208 days.
 *
 * The return value is guaranteed to be monotonic in that range as
 * long as there is always less than 582 seconds between successive
 * calls to sched_clock() which should always be the case in practice.
 */

#define OSCR2NS_SCALE_FACTOR 10

static unsigned long oscr2ns_scale;

static void __init set_oscr2ns_scale(unsigned long oscr_rate)
{
	unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
	do_div(v, oscr_rate);
	oscr2ns_scale = v;
	/*
	 * We want an even value to automatically clear the top bit
	 * returned by cnt32_to_63() without an additional run time
	 * instruction. So if the LSB is 1 then round it up.
	 */
	if (oscr2ns_scale & 1)
		oscr2ns_scale++;
}

unsigned long long sched_clock(void)
{
	unsigned long long v = cnt32_to_63(OSCR);
	return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
}


static irqreturn_t
pxa_ost0_interrupt(int irq, void *dev_id)
{
	int next_match;
	struct clock_event_device *c = dev_id;

	if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
		/* Disarm the compare/match, signal the event. */
		OIER &= ~OIER_E0;
		c->event_handler(c);
	} else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
		/* Call the event handler as many times as necessary
		 * to recover missed events, if any (if we update
		 * OSMR0 and OSCR0 is still ahead of us, we've missed
		 * the event).  As we're dealing with that, re-arm the
		 * compare/match for the next event.
		 *
		 * HACK ALERT:
		 *
		 * There's a latency between the instruction that
		 * writes to OSMR0 and the actual commit to the
		 * physical hardware, because the CPU doesn't (have
		 * to) run at bus speed, there's a write buffer
		 * between the CPU and the bus, etc. etc.  So if the
		 * target OSCR0 is "very close", to the OSMR0 load
		 * value, the update to OSMR0 might not get to the
		 * hardware in time and we'll miss that interrupt.
		 *
		 * To be safe, if the new OSMR0 is "very close" to the
		 * target OSCR0 value, we call the event_handler as
		 * though the event actually happened.  According to
		 * Nico's comment in the previous version of this
		 * code, experience has shown that 6 OSCR ticks is
		 * "very close" but he went with 8.  We will use 16,
		 * based on the results of testing on PXA270.
		 *
		 * To be doubly sure, we also tell clkevt via
		 * clockevents_register_device() not to ask for
		 * anything that might put us "very close".
	 */
#define MIN_OSCR_DELTA 16
	do {
			OSSR = OSSR_M0;
		next_match = (OSMR0 += LATCH);
			c->event_handler(c);
		} while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
			 && (c->mode == CLOCK_EVT_MODE_PERIODIC));
	}

	return IRQ_HANDLED;
}

static int
pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
{
	unsigned long irqflags;

	raw_local_irq_save(irqflags);
	OSMR0 = OSCR + delta;
	OSSR = OSSR_M0;
	OIER |= OIER_E0;
	raw_local_irq_restore(irqflags);
	return 0;
}

static void
pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
	unsigned long irqflags;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		raw_local_irq_save(irqflags);
		OSMR0 = OSCR + LATCH;
		OSSR = OSSR_M0;
		OIER |= OIER_E0;
		raw_local_irq_restore(irqflags);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		raw_local_irq_save(irqflags);
		OIER &= ~OIER_E0;
		raw_local_irq_restore(irqflags);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		/* initializing, released, or preparing for suspend */
		raw_local_irq_save(irqflags);
		OIER &= ~OIER_E0;
		raw_local_irq_restore(irqflags);
		break;

	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device ckevt_pxa_osmr0 = {
	.name		= "osmr0",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.rating		= 200,
	.cpumask	= CPU_MASK_CPU0,
	.set_next_event	= pxa_osmr0_set_next_event,
	.set_mode	= pxa_osmr0_set_mode,
};

static cycle_t pxa_read_oscr(void)
{
	return OSCR;
}

static struct clocksource cksrc_pxa_oscr0 = {
	.name           = "oscr0",
	.rating         = 200,
	.read           = pxa_read_oscr,
	.mask           = CLOCKSOURCE_MASK(32),
	.shift          = 20,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct irqaction pxa_ost0_irq = {
	.name		= "ost0",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= pxa_ost0_interrupt,
	.dev_id		= &ckevt_pxa_osmr0,
};

static void __init pxa_timer_init(void)
{
	unsigned long clock_tick_rate;

	OIER = 0;
	OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;

	if (cpu_is_pxa21x() || cpu_is_pxa25x())
		clock_tick_rate = 3686400;
	else if (machine_is_mainstone())
		clock_tick_rate = 3249600;
	else
		clock_tick_rate = 3250000;

	set_oscr2ns_scale(clock_tick_rate);

	ckevt_pxa_osmr0.mult =
		div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
	ckevt_pxa_osmr0.max_delta_ns =
		clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
	ckevt_pxa_osmr0.min_delta_ns =
		clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;

	cksrc_pxa_oscr0.mult =
		clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);

	setup_irq(IRQ_OST0, &pxa_ost0_irq);

	clocksource_register(&cksrc_pxa_oscr0);
	clockevents_register_device(&ckevt_pxa_osmr0);
}

#ifdef CONFIG_PM
static unsigned long osmr[4], oier;

static void pxa_timer_suspend(void)
{
	osmr[0] = OSMR0;
	osmr[1] = OSMR1;
	osmr[2] = OSMR2;
	osmr[3] = OSMR3;
	oier = OIER;
}

static void pxa_timer_resume(void)
{
	OSMR0 = osmr[0];
	OSMR1 = osmr[1];
	OSMR2 = osmr[2];
	OSMR3 = osmr[3];
	OIER = oier;

	/*
	 * OSCR0 is the system timer, which has to increase
	 * monotonically until it rolls over in hardware.  The value
	 * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
	 * which is a handy value to restore to OSCR0.
	 */
	OSCR = OSMR0 - LATCH;
}
#else
#define pxa_timer_suspend NULL
#define pxa_timer_resume NULL
#endif

struct sys_timer pxa_timer = {
	.init		= pxa_timer_init,
	.suspend	= pxa_timer_suspend,
	.resume		= pxa_timer_resume,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-pxa/time.c
	3	*
7bbb18c9 BG	4	* PXA clocksource, clockevents, and OST interrupt handlers.
	5	* Copyright (c) 2007 by Bill Gatliff <[email protected]>.
	6	*
	7	* Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
	8	* by MontaVista Software, Inc. (Nico, your code rocks!)
1da177e4 LT	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
1da177e4 LT	15	#include <linux/kernel.h>
1da177e4 LT	16	#include <linux/init.h>
1da177e4	17	#include <linux/interrupt.h>
7bbb18c9	18	#include <linux/clockchips.h>
6c3a1583	19	#include <linux/sched.h>
7bbb18c9	20
6c3a1583 NP	21	#include <asm/div64.h>
6c3a1583 NP	22	#include <asm/cnt32_to_63.h>
1da177e4 LT	23	#include <asm/mach/irq.h>
	24	#include <asm/mach/time.h>
	25	#include <asm/arch/pxa-regs.h>
08197f6e	26	#include <asm/mach-types.h>
1da177e4	27
6c3a1583 NP	28	/*
	29	* This is PXA's sched_clock implementation. This has a resolution
	30	* of at least 308 ns and a maximum value of 208 days.
	31	*
	32	* The return value is guaranteed to be monotonic in that range as
	33	* long as there is always less than 582 seconds between successive
	34	* calls to sched_clock() which should always be the case in practice.
	35	*/
	36
	37	#define OSCR2NS_SCALE_FACTOR 10
	38
	39	static unsigned long oscr2ns_scale;
	40
	41	static void __init set_oscr2ns_scale(unsigned long oscr_rate)
	42	{
	43	unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
	44	do_div(v, oscr_rate);
	45	oscr2ns_scale = v;
	46	/*
	47	* We want an even value to automatically clear the top bit
	48	* returned by cnt32_to_63() without an additional run time
	49	* instruction. So if the LSB is 1 then round it up.
	50	*/
	51	if (oscr2ns_scale & 1)
	52	oscr2ns_scale++;
	53	}
	54
	55	unsigned long long sched_clock(void)
	56	{
	57	unsigned long long v = cnt32_to_63(OSCR);
	58	return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
	59	}
	60
	61
1da177e4	62	static irqreturn_t
7bbb18c9	63	pxa_ost0_interrupt(int irq, void *dev_id)
1da177e4 LT	64	{
1da177e4 LT	65	int next_match;
7bbb18c9 BG	66	struct clock_event_device *c = dev_id;
	67
	68	if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
	69	/* Disarm the compare/match, signal the event. */
	70	OIER &= ~OIER_E0;
	71	c->event_handler(c);
	72	} else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
	73	/* Call the event handler as many times as necessary
	74	* to recover missed events, if any (if we update
	75	* OSMR0 and OSCR0 is still ahead of us, we've missed
	76	* the event). As we're dealing with that, re-arm the
	77	* compare/match for the next event.
	78	*
	79	* HACK ALERT:
	80	*
	81	* There's a latency between the instruction that
	82	* writes to OSMR0 and the actual commit to the
	83	* physical hardware, because the CPU doesn't (have
	84	* to) run at bus speed, there's a write buffer
	85	* between the CPU and the bus, etc. etc. So if the
	86	* target OSCR0 is "very close", to the OSMR0 load
	87	* value, the update to OSMR0 might not get to the
	88	* hardware in time and we'll miss that interrupt.
	89	*
	90	* To be safe, if the new OSMR0 is "very close" to the
	91	* target OSCR0 value, we call the event_handler as
	92	* though the event actually happened. According to
	93	* Nico's comment in the previous version of this
	94	* code, experience has shown that 6 OSCR ticks is
	95	* "very close" but he went with 8. We will use 16,
	96	* based on the results of testing on PXA270.
	97	*
	98	* To be doubly sure, we also tell clkevt via
	99	* clockevents_register_device() not to ask for
	100	* anything that might put us "very close".
1da177e4	101	*/
7bbb18c9	102	#define MIN_OSCR_DELTA 16
1da177e4	103	do {
7bbb18c9	104	OSSR = OSSR_M0;
1da177e4	105	next_match = (OSMR0 += LATCH);
7bbb18c9 BG	106	c->event_handler(c);
	107	} while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
	108	&& (c->mode == CLOCK_EVT_MODE_PERIODIC));
	109	}
1da177e4 LT	110
	111	return IRQ_HANDLED;
	112	}
	113
7bbb18c9 BG	114	static int
	115	pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
	116	{
	117	unsigned long irqflags;
	118
	119	raw_local_irq_save(irqflags);
	120	OSMR0 = OSCR + delta;
	121	OSSR = OSSR_M0;
	122	OIER \|= OIER_E0;
	123	raw_local_irq_restore(irqflags);
	124	return 0;
	125	}
	126
	127	static void
	128	pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
	129	{
	130	unsigned long irqflags;
	131
	132	switch (mode) {
	133	case CLOCK_EVT_MODE_PERIODIC:
	134	raw_local_irq_save(irqflags);
	135	OSMR0 = OSCR + LATCH;
	136	OSSR = OSSR_M0;
	137	OIER \|= OIER_E0;
	138	raw_local_irq_restore(irqflags);
	139	break;
	140
	141	case CLOCK_EVT_MODE_ONESHOT:
	142	raw_local_irq_save(irqflags);
	143	OIER &= ~OIER_E0;
	144	raw_local_irq_restore(irqflags);
	145	break;
	146
	147	case CLOCK_EVT_MODE_UNUSED:
	148	case CLOCK_EVT_MODE_SHUTDOWN:
	149	/* initializing, released, or preparing for suspend */
	150	raw_local_irq_save(irqflags);
	151	OIER &= ~OIER_E0;
	152	raw_local_irq_restore(irqflags);
	153	break;
df43309b RK	154
	155	case CLOCK_EVT_MODE_RESUME:
	156	break;
7bbb18c9 BG	157	}
	158	}
	159
	160	static struct clock_event_device ckevt_pxa_osmr0 = {
	161	.name = "osmr0",
	162	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	163	.shift = 32,
	164	.rating = 200,
	165	.cpumask = CPU_MASK_CPU0,
	166	.set_next_event = pxa_osmr0_set_next_event,
	167	.set_mode = pxa_osmr0_set_mode,
1da177e4 LT	168	};
1da177e4 LT	169
7bbb18c9	170	static cycle_t pxa_read_oscr(void)
c80204e5 SH	171	{
	172	return OSCR;
	173	}
	174
7bbb18c9 BG	175	static struct clocksource cksrc_pxa_oscr0 = {
7bbb18c9 BG	176	.name = "oscr0",
c80204e5	177	.rating = 200,
7bbb18c9	178	.read = pxa_read_oscr,
c80204e5 SH	179	.mask = CLOCKSOURCE_MASK(32),
c80204e5 SH	180	.shift = 20,
c66699a7	181	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
c80204e5 SH	182	};
c80204e5 SH	183
7bbb18c9 BG	184	static struct irqaction pxa_ost0_irq = {
	185	.name = "ost0",
	186	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	187	.handler = pxa_ost0_interrupt,
	188	.dev_id = &ckevt_pxa_osmr0,
	189	};
	190
1da177e4 LT	191	static void __init pxa_timer_init(void)
1da177e4 LT	192	{
08197f6e RK	193	unsigned long clock_tick_rate;
08197f6e RK	194
7bbb18c9 BG	195	OIER = 0;
7bbb18c9 BG	196	OSSR = OSSR_M0 \| OSSR_M1 \| OSSR_M2 \| OSSR_M3;
1da177e4	197
08197f6e RK	198	if (cpu_is_pxa21x() \|\| cpu_is_pxa25x())
	199	clock_tick_rate = 3686400;
	200	else if (machine_is_mainstone())
	201	clock_tick_rate = 3249600;
	202	else
	203	clock_tick_rate = 3250000;
	204
	205	set_oscr2ns_scale(clock_tick_rate);
6c3a1583	206
7bbb18c9	207	ckevt_pxa_osmr0.mult =
08197f6e	208	div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
7bbb18c9 BG	209	ckevt_pxa_osmr0.max_delta_ns =
	210	clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
	211	ckevt_pxa_osmr0.min_delta_ns =
	212	clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
1da177e4	213
7bbb18c9	214	cksrc_pxa_oscr0.mult =
08197f6e	215	clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
5c53ff08	216
7bbb18c9	217	setup_irq(IRQ_OST0, &pxa_ost0_irq);
5c53ff08	218
7bbb18c9 BG	219	clocksource_register(&cksrc_pxa_oscr0);
7bbb18c9 BG	220	clockevents_register_device(&ckevt_pxa_osmr0);
5c53ff08 NP	221	}
5c53ff08 NP	222
1da177e4 LT	223	#ifdef CONFIG_PM
	224	static unsigned long osmr[4], oier;
	225
	226	static void pxa_timer_suspend(void)
	227	{
	228	osmr[0] = OSMR0;
	229	osmr[1] = OSMR1;
	230	osmr[2] = OSMR2;
	231	osmr[3] = OSMR3;
	232	oier = OIER;
	233	}
	234
	235	static void pxa_timer_resume(void)
	236	{
	237	OSMR0 = osmr[0];
	238	OSMR1 = osmr[1];
	239	OSMR2 = osmr[2];
	240	OSMR3 = osmr[3];
	241	OIER = oier;
	242
	243	/*
7bbb18c9 BG	244	* OSCR0 is the system timer, which has to increase
	245	* monotonically until it rolls over in hardware. The value
	246	* (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
	247	* which is a handy value to restore to OSCR0.
1da177e4 LT	248	*/
	249	OSCR = OSMR0 - LATCH;
	250	}
	251	#else
	252	#define pxa_timer_suspend NULL
	253	#define pxa_timer_resume NULL
	254	#endif
	255
	256	struct sys_timer pxa_timer = {
	257	.init = pxa_timer_init,
	258	.suspend = pxa_timer_suspend,
	259	.resume = pxa_timer_resume,
1da177e4	260	};