[linux.git] / drivers / ata / ata_generic.c

/*
 *  ata_generic.c - Generic PATA/SATA controller driver.
 *  Copyright 2005 Red Hat Inc, all rights reserved.
 *
 *  Elements from ide/pci/generic.c
 *	    Copyright (C) 2001-2002	Andre Hedrick <[email protected]>
 *	    Portions (C) Copyright 2002  Red Hat Inc <[email protected]>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  Driver for PCI IDE interfaces implementing the standard bus mastering
 *  interface functionality. This assumes the BIOS did the drive set up and
 *  tuning for us. By default we do not grab all IDE class devices as they
 *  may have other drivers or need fixups to avoid problems. Instead we keep
 *  a default list of stuff without documentation/driver that appears to
 *  work.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "ata_generic"
#define DRV_VERSION "0.2.15"

/*
 *	A generic parallel ATA driver using libata
 */

enum {
	ATA_GEN_CLASS_MATCH		= (1 << 0),
	ATA_GEN_FORCE_DMA		= (1 << 1),
	ATA_GEN_INTEL_IDER		= (1 << 2),
};

/**
 *	generic_set_mode	-	mode setting
 *	@link: link to set up
 *	@unused: returned device on error
 *
 *	Use a non standard set_mode function. We don't want to be tuned.
 *	The BIOS configured everything. Our job is not to fiddle. We
 *	read the dma enabled bits from the PCI configuration of the device
 *	and respect them.
 */

static int generic_set_mode(struct ata_link *link, struct ata_device **unused)
{
	struct ata_port *ap = link->ap;
	const struct pci_device_id *id = ap->host->private_data;
	int dma_enabled = 0;
	struct ata_device *dev;

	if (id->driver_data & ATA_GEN_FORCE_DMA) {
		dma_enabled = 0xff;
	} else if (ap->ioaddr.bmdma_addr) {
		/* Bits 5 and 6 indicate if DMA is active on master/slave */
		dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
	}

	ata_for_each_dev(dev, link, ENABLED) {
		/* We don't really care */
		dev->pio_mode = XFER_PIO_0;
		dev->dma_mode = XFER_MW_DMA_0;
		/* We do need the right mode information for DMA or PIO
		   and this comes from the current configuration flags */
		if (dma_enabled & (1 << (5 + dev->devno))) {
			unsigned int xfer_mask = ata_id_xfermask(dev->id);
			const char *name;

			if (xfer_mask & (ATA_MASK_MWDMA | ATA_MASK_UDMA))
				name = ata_mode_string(xfer_mask);
			else {
				/* SWDMA perhaps? */
				name = "DMA";
				xfer_mask |= ata_xfer_mode2mask(XFER_MW_DMA_0);
			}

			ata_dev_info(dev, "configured for %s\n", name);

			dev->xfer_mode = ata_xfer_mask2mode(xfer_mask);
			dev->xfer_shift = ata_xfer_mode2shift(dev->xfer_mode);
			dev->flags &= ~ATA_DFLAG_PIO;
		} else {
			ata_dev_info(dev, "configured for PIO\n");
			dev->xfer_mode = XFER_PIO_0;
			dev->xfer_shift = ATA_SHIFT_PIO;
			dev->flags |= ATA_DFLAG_PIO;
		}
	}
	return 0;
}

static struct scsi_host_template generic_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations generic_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= ata_cable_unknown,
	.set_mode	= generic_set_mode,
};

static int all_generic_ide;		/* Set to claim all devices */

/**
 *	is_intel_ider		-	identify intel IDE-R devices
 *	@dev: PCI device
 *
 *	Distinguish Intel IDE-R controller devices from other Intel IDE
 *	devices. IDE-R devices have no timing registers and are in
 *	most respects virtual. They should be driven by the ata_generic
 *	driver.
 *
 *	IDE-R devices have PCI offset 0xF8.L as zero, later Intel ATA has
 *	it non zero. All Intel ATA has 0x40 writable (timing), but it is
 *	not writable on IDE-R devices (this is guaranteed).
 */

static int is_intel_ider(struct pci_dev *dev)
{
	/* For Intel IDE the value at 0xF8 is only zero on IDE-R
	   interfaces */
	u32 r;
	u16 t;

	/* Check the manufacturing ID, it will be zero for IDE-R */
	pci_read_config_dword(dev, 0xF8, &r);
	/* Not IDE-R: punt so that ata_(old)piix gets it */
	if (r != 0)
		return 0;
	/* 0xF8 will also be zero on some early Intel IDE devices
	   but they will have a sane timing register */
	pci_read_config_word(dev, 0x40, &t);
	if (t != 0)
		return 0;
	/* Finally check if the timing register is writable so that
	   we eliminate any early devices hot-docked in a docking
	   station */
	pci_write_config_word(dev, 0x40, 1);
	pci_read_config_word(dev, 0x40, &t);
	if (t) {
		pci_write_config_word(dev, 0x40, 0);
		return 0;
	}
	return 1;
}

/**
 *	ata_generic_init		-	attach generic IDE
 *	@dev: PCI device found
 *	@id: match entry
 *
 *	Called each time a matching IDE interface is found. We check if the
 *	interface is one we wish to claim and if so we perform any chip
 *	specific hacks then let the ATA layer do the heavy lifting.
 */

static int ata_generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	u16 command;
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA5,
		.port_ops = &generic_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };

	/* Don't use the generic entry unless instructed to do so */
	if ((id->driver_data & ATA_GEN_CLASS_MATCH) && all_generic_ide == 0)
		return -ENODEV;

	if ((id->driver_data & ATA_GEN_INTEL_IDER) && !all_generic_ide)
		if (!is_intel_ider(dev))
			return -ENODEV;

	/* Devices that need care */
	if (dev->vendor == PCI_VENDOR_ID_UMC &&
	    dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
	    (!(PCI_FUNC(dev->devfn) & 1)))
		return -ENODEV;

	if (dev->vendor == PCI_VENDOR_ID_OPTI &&
	    dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
	    (!(PCI_FUNC(dev->devfn) & 1)))
		return -ENODEV;

	/* Don't re-enable devices in generic mode or we will break some
	   motherboards with disabled and unused IDE controllers */
	pci_read_config_word(dev, PCI_COMMAND, &command);
	if (!(command & PCI_COMMAND_IO))
		return -ENODEV;

	if (dev->vendor == PCI_VENDOR_ID_AL)
		ata_pci_bmdma_clear_simplex(dev);

	if (dev->vendor == PCI_VENDOR_ID_ATI) {
		int rc = pcim_enable_device(dev);
		if (rc < 0)
			return rc;
		pcim_pin_device(dev);
	}
	return ata_pci_bmdma_init_one(dev, ppi, &generic_sht, (void *)id, 0);
}

static struct pci_device_id ata_generic[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
	{ PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8673F), },
	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8886A), },
	{ PCI_DEVICE(PCI_VENDOR_ID_UMC,    PCI_DEVICE_ID_UMC_UM8886BF), },
	{ PCI_DEVICE(PCI_VENDOR_ID_HINT,   PCI_DEVICE_ID_HINT_VXPROII_IDE), },
	{ PCI_DEVICE(PCI_VENDOR_ID_VIA,    PCI_DEVICE_ID_VIA_82C561), },
	{ PCI_DEVICE(PCI_VENDOR_ID_OPTI,   PCI_DEVICE_ID_OPTI_82C558), },
	{ PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE),
	  .driver_data = ATA_GEN_FORCE_DMA },
#if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE)
	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2),  },
	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_3),  },
	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_5),  },
#endif
	/* Intel, IDE class device */
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL,
	  .driver_data = ATA_GEN_INTEL_IDER },
	/* Must come last. If you add entries adjust this table appropriately */
	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL),
	  .driver_data = ATA_GEN_CLASS_MATCH },
	{ 0, },
};

static struct pci_driver ata_generic_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= ata_generic,
	.probe 		= ata_generic_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

module_pci_driver(ata_generic_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for generic ATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, ata_generic);
MODULE_VERSION(DRV_VERSION);

module_param(all_generic_ide, int, 0);
Commit	Line	Data
669a5db4 JG	1	/*
669a5db4 JG	2	* ata_generic.c - Generic PATA/SATA controller driver.
ab771630	3	* Copyright 2005 Red Hat Inc, all rights reserved.
669a5db4	4	*
85cd7251	5	* Elements from ide/pci/generic.c
669a5db4 JG	6	* Copyright (C) 2001-2002 Andre Hedrick <[email protected]>
	7	* Portions (C) Copyright 2002 Red Hat Inc <[email protected]>
	8	*
	9	* May be copied or modified under the terms of the GNU General Public License
85cd7251	10	*
669a5db4 JG	11	* Driver for PCI IDE interfaces implementing the standard bus mastering
	12	* interface functionality. This assumes the BIOS did the drive set up and
	13	* tuning for us. By default we do not grab all IDE class devices as they
	14	* may have other drivers or need fixups to avoid problems. Instead we keep
	15	* a default list of stuff without documentation/driver that appears to
85cd7251	16	* work.
669a5db4 JG	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
669a5db4 JG	22	#include <linux/blkdev.h>
	23	#include <linux/delay.h>
	24	#include <scsi/scsi_host.h>
	25	#include <linux/libata.h>
	26
	27	#define DRV_NAME "ata_generic"
5e8f757c	28	#define DRV_VERSION "0.2.15"
669a5db4 JG	29
	30	/*
	31	* A generic parallel ATA driver using libata
	32	*/
	33
1529c69a TH	34	enum {
	35	ATA_GEN_CLASS_MATCH = (1 << 0),
	36	ATA_GEN_FORCE_DMA = (1 << 1),
60039a52	37	ATA_GEN_INTEL_IDER = (1 << 2),
1529c69a TH	38	};
1529c69a TH	39
669a5db4 JG	40	/**
669a5db4 JG	41	* generic_set_mode - mode setting
0260731f	42	* @link: link to set up
b229a7b0	43	* @unused: returned device on error
669a5db4 JG	44	*
	45	* Use a non standard set_mode function. We don't want to be tuned.
	46	* The BIOS configured everything. Our job is not to fiddle. We
	47	* read the dma enabled bits from the PCI configuration of the device
85cd7251	48	* and respect them.
669a5db4	49	*/
85cd7251	50
0260731f	51	static int generic_set_mode(struct ata_link link, struct ata_device *unused)
669a5db4	52	{
0260731f	53	struct ata_port *ap = link->ap;
1529c69a	54	const struct pci_device_id *id = ap->host->private_data;
669a5db4	55	int dma_enabled = 0;
f58229f8	56	struct ata_device *dev;
669a5db4	57
1529c69a TH	58	if (id->driver_data & ATA_GEN_FORCE_DMA) {
	59	dma_enabled = 0xff;
	60	} else if (ap->ioaddr.bmdma_addr) {
	61	/* Bits 5 and 6 indicate if DMA is active on master/slave */
d6f4d5ea	62	dma_enabled = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1529c69a	63	}
85cd7251	64
1eca4365	65	ata_for_each_dev(dev, link, ENABLED) {
f8ab6d8e TH	66	/* We don't really care */
	67	dev->pio_mode = XFER_PIO_0;
	68	dev->dma_mode = XFER_MW_DMA_0;
	69	/* We do need the right mode information for DMA or PIO
	70	and this comes from the current configuration flags */
	71	if (dma_enabled & (1 << (5 + dev->devno))) {
9d3501ab TH	72	unsigned int xfer_mask = ata_id_xfermask(dev->id);
	73	const char *name;
	74
	75	if (xfer_mask & (ATA_MASK_MWDMA \| ATA_MASK_UDMA))
	76	name = ata_mode_string(xfer_mask);
	77	else {
	78	/* SWDMA perhaps? */
	79	name = "DMA";
	80	xfer_mask \|= ata_xfer_mode2mask(XFER_MW_DMA_0);
	81	}
	82
a9a79dfe	83	ata_dev_info(dev, "configured for %s\n", name);
9d3501ab TH	84
	85	dev->xfer_mode = ata_xfer_mask2mode(xfer_mask);
	86	dev->xfer_shift = ata_xfer_mode2shift(dev->xfer_mode);
f8ab6d8e TH	87	dev->flags &= ~ATA_DFLAG_PIO;
f8ab6d8e TH	88	} else {
a9a79dfe	89	ata_dev_info(dev, "configured for PIO\n");
f8ab6d8e TH	90	dev->xfer_mode = XFER_PIO_0;
	91	dev->xfer_shift = ATA_SHIFT_PIO;
	92	dev->flags \|= ATA_DFLAG_PIO;
669a5db4 JG	93	}
669a5db4 JG	94	}
b229a7b0	95	return 0;
669a5db4 JG	96	}
	97
	98	static struct scsi_host_template generic_sht = {
68d1d07b	99	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	100	};
	101
	102	static struct ata_port_operations generic_port_ops = {
029cfd6b	103	.inherits = &ata_bmdma_port_ops,
eb4a2c7f	104	.cable_detect = ata_cable_unknown,
029cfd6b	105	.set_mode = generic_set_mode,
85cd7251 JG	106	};
85cd7251 JG	107
669a5db4 JG	108	static int all_generic_ide; /* Set to claim all devices */
669a5db4 JG	109
60039a52 AC	110	/**
	111	* is_intel_ider - identify intel IDE-R devices
	112	* @dev: PCI device
	113	*
	114	* Distinguish Intel IDE-R controller devices from other Intel IDE
	115	* devices. IDE-R devices have no timing registers and are in
	116	* most respects virtual. They should be driven by the ata_generic
	117	* driver.
	118	*
	119	* IDE-R devices have PCI offset 0xF8.L as zero, later Intel ATA has
	120	* it non zero. All Intel ATA has 0x40 writable (timing), but it is
	121	* not writable on IDE-R devices (this is guaranteed).
	122	*/
	123
	124	static int is_intel_ider(struct pci_dev *dev)
	125	{
	126	/* For Intel IDE the value at 0xF8 is only zero on IDE-R
	127	interfaces */
	128	u32 r;
	129	u16 t;
	130
	131	/* Check the manufacturing ID, it will be zero for IDE-R */
	132	pci_read_config_dword(dev, 0xF8, &r);
	133	/* Not IDE-R: punt so that ata_(old)piix gets it */
	134	if (r != 0)
	135	return 0;
	136	/* 0xF8 will also be zero on some early Intel IDE devices
	137	but they will have a sane timing register */
	138	pci_read_config_word(dev, 0x40, &t);
	139	if (t != 0)
	140	return 0;
	141	/* Finally check if the timing register is writable so that
	142	we eliminate any early devices hot-docked in a docking
	143	station */
	144	pci_write_config_word(dev, 0x40, 1);
	145	pci_read_config_word(dev, 0x40, &t);
	146	if (t) {
	147	pci_write_config_word(dev, 0x40, 0);
	148	return 0;
	149	}
	150	return 1;
	151	}
	152
669a5db4 JG	153	/**
	154	* ata_generic_init - attach generic IDE
	155	* @dev: PCI device found
	156	* @id: match entry
	157	*
	158	* Called each time a matching IDE interface is found. We check if the
85cd7251	159	* interface is one we wish to claim and if so we perform any chip
669a5db4 JG	160	* specific hacks then let the ATA layer do the heavy lifting.
669a5db4 JG	161	*/
85cd7251	162
669a5db4 JG	163	static int ata_generic_init_one(struct pci_dev dev, const struct pci_device_id id)
	164	{
	165	u16 command;
1626aeb8	166	static const struct ata_port_info info = {
1d2808fd	167	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	168	.pio_mask = ATA_PIO4,
14bdef98 EIB	169	.mwdma_mask = ATA_MWDMA2,
bf6263a8	170	.udma_mask = ATA_UDMA5,
669a5db4 JG	171	.port_ops = &generic_port_ops
669a5db4 JG	172	};
1626aeb8	173	const struct ata_port_info *ppi[] = { &info, NULL };
85cd7251	174
669a5db4	175	/* Don't use the generic entry unless instructed to do so */
1529c69a	176	if ((id->driver_data & ATA_GEN_CLASS_MATCH) && all_generic_ide == 0)
669a5db4 JG	177	return -ENODEV;
669a5db4 JG	178
47ee9108	179	if ((id->driver_data & ATA_GEN_INTEL_IDER) && !all_generic_ide)
60039a52 AC	180	if (!is_intel_ider(dev))
	181	return -ENODEV;
	182
669a5db4 JG	183	/* Devices that need care */
	184	if (dev->vendor == PCI_VENDOR_ID_UMC &&
	185	dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
	186	(!(PCI_FUNC(dev->devfn) & 1)))
	187	return -ENODEV;
	188
	189	if (dev->vendor == PCI_VENDOR_ID_OPTI &&
	190	dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
	191	(!(PCI_FUNC(dev->devfn) & 1)))
	192	return -ENODEV;
	193
	194	/* Don't re-enable devices in generic mode or we will break some
	195	motherboards with disabled and unused IDE controllers */
	196	pci_read_config_word(dev, PCI_COMMAND, &command);
	197	if (!(command & PCI_COMMAND_IO))
	198	return -ENODEV;
85cd7251	199
669a5db4	200	if (dev->vendor == PCI_VENDOR_ID_AL)
9363c382	201	ata_pci_bmdma_clear_simplex(dev);
669a5db4	202
05177f17 AC	203	if (dev->vendor == PCI_VENDOR_ID_ATI) {
	204	int rc = pcim_enable_device(dev);
	205	if (rc < 0)
	206	return rc;
	207	pcim_pin_device(dev);
	208	}
1529c69a	209	return ata_pci_bmdma_init_one(dev, ppi, &generic_sht, (void *)id, 0);
669a5db4 JG	210	}
	211
	212	static struct pci_device_id ata_generic[] = {
	213	{ PCI_DEVICE(PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), },
	214	{ PCI_DEVICE(PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), },
85cd7251	215	{ PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F), },
669a5db4 JG	216	{ PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A), },
	217	{ PCI_DEVICE(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF), },
	218	{ PCI_DEVICE(PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), },
	219	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561), },
	220	{ PCI_DEVICE(PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558), },
1529c69a TH	221	{ PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE),
1529c69a TH	222	.driver_data = ATA_GEN_FORCE_DMA },
8e182a90	223	#if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE)
669a5db4 JG	224	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
669a5db4 JG	225	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), },
8e182a90 AC	226	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_3), },
8e182a90 AC	227	{ PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_5), },
60039a52 AC	228	#endif
	229	/* Intel, IDE class device */
	230	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
4fca377f	231	PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL,
60039a52	232	.driver_data = ATA_GEN_INTEL_IDER },
669a5db4	233	/* Must come last. If you add entries adjust this table appropriately */
1529c69a TH	234	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL),
1529c69a TH	235	.driver_data = ATA_GEN_CLASS_MATCH },
669a5db4 JG	236	{ 0, },
	237	};
	238
	239	static struct pci_driver ata_generic_pci_driver = {
	240	.name = DRV_NAME,
	241	.id_table = ata_generic,
	242	.probe = ata_generic_init_one,
30ced0f0	243	.remove = ata_pci_remove_one,
58eb8cd5	244	#ifdef CONFIG_PM_SLEEP
30ced0f0 AC	245	.suspend = ata_pci_device_suspend,
30ced0f0 AC	246	.resume = ata_pci_device_resume,
438ac6d5	247	#endif
669a5db4 JG	248	};
669a5db4 JG	249
2fc75da0	250	module_pci_driver(ata_generic_pci_driver);
669a5db4 JG	251
	252	MODULE_AUTHOR("Alan Cox");
	253	MODULE_DESCRIPTION("low-level driver for generic ATA");
	254	MODULE_LICENSE("GPL");
	255	MODULE_DEVICE_TABLE(pci, ata_generic);
	256	MODULE_VERSION(DRV_VERSION);
	257
669a5db4	258	module_param(all_generic_ide, int, 0);