projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | #ifndef _I8042_H |
| 2 | #define _I8042_H | |
| 3 | ||
| 1da177e4 LT |
4 | |
| 5 | /* | |
| 6 | * Copyright (c) 1999-2002 Vojtech Pavlik | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify it | |
| 9 | * under the terms of the GNU General Public License version 2 as published by | |
| 10 | * the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | /* | |
| 14 | * Arch-dependent inline functions and defines. | |
| 15 | */ | |
| 16 | ||
| 17 | #if defined(CONFIG_MACH_JAZZ) | |
| 18 | #include "i8042-jazzio.h" | |
| f47831fa | 19 | #elif defined(CONFIG_SGI_HAS_I8042) |
| 1da177e4 | 20 | #include "i8042-ip22io.h" |
| f1782447 TB |
21 | #elif defined(CONFIG_SNI_RM) |
| 22 | #include "i8042-snirm.h" | |
| 1da177e4 LT |
23 | #elif defined(CONFIG_PPC) |
| 24 | #include "i8042-ppcio.h" | |
| 0b57ee9e | 25 | #elif defined(CONFIG_SPARC) |
| 1da177e4 LT |
26 | #include "i8042-sparcio.h" |
| 27 | #elif defined(CONFIG_X86) || defined(CONFIG_IA64) | |
| 28 | #include "i8042-x86ia64io.h" | |
| 425ad52b G |
29 | #elif defined(CONFIG_UNICORE32) |
| 30 | #include "i8042-unicore32io.h" | |
| 1da177e4 LT |
31 | #else |
| 32 | #include "i8042-io.h" | |
| 33 | #endif | |
| 34 | ||
| 35 | /* | |
| 36 | * This is in 50us units, the time we wait for the i8042 to react. This | |
| 37 | * has to be long enough for the i8042 itself to timeout on sending a byte | |
| 38 | * to a non-existent mouse. | |
| 39 | */ | |
| 40 | ||
| 41 | #define I8042_CTL_TIMEOUT 10000 | |
| 42 | ||
| 1da177e4 LT |
43 | /* |
| 44 | * Status register bits. | |
| 45 | */ | |
| 46 | ||
| 47 | #define I8042_STR_PARITY 0x80 | |
| 48 | #define I8042_STR_TIMEOUT 0x40 | |
| 49 | #define I8042_STR_AUXDATA 0x20 | |
| 50 | #define I8042_STR_KEYLOCK 0x10 | |
| 51 | #define I8042_STR_CMDDAT 0x08 | |
| 52 | #define I8042_STR_MUXERR 0x04 | |
| 53 | #define I8042_STR_IBF 0x02 | |
| 54 | #define I8042_STR_OBF 0x01 | |
| 55 | ||
| 56 | /* | |
| 57 | * Control register bits. | |
| 58 | */ | |
| 59 | ||
| 60 | #define I8042_CTR_KBDINT 0x01 | |
| 61 | #define I8042_CTR_AUXINT 0x02 | |
| 62 | #define I8042_CTR_IGNKEYLOCK 0x08 | |
| 63 | #define I8042_CTR_KBDDIS 0x10 | |
| 64 | #define I8042_CTR_AUXDIS 0x20 | |
| 65 | #define I8042_CTR_XLATE 0x40 | |
| 66 | ||
| 1da177e4 LT |
67 | /* |
| 68 | * Return codes. | |
| 69 | */ | |
| 70 | ||
| 71 | #define I8042_RET_CTL_TEST 0x55 | |
| 72 | ||
| 73 | /* | |
| 74 | * Expected maximum internal i8042 buffer size. This is used for flushing | |
| 75 | * the i8042 buffers. | |
| 76 | */ | |
| 77 | ||
| 78 | #define I8042_BUFFER_SIZE 16 | |
| 79 | ||
| 80 | /* | |
| 81 | * Number of AUX ports on controllers supporting active multiplexing | |
| 82 | * specification | |
| 83 | */ | |
| 84 | ||
| 85 | #define I8042_NUM_MUX_PORTS 4 | |
| 86 | ||
| 87 | /* | |
| 88 | * Debug. | |
| 89 | */ | |
| 90 | ||
| 91 | #ifdef DEBUG | |
| 92 | static unsigned long i8042_start_time; | |
| 93 | #define dbg_init() do { i8042_start_time = jiffies; } while (0) | |
| 4eb3c30b JP |
94 | #define dbg(format, arg...) \ |
| 95 | do { \ | |
| 1da177e4 | 96 | if (i8042_debug) \ |
| 4eb3c30b JP |
97 | printk(KERN_DEBUG KBUILD_MODNAME ": [%d] " format, \ |
| 98 | (int) (jiffies - i8042_start_time), ##arg); \ | |
| 1da177e4 LT |
99 | } while (0) |
| 100 | #else | |
| 101 | #define dbg_init() do { } while (0) | |
| 4eb3c30b JP |
102 | #define dbg(format, arg...) \ |
| 103 | do { \ | |
| 104 | if (0) \ | |
| 105 | printk(KERN_DEBUG pr_fmt(format), ##arg); \ | |
| 106 | } while (0) | |
| 1da177e4 LT |
107 | #endif |
| 108 | ||
| 109 | #endif /* _I8042_H */ |