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[NET]: Make NAPI polling independent of struct net_device objects.
[linux.git] / drivers / net / epic100.c
CommitLineData
1da177e4
LT		 1/* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2/*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as [email protected], or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
36e1e847 22 [this link no longer provides anything useful -jgarzik]
1da177e4
LT		 23
24 ---------------------------------------------------------------------
f3b197ac 25
1da177e4
LT		 26*/
27
28#define DRV_NAME "epic100"
d5b20697
AG		 29#define DRV_VERSION "2.1"
30#define DRV_RELDATE "Sept 11, 2006"
1da177e4
LT		 31
32/* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36
37/* Used to pass the full-duplex flag, etc. */
38#define MAX_UNITS 8 /* More are supported, limit only on options */
39static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
41
42/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43 Setting to > 1518 effectively disables this feature. */
44static int rx_copybreak;
45
46/* Operational parameters that are set at compile time. */
47
48/* Keep the ring sizes a power of two for operational efficiency.
49 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50 Making the Tx ring too large decreases the effectiveness of channel
51 bonding and packet priority.
52 There are no ill effects from too-large receive rings. */
53#define TX_RING_SIZE 256
54#define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55#define RX_RING_SIZE 256
56#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
58
59/* Operational parameters that usually are not changed. */
60/* Time in jiffies before concluding the transmitter is hung. */
61#define TX_TIMEOUT (2*HZ)
62
63#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
64
65/* Bytes transferred to chip before transmission starts. */
66/* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67#define TX_FIFO_THRESH 256
68#define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
69
1da177e4
LT		 70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/string.h>
73#include <linux/timer.h>
74#include <linux/errno.h>
75#include <linux/ioport.h>
76#include <linux/slab.h>
77#include <linux/interrupt.h>
78#include <linux/pci.h>
79#include <linux/delay.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/init.h>
84#include <linux/spinlock.h>
85#include <linux/ethtool.h>
86#include <linux/mii.h>
87#include <linux/crc32.h>
88#include <linux/bitops.h>
89#include <asm/io.h>
90#include <asm/uaccess.h>
91
92/* These identify the driver base version and may not be removed. */
93static char version[] __devinitdata =
94DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <[email protected]>\n";
95static char version2[] __devinitdata =
1da177e4
LT		 96" (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
97
98MODULE_AUTHOR("Donald Becker <[email protected]>");
99MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
100MODULE_LICENSE("GPL");
101
102module_param(debug, int, 0);
103module_param(rx_copybreak, int, 0);
104module_param_array(options, int, NULL, 0);
105module_param_array(full_duplex, int, NULL, 0);
106MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
107MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
108MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
109MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
110
111/*
112 Theory of Operation
113
114I. Board Compatibility
115
116This device driver is designed for the SMC "EPIC/100", the SMC
117single-chip Ethernet controllers for PCI. This chip is used on
118the SMC EtherPower II boards.
119
120II. Board-specific settings
121
122PCI bus devices are configured by the system at boot time, so no jumpers
123need to be set on the board. The system BIOS will assign the
124PCI INTA signal to a (preferably otherwise unused) system IRQ line.
125Note: Kernel versions earlier than 1.3.73 do not support shared PCI
126interrupt lines.
127
128III. Driver operation
129
130IIIa. Ring buffers
131
132IVb. References
133
134http://www.smsc.com/main/datasheets/83c171.pdf
135http://www.smsc.com/main/datasheets/83c175.pdf
136http://scyld.com/expert/NWay.html
137http://www.national.com/pf/DP/DP83840A.html
138
139IVc. Errata
140
141*/
142
143
1da177e4
LT		 144enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
145
146#define EPIC_TOTAL_SIZE 0x100
147#define USE_IO_OPS 1
1da177e4
LT		 148
149typedef enum {
150 SMSC_83C170_0,
151 SMSC_83C170,
152 SMSC_83C175,
153} chip_t;
154
155
156struct epic_chip_info {
157 const char *name;
1da177e4
LT		 158 int drv_flags; /* Driver use, intended as capability flags. */
159};
160
161
162/* indexed by chip_t */
f71e1309 163static const struct epic_chip_info pci_id_tbl[] = {
36e1e847
JG		 164 { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
165 { "SMSC EPIC/100 83c170", TYPE2_INTR },
166 { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
1da177e4
LT		 167};
168
169
170static struct pci_device_id epic_pci_tbl[] = {
171 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
172 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
173 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
174 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
175 { 0,}
176};
177MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
178
f3b197ac 179
1da177e4
LT		 180#ifndef USE_IO_OPS
181#undef inb
182#undef inw
183#undef inl
184#undef outb
185#undef outw
186#undef outl
187#define inb readb
188#define inw readw
189#define inl readl
190#define outb writeb
191#define outw writew
192#define outl writel
193#endif
194
195/* Offsets to registers, using the (ugh) SMC names. */
196enum epic_registers {
197 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
198 PCIBurstCnt=0x18,
199 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
200 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
201 LAN0=64, /* MAC address. */
202 MC0=80, /* Multicast filter table. */
203 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
204 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
205};
206
207/* Interrupt register bits, using my own meaningful names. */
208enum IntrStatus {
209 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
210 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
211 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
212 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
213 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
214};
215enum CommandBits {
216 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
217 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
218};
219
220#define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
221
222#define EpicNapiEvent (TxEmpty | TxDone | \
223 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
224#define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
225
f71e1309 226static const u16 media2miictl[16] = {
1da177e4
LT		 227 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0 };
229
230/* The EPIC100 Rx and Tx buffer descriptors. */
231
232struct epic_tx_desc {
233 u32 txstatus;
234 u32 bufaddr;
235 u32 buflength;
236 u32 next;
237};
238
239struct epic_rx_desc {
240 u32 rxstatus;
241 u32 bufaddr;
242 u32 buflength;
243 u32 next;
244};
245
246enum desc_status_bits {
247 DescOwn=0x8000,
248};
249
250#define PRIV_ALIGN 15 /* Required alignment mask */
251struct epic_private {
252 struct epic_rx_desc *rx_ring;
253 struct epic_tx_desc *tx_ring;
254 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
255 struct sk_buff* tx_skbuff[TX_RING_SIZE];
256 /* The addresses of receive-in-place skbuffs. */
257 struct sk_buff* rx_skbuff[RX_RING_SIZE];
258
259 dma_addr_t tx_ring_dma;
260 dma_addr_t rx_ring_dma;
261
262 /* Ring pointers. */
263 spinlock_t lock; /* Group with Tx control cache line. */
264 spinlock_t napi_lock;
bea3348e 265 struct napi_struct napi;
1da177e4
LT		 266 unsigned int reschedule_in_poll;
267 unsigned int cur_tx, dirty_tx;
268
269 unsigned int cur_rx, dirty_rx;
270 u32 irq_mask;
271 unsigned int rx_buf_sz; /* Based on MTU+slack. */
272
273 struct pci_dev *pci_dev; /* PCI bus location. */
274 int chip_id, chip_flags;
275
276 struct net_device_stats stats;
277 struct timer_list timer; /* Media selection timer. */
278 int tx_threshold;
279 unsigned char mc_filter[8];
280 signed char phys[4]; /* MII device addresses. */
281 u16 advertising; /* NWay media advertisement */
282 int mii_phy_cnt;
283 struct mii_if_info mii;
284 unsigned int tx_full:1; /* The Tx queue is full. */
285 unsigned int default_port:4; /* Last dev->if_port value. */
286};
287
288static int epic_open(struct net_device *dev);
289static int read_eeprom(long ioaddr, int location);
290static int mdio_read(struct net_device *dev, int phy_id, int location);
291static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
292static void epic_restart(struct net_device *dev);
293static void epic_timer(unsigned long data);
294static void epic_tx_timeout(struct net_device *dev);
295static void epic_init_ring(struct net_device *dev);
296static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
297static int epic_rx(struct net_device *dev, int budget);
bea3348e 298static int epic_poll(struct napi_struct *napi, int budget);
7d12e780 299static irqreturn_t epic_interrupt(int irq, void *dev_instance);
1da177e4 300static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
7282d491 301static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 302static int epic_close(struct net_device *dev);
303static struct net_device_stats *epic_get_stats(struct net_device *dev);
304static void set_rx_mode(struct net_device *dev);
305
f3b197ac 306
1da177e4
LT		 307
308static int __devinit epic_init_one (struct pci_dev *pdev,
309 const struct pci_device_id *ent)
310{
311 static int card_idx = -1;
312 long ioaddr;
313 int chip_idx = (int) ent->driver_data;
314 int irq;
315 struct net_device *dev;
316 struct epic_private *ep;
317 int i, ret, option = 0, duplex = 0;
318 void *ring_space;
319 dma_addr_t ring_dma;
320
321/* when built into the kernel, we only print version if device is found */
322#ifndef MODULE
323 static int printed_version;
324 if (!printed_version++)
2c2a8c53
MD		 325 printk (KERN_INFO "%s" KERN_INFO "%s",
326 version, version2);
1da177e4 327#endif
f3b197ac 328
1da177e4 329 card_idx++;
f3b197ac 330
1da177e4
LT		 331 ret = pci_enable_device(pdev);
332 if (ret)
333 goto out;
334 irq = pdev->irq;
335
36e1e847 336 if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
9b91cf9d 337 dev_err(&pdev->dev, "no PCI region space\n");
1da177e4
LT		 338 ret = -ENODEV;
339 goto err_out_disable;
340 }
f3b197ac 341
1da177e4
LT		 342 pci_set_master(pdev);
343
344 ret = pci_request_regions(pdev, DRV_NAME);
345 if (ret < 0)
346 goto err_out_disable;
347
348 ret = -ENOMEM;
349
350 dev = alloc_etherdev(sizeof (*ep));
351 if (!dev) {
9b91cf9d 352 dev_err(&pdev->dev, "no memory for eth device\n");
1da177e4
LT		 353 goto err_out_free_res;
354 }
355 SET_MODULE_OWNER(dev);
356 SET_NETDEV_DEV(dev, &pdev->dev);
357
358#ifdef USE_IO_OPS
359 ioaddr = pci_resource_start (pdev, 0);
360#else
361 ioaddr = pci_resource_start (pdev, 1);
362 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
363 if (!ioaddr) {
9b91cf9d 364 dev_err(&pdev->dev, "ioremap failed\n");
1da177e4
LT		 365 goto err_out_free_netdev;
366 }
367#endif
368
369 pci_set_drvdata(pdev, dev);
370 ep = dev->priv;
371 ep->mii.dev = dev;
372 ep->mii.mdio_read = mdio_read;
373 ep->mii.mdio_write = mdio_write;
374 ep->mii.phy_id_mask = 0x1f;
375 ep->mii.reg_num_mask = 0x1f;
376
377 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
378 if (!ring_space)
379 goto err_out_iounmap;
380 ep->tx_ring = (struct epic_tx_desc *)ring_space;
381 ep->tx_ring_dma = ring_dma;
382
383 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
384 if (!ring_space)
385 goto err_out_unmap_tx;
386 ep->rx_ring = (struct epic_rx_desc *)ring_space;
387 ep->rx_ring_dma = ring_dma;
388
389 if (dev->mem_start) {
390 option = dev->mem_start;
391 duplex = (dev->mem_start & 16) ? 1 : 0;
392 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
393 if (options[card_idx] >= 0)
394 option = options[card_idx];
395 if (full_duplex[card_idx] >= 0)
396 duplex = full_duplex[card_idx];
397 }
398
399 dev->base_addr = ioaddr;
400 dev->irq = irq;
401
402 spin_lock_init(&ep->lock);
403 spin_lock_init(&ep->napi_lock);
404 ep->reschedule_in_poll = 0;
405
406 /* Bring the chip out of low-power mode. */
407 outl(0x4200, ioaddr + GENCTL);
408 /* Magic?! If we don't set this bit the MII interface won't work. */
409 /* This magic is documented in SMSC app note 7.15 */
410 for (i = 16; i > 0; i--)
411 outl(0x0008, ioaddr + TEST1);
412
413 /* Turn on the MII transceiver. */
414 outl(0x12, ioaddr + MIICfg);
415 if (chip_idx == 1)
416 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
417 outl(0x0200, ioaddr + GENCTL);
418
419 /* Note: the '175 does not have a serial EEPROM. */
420 for (i = 0; i < 3; i++)
421 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
422
423 if (debug > 2) {
2e8a538d 424 dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
1da177e4
LT		 425 for (i = 0; i < 64; i++)
426 printk(" %4.4x%s", read_eeprom(ioaddr, i),
427 i % 16 == 15 ? "\n" : "");
428 }
429
430 ep->pci_dev = pdev;
431 ep->chip_id = chip_idx;
432 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
f3b197ac 433 ep->irq_mask =
1da177e4
LT		 434 (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
435 | CntFull | TxUnderrun | EpicNapiEvent;
436
437 /* Find the connected MII xcvrs.
438 Doing this in open() would allow detecting external xcvrs later, but
439 takes much time and no cards have external MII. */
440 {
441 int phy, phy_idx = 0;
442 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
443 int mii_status = mdio_read(dev, phy, MII_BMSR);
444 if (mii_status != 0xffff && mii_status != 0x0000) {
445 ep->phys[phy_idx++] = phy;
9b91cf9d 446 dev_info(&pdev->dev,
2e8a538d
JG		 447 "MII transceiver #%d control "
448 "%4.4x status %4.4x.\n",
449 phy, mdio_read(dev, phy, 0), mii_status);
1da177e4
LT		 450 }
451 }
452 ep->mii_phy_cnt = phy_idx;
453 if (phy_idx != 0) {
454 phy = ep->phys[0];
455 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
9b91cf9d 456 dev_info(&pdev->dev,
2e8a538d 457 "Autonegotiation advertising %4.4x link "
1da177e4 458 "partner %4.4x.\n",
2e8a538d 459 ep->mii.advertising, mdio_read(dev, phy, 5));
1da177e4 460 } else if ( ! (ep->chip_flags & NO_MII)) {
9b91cf9d 461 dev_warn(&pdev->dev,
2e8a538d 462 "***WARNING***: No MII transceiver found!\n");
1da177e4
LT		 463 /* Use the known PHY address of the EPII. */
464 ep->phys[0] = 3;
465 }
466 ep->mii.phy_id = ep->phys[0];
467 }
468
469 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
470 if (ep->chip_flags & MII_PWRDWN)
471 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
472 outl(0x0008, ioaddr + GENCTL);
473
474 /* The lower four bits are the media type. */
475 if (duplex) {
476 ep->mii.force_media = ep->mii.full_duplex = 1;
9b91cf9d 477 dev_info(&pdev->dev, "Forced full duplex requested.\n");
1da177e4
LT		 478 }
479 dev->if_port = ep->default_port = option;
480
481 /* The Epic-specific entries in the device structure. */
482 dev->open = &epic_open;
483 dev->hard_start_xmit = &epic_start_xmit;
484 dev->stop = &epic_close;
485 dev->get_stats = &epic_get_stats;
486 dev->set_multicast_list = &set_rx_mode;
487 dev->do_ioctl = &netdev_ioctl;
488 dev->ethtool_ops = &netdev_ethtool_ops;
489 dev->watchdog_timeo = TX_TIMEOUT;
490 dev->tx_timeout = &epic_tx_timeout;
bea3348e 491 netif_napi_add(dev, &ep->napi, epic_poll, 64);
1da177e4
LT		 492
493 ret = register_netdev(dev);
494 if (ret < 0)
495 goto err_out_unmap_rx;
496
497 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
498 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq);
499 for (i = 0; i < 5; i++)
500 printk("%2.2x:", dev->dev_addr[i]);
501 printk("%2.2x.\n", dev->dev_addr[i]);
502
503out:
504 return ret;
505
506err_out_unmap_rx:
507 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
508err_out_unmap_tx:
509 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
510err_out_iounmap:
511#ifndef USE_IO_OPS
512 iounmap(ioaddr);
513err_out_free_netdev:
514#endif
515 free_netdev(dev);
516err_out_free_res:
517 pci_release_regions(pdev);
518err_out_disable:
519 pci_disable_device(pdev);
520 goto out;
521}
f3b197ac 522
1da177e4
LT		 523/* Serial EEPROM section. */
524
525/* EEPROM_Ctrl bits. */
526#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
527#define EE_CS 0x02 /* EEPROM chip select. */
528#define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
529#define EE_WRITE_0 0x01
530#define EE_WRITE_1 0x09
531#define EE_DATA_READ 0x10 /* EEPROM chip data out. */
532#define EE_ENB (0x0001 | EE_CS)
533
534/* Delay between EEPROM clock transitions.
535 This serves to flush the operation to the PCI bus.
536 */
537
538#define eeprom_delay() inl(ee_addr)
539
540/* The EEPROM commands include the alway-set leading bit. */
541#define EE_WRITE_CMD (5 << 6)
542#define EE_READ64_CMD (6 << 6)
543#define EE_READ256_CMD (6 << 8)
544#define EE_ERASE_CMD (7 << 6)
545
546static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
547{
548 long ioaddr = dev->base_addr;
549
550 outl(0x00000000, ioaddr + INTMASK);
551}
552
553static inline void __epic_pci_commit(long ioaddr)
554{
555#ifndef USE_IO_OPS
556 inl(ioaddr + INTMASK);
557#endif
558}
559
560static inline void epic_napi_irq_off(struct net_device *dev,
561 struct epic_private *ep)
562{
563 long ioaddr = dev->base_addr;
564
565 outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
566 __epic_pci_commit(ioaddr);
567}
568
569static inline void epic_napi_irq_on(struct net_device *dev,
570 struct epic_private *ep)
571{
572 long ioaddr = dev->base_addr;
573
574 /* No need to commit possible posted write */
575 outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
576}
577
578static int __devinit read_eeprom(long ioaddr, int location)
579{
580 int i;
581 int retval = 0;
582 long ee_addr = ioaddr + EECTL;
583 int read_cmd = location |
584 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
585
586 outl(EE_ENB & ~EE_CS, ee_addr);
587 outl(EE_ENB, ee_addr);
588
589 /* Shift the read command bits out. */
590 for (i = 12; i >= 0; i--) {
591 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
592 outl(EE_ENB | dataval, ee_addr);
593 eeprom_delay();
594 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
595 eeprom_delay();
596 }
597 outl(EE_ENB, ee_addr);
598
599 for (i = 16; i > 0; i--) {
600 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
601 eeprom_delay();
602 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
603 outl(EE_ENB, ee_addr);
604 eeprom_delay();
605 }
606
607 /* Terminate the EEPROM access. */
608 outl(EE_ENB & ~EE_CS, ee_addr);
609 return retval;
610}
611
612#define MII_READOP 1
613#define MII_WRITEOP 2
614static int mdio_read(struct net_device *dev, int phy_id, int location)
615{
616 long ioaddr = dev->base_addr;
617 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
618 int i;
619
620 outl(read_cmd, ioaddr + MIICtrl);
621 /* Typical operation takes 25 loops. */
622 for (i = 400; i > 0; i--) {
623 barrier();
624 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
625 /* Work around read failure bug. */
626 if (phy_id == 1 && location < 6
627 && inw(ioaddr + MIIData) == 0xffff) {
628 outl(read_cmd, ioaddr + MIICtrl);
629 continue;
630 }
631 return inw(ioaddr + MIIData);
632 }
633 }
634 return 0xffff;
635}
636
637static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
638{
639 long ioaddr = dev->base_addr;
640 int i;
641
642 outw(value, ioaddr + MIIData);
643 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
f3b197ac 644 for (i = 10000; i > 0; i--) {
1da177e4
LT		 645 barrier();
646 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
647 break;
648 }
649 return;
650}
651
f3b197ac 652
1da177e4
LT		 653static int epic_open(struct net_device *dev)
654{
655 struct epic_private *ep = dev->priv;
656 long ioaddr = dev->base_addr;
657 int i;
658 int retval;
659
660 /* Soft reset the chip. */
661 outl(0x4001, ioaddr + GENCTL);
662
bea3348e
SH		 663 napi_enable(&ep->napi);
664 if ((retval = request_irq(dev->irq, &epic_interrupt, IRQF_SHARED, dev->name, dev))) {
665 napi_disable(&ep->napi);
1da177e4 666 return retval;
bea3348e 667 }
1da177e4
LT		 668
669 epic_init_ring(dev);
670
671 outl(0x4000, ioaddr + GENCTL);
672 /* This magic is documented in SMSC app note 7.15 */
673 for (i = 16; i > 0; i--)
674 outl(0x0008, ioaddr + TEST1);
675
676 /* Pull the chip out of low-power mode, enable interrupts, and set for
677 PCI read multiple. The MIIcfg setting and strange write order are
678 required by the details of which bits are reset and the transceiver
679 wiring on the Ositech CardBus card.
680 */
681#if 0
682 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
683#endif
684 if (ep->chip_flags & MII_PWRDWN)
685 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
686
687#if defined(__powerpc__) || defined(__sparc__) /* Big endian */
688 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
689 inl(ioaddr + GENCTL);
690 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
691#else
692 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
693 inl(ioaddr + GENCTL);
694 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
695#endif
696
697 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
f3b197ac 698
1da177e4
LT		 699 for (i = 0; i < 3; i++)
700 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
701
702 ep->tx_threshold = TX_FIFO_THRESH;
703 outl(ep->tx_threshold, ioaddr + TxThresh);
704
705 if (media2miictl[dev->if_port & 15]) {
706 if (ep->mii_phy_cnt)
707 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
708 if (dev->if_port == 1) {
709 if (debug > 1)
710 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
711 "status %4.4x.\n",
712 dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
713 }
714 } else {
715 int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
716 if (mii_lpa != 0xffff) {
717 if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
718 ep->mii.full_duplex = 1;
719 else if (! (mii_lpa & LPA_LPACK))
720 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
721 if (debug > 1)
722 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
723 " register read of %4.4x.\n", dev->name,
724 ep->mii.full_duplex ? "full" : "half",
725 ep->phys[0], mii_lpa);
726 }
727 }
728
729 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
730 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
731 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
732
733 /* Start the chip's Rx process. */
734 set_rx_mode(dev);
735 outl(StartRx | RxQueued, ioaddr + COMMAND);
736
737 netif_start_queue(dev);
738
739 /* Enable interrupts by setting the interrupt mask. */
740 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
f3b197ac 741 | CntFull | TxUnderrun
1da177e4
LT		 742 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
743
744 if (debug > 1)
745 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
746 "%s-duplex.\n",
747 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
748 ep->mii.full_duplex ? "full" : "half");
749
750 /* Set the timer to switch to check for link beat and perhaps switch
751 to an alternate media type. */
752 init_timer(&ep->timer);
753 ep->timer.expires = jiffies + 3*HZ;
754 ep->timer.data = (unsigned long)dev;
755 ep->timer.function = &epic_timer; /* timer handler */
756 add_timer(&ep->timer);
757
758 return 0;
759}
760
761/* Reset the chip to recover from a PCI transaction error.
762 This may occur at interrupt time. */
763static void epic_pause(struct net_device *dev)
764{
765 long ioaddr = dev->base_addr;
766 struct epic_private *ep = dev->priv;
767
768 netif_stop_queue (dev);
f3b197ac 769
1da177e4
LT		 770 /* Disable interrupts by clearing the interrupt mask. */
771 outl(0x00000000, ioaddr + INTMASK);
772 /* Stop the chip's Tx and Rx DMA processes. */
773 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
774
775 /* Update the error counts. */
776 if (inw(ioaddr + COMMAND) != 0xffff) {
777 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
778 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
779 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
780 }
781
782 /* Remove the packets on the Rx queue. */
783 epic_rx(dev, RX_RING_SIZE);
784}
785
786static void epic_restart(struct net_device *dev)
787{
788 long ioaddr = dev->base_addr;
789 struct epic_private *ep = dev->priv;
790 int i;
791
792 /* Soft reset the chip. */
793 outl(0x4001, ioaddr + GENCTL);
794
795 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
796 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
797 udelay(1);
798
799 /* This magic is documented in SMSC app note 7.15 */
800 for (i = 16; i > 0; i--)
801 outl(0x0008, ioaddr + TEST1);
802
803#if defined(__powerpc__) || defined(__sparc__) /* Big endian */
804 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
805#else
806 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
807#endif
808 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
809 if (ep->chip_flags & MII_PWRDWN)
810 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
811
812 for (i = 0; i < 3; i++)
813 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
814
815 ep->tx_threshold = TX_FIFO_THRESH;
816 outl(ep->tx_threshold, ioaddr + TxThresh);
817 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
818 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
819 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
820 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
821 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
822
823 /* Start the chip's Rx process. */
824 set_rx_mode(dev);
825 outl(StartRx | RxQueued, ioaddr + COMMAND);
826
827 /* Enable interrupts by setting the interrupt mask. */
828 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
829 | CntFull | TxUnderrun
830 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
831
832 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
833 " interrupt %4.4x.\n",
834 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
835 (int)inl(ioaddr + INTSTAT));
836 return;
837}
838
839static void check_media(struct net_device *dev)
840{
841 struct epic_private *ep = dev->priv;
842 long ioaddr = dev->base_addr;
843 int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
844 int negotiated = mii_lpa & ep->mii.advertising;
845 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
846
847 if (ep->mii.force_media)
848 return;
849 if (mii_lpa == 0xffff) /* Bogus read */
850 return;
851 if (ep->mii.full_duplex != duplex) {
852 ep->mii.full_duplex = duplex;
853 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
854 " partner capability of %4.4x.\n", dev->name,
855 ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
856 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
857 }
858}
859
860static void epic_timer(unsigned long data)
861{
862 struct net_device *dev = (struct net_device *)data;
863 struct epic_private *ep = dev->priv;
864 long ioaddr = dev->base_addr;
865 int next_tick = 5*HZ;
866
867 if (debug > 3) {
868 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
869 dev->name, (int)inl(ioaddr + TxSTAT));
870 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
871 "IntStatus %4.4x RxStatus %4.4x.\n",
872 dev->name, (int)inl(ioaddr + INTMASK),
873 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
874 }
875
876 check_media(dev);
877
878 ep->timer.expires = jiffies + next_tick;
879 add_timer(&ep->timer);
880}
881
882static void epic_tx_timeout(struct net_device *dev)
883{
884 struct epic_private *ep = dev->priv;
885 long ioaddr = dev->base_addr;
886
887 if (debug > 0) {
888 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
889 "Tx status %4.4x.\n",
890 dev->name, (int)inw(ioaddr + TxSTAT));
891 if (debug > 1) {
892 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
893 dev->name, ep->dirty_tx, ep->cur_tx);
894 }
895 }
896 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
897 ep->stats.tx_fifo_errors++;
898 outl(RestartTx, ioaddr + COMMAND);
899 } else {
900 epic_restart(dev);
901 outl(TxQueued, dev->base_addr + COMMAND);
902 }
903
904 dev->trans_start = jiffies;
905 ep->stats.tx_errors++;
906 if (!ep->tx_full)
907 netif_wake_queue(dev);
908}
909
910/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
911static void epic_init_ring(struct net_device *dev)
912{
913 struct epic_private *ep = dev->priv;
914 int i;
915
916 ep->tx_full = 0;
917 ep->dirty_tx = ep->cur_tx = 0;
918 ep->cur_rx = ep->dirty_rx = 0;
919 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
920
921 /* Initialize all Rx descriptors. */
922 for (i = 0; i < RX_RING_SIZE; i++) {
923 ep->rx_ring[i].rxstatus = 0;
924 ep->rx_ring[i].buflength = cpu_to_le32(ep->rx_buf_sz);
f3b197ac 925 ep->rx_ring[i].next = ep->rx_ring_dma +
1da177e4
LT		 926 (i+1)*sizeof(struct epic_rx_desc);
927 ep->rx_skbuff[i] = NULL;
928 }
929 /* Mark the last entry as wrapping the ring. */
930 ep->rx_ring[i-1].next = ep->rx_ring_dma;
931
932 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
933 for (i = 0; i < RX_RING_SIZE; i++) {
934 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
935 ep->rx_skbuff[i] = skb;
936 if (skb == NULL)
937 break;
1da177e4 938 skb_reserve(skb, 2); /* 16 byte align the IP header. */
f3b197ac 939 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
689be439 940 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT		 941 ep->rx_ring[i].rxstatus = cpu_to_le32(DescOwn);
942 }
943 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
944
945 /* The Tx buffer descriptor is filled in as needed, but we
946 do need to clear the ownership bit. */
947 for (i = 0; i < TX_RING_SIZE; i++) {
948 ep->tx_skbuff[i] = NULL;
949 ep->tx_ring[i].txstatus = 0x0000;
f3b197ac 950 ep->tx_ring[i].next = ep->tx_ring_dma +
1da177e4
LT		 951 (i+1)*sizeof(struct epic_tx_desc);
952 }
953 ep->tx_ring[i-1].next = ep->tx_ring_dma;
954 return;
955}
956
957static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
958{
959 struct epic_private *ep = dev->priv;
960 int entry, free_count;
961 u32 ctrl_word;
962 unsigned long flags;
f3b197ac 963
5b057c6b
HX		 964 if (skb_padto(skb, ETH_ZLEN))
965 return 0;
1da177e4
LT		 966
967 /* Caution: the write order is important here, set the field with the
968 "ownership" bit last. */
969
970 /* Calculate the next Tx descriptor entry. */
971 spin_lock_irqsave(&ep->lock, flags);
972 free_count = ep->cur_tx - ep->dirty_tx;
973 entry = ep->cur_tx % TX_RING_SIZE;
974
975 ep->tx_skbuff[entry] = skb;
f3b197ac 976 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
1da177e4
LT		 977 skb->len, PCI_DMA_TODEVICE);
978 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
979 ctrl_word = cpu_to_le32(0x100000); /* No interrupt */
980 } else if (free_count == TX_QUEUE_LEN/2) {
981 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
982 } else if (free_count < TX_QUEUE_LEN - 1) {
983 ctrl_word = cpu_to_le32(0x100000); /* No Tx-done intr. */
984 } else {
985 /* Leave room for an additional entry. */
986 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
987 ep->tx_full = 1;
988 }
989 ep->tx_ring[entry].buflength = ctrl_word | cpu_to_le32(skb->len);
990 ep->tx_ring[entry].txstatus =
991 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
992 | cpu_to_le32(DescOwn);
993
994 ep->cur_tx++;
995 if (ep->tx_full)
996 netif_stop_queue(dev);
997
998 spin_unlock_irqrestore(&ep->lock, flags);
999 /* Trigger an immediate transmit demand. */
1000 outl(TxQueued, dev->base_addr + COMMAND);
1001
1002 dev->trans_start = jiffies;
1003 if (debug > 4)
1004 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1005 "flag %2.2x Tx status %8.8x.\n",
1006 dev->name, (int)skb->len, entry, ctrl_word,
1007 (int)inl(dev->base_addr + TxSTAT));
1008
1009 return 0;
1010}
1011
1012static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1013 int status)
1014{
1015 struct net_device_stats *stats = &ep->stats;
1016
1017#ifndef final_version
1018 /* There was an major error, log it. */
1019 if (debug > 1)
1020 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1021 dev->name, status);
1022#endif
1023 stats->tx_errors++;
1024 if (status & 0x1050)
1025 stats->tx_aborted_errors++;
1026 if (status & 0x0008)
1027 stats->tx_carrier_errors++;
1028 if (status & 0x0040)
1029 stats->tx_window_errors++;
1030 if (status & 0x0010)
1031 stats->tx_fifo_errors++;
1032}
1033
1034static void epic_tx(struct net_device *dev, struct epic_private *ep)
1035{
1036 unsigned int dirty_tx, cur_tx;
1037
1038 /*
1039 * Note: if this lock becomes a problem we can narrow the locked
1040 * region at the cost of occasionally grabbing the lock more times.
1041 */
1042 cur_tx = ep->cur_tx;
1043 for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1044 struct sk_buff *skb;
1045 int entry = dirty_tx % TX_RING_SIZE;
1046 int txstatus = le32_to_cpu(ep->tx_ring[entry].txstatus);
1047
1048 if (txstatus & DescOwn)
1049 break; /* It still hasn't been Txed */
1050
1051 if (likely(txstatus & 0x0001)) {
1052 ep->stats.collisions += (txstatus >> 8) & 15;
1053 ep->stats.tx_packets++;
1054 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1055 } else
1056 epic_tx_error(dev, ep, txstatus);
1057
1058 /* Free the original skb. */
1059 skb = ep->tx_skbuff[entry];
f3b197ac 1060 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1da177e4
LT		 1061 skb->len, PCI_DMA_TODEVICE);
1062 dev_kfree_skb_irq(skb);
1063 ep->tx_skbuff[entry] = NULL;
1064 }
1065
1066#ifndef final_version
1067 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1068 printk(KERN_WARNING
1069 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1070 dev->name, dirty_tx, cur_tx, ep->tx_full);
1071 dirty_tx += TX_RING_SIZE;
1072 }
1073#endif
1074 ep->dirty_tx = dirty_tx;
1075 if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1076 /* The ring is no longer full, allow new TX entries. */
1077 ep->tx_full = 0;
1078 netif_wake_queue(dev);
1079 }
1080}
1081
1082/* The interrupt handler does all of the Rx thread work and cleans up
1083 after the Tx thread. */
7d12e780 1084static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1da177e4
LT		 1085{
1086 struct net_device *dev = dev_instance;
1087 struct epic_private *ep = dev->priv;
1088 long ioaddr = dev->base_addr;
1089 unsigned int handled = 0;
1090 int status;
1091
1092 status = inl(ioaddr + INTSTAT);
1093 /* Acknowledge all of the current interrupt sources ASAP. */
1094 outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1095
1096 if (debug > 4) {
1097 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1098 "intstat=%#8.8x.\n", dev->name, status,
1099 (int)inl(ioaddr + INTSTAT));
1100 }
1101
1102 if ((status & IntrSummary) == 0)
1103 goto out;
1104
1105 handled = 1;
1106
1107 if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1108 spin_lock(&ep->napi_lock);
bea3348e 1109 if (netif_rx_schedule_prep(dev, &ep->napi)) {
1da177e4 1110 epic_napi_irq_off(dev, ep);
bea3348e 1111 __netif_rx_schedule(dev, &ep->napi);
1da177e4
LT		 1112 } else
1113 ep->reschedule_in_poll++;
1114 spin_unlock(&ep->napi_lock);
1115 }
1116 status &= ~EpicNapiEvent;
1117
1118 /* Check uncommon events all at once. */
1119 if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1120 if (status == EpicRemoved)
1121 goto out;
1122
1123 /* Always update the error counts to avoid overhead later. */
1124 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1125 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1126 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1127
1128 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1129 ep->stats.tx_fifo_errors++;
1130 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1131 /* Restart the transmit process. */
1132 outl(RestartTx, ioaddr + COMMAND);
1133 }
1134 if (status & PCIBusErr170) {
1135 printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1136 dev->name, status);
1137 epic_pause(dev);
1138 epic_restart(dev);
1139 }
1140 /* Clear all error sources. */
1141 outl(status & 0x7f18, ioaddr + INTSTAT);
1142 }
1143
1144out:
1145 if (debug > 3) {
1146 printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1147 dev->name, status);
1148 }
1149
1150 return IRQ_RETVAL(handled);
1151}
1152
1153static int epic_rx(struct net_device *dev, int budget)
1154{
1155 struct epic_private *ep = dev->priv;
1156 int entry = ep->cur_rx % RX_RING_SIZE;
1157 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1158 int work_done = 0;
1159
1160 if (debug > 4)
1161 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1162 ep->rx_ring[entry].rxstatus);
1163
1164 if (rx_work_limit > budget)
1165 rx_work_limit = budget;
1166
1167 /* If we own the next entry, it's a new packet. Send it up. */
1168 while ((ep->rx_ring[entry].rxstatus & cpu_to_le32(DescOwn)) == 0) {
1169 int status = le32_to_cpu(ep->rx_ring[entry].rxstatus);
1170
1171 if (debug > 4)
1172 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1173 if (--rx_work_limit < 0)
1174 break;
1175 if (status & 0x2006) {
1176 if (debug > 2)
1177 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1178 dev->name, status);
1179 if (status & 0x2000) {
1180 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1181 "multiple buffers, status %4.4x!\n", dev->name, status);
1182 ep->stats.rx_length_errors++;
1183 } else if (status & 0x0006)
1184 /* Rx Frame errors are counted in hardware. */
1185 ep->stats.rx_errors++;
1186 } else {
1187 /* Malloc up new buffer, compatible with net-2e. */
1188 /* Omit the four octet CRC from the length. */
1189 short pkt_len = (status >> 16) - 4;
1190 struct sk_buff *skb;
1191
1192 if (pkt_len > PKT_BUF_SZ - 4) {
1193 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1194 "%d bytes.\n",
1195 dev->name, status, pkt_len);
1196 pkt_len = 1514;
1197 }
1198 /* Check if the packet is long enough to accept without copying
1199 to a minimally-sized skbuff. */
1200 if (pkt_len < rx_copybreak
1201 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 1202 skb_reserve(skb, 2); /* 16 byte align the IP header */
1203 pci_dma_sync_single_for_cpu(ep->pci_dev,
1204 ep->rx_ring[entry].bufaddr,
1205 ep->rx_buf_sz,
1206 PCI_DMA_FROMDEVICE);
8c7b7faa 1207 skb_copy_to_linear_data(skb, ep->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 1208 skb_put(skb, pkt_len);
1209 pci_dma_sync_single_for_device(ep->pci_dev,
1210 ep->rx_ring[entry].bufaddr,
1211 ep->rx_buf_sz,
1212 PCI_DMA_FROMDEVICE);
1213 } else {
f3b197ac
JG		 1214 pci_unmap_single(ep->pci_dev,
1215 ep->rx_ring[entry].bufaddr,
1da177e4
LT		 1216 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1217 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1218 ep->rx_skbuff[entry] = NULL;
1219 }
1220 skb->protocol = eth_type_trans(skb, dev);
1221 netif_receive_skb(skb);
1222 dev->last_rx = jiffies;
1223 ep->stats.rx_packets++;
1224 ep->stats.rx_bytes += pkt_len;
1225 }
1226 work_done++;
1227 entry = (++ep->cur_rx) % RX_RING_SIZE;
1228 }
1229
1230 /* Refill the Rx ring buffers. */
1231 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1232 entry = ep->dirty_rx % RX_RING_SIZE;
1233 if (ep->rx_skbuff[entry] == NULL) {
1234 struct sk_buff *skb;
1235 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1236 if (skb == NULL)
1237 break;
1da177e4 1238 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
f3b197ac 1239 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
689be439 1240 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1241 work_done++;
1242 }
1243 ep->rx_ring[entry].rxstatus = cpu_to_le32(DescOwn);
1244 }
1245 return work_done;
1246}
1247
1248static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1249{
1250 long ioaddr = dev->base_addr;
1251 int status;
1252
1253 status = inl(ioaddr + INTSTAT);
1254
1255 if (status == EpicRemoved)
1256 return;
1257 if (status & RxOverflow) /* Missed a Rx frame. */
1258 ep->stats.rx_errors++;
1259 if (status & (RxOverflow | RxFull))
1260 outw(RxQueued, ioaddr + COMMAND);
1261}
1262
bea3348e 1263static int epic_poll(struct napi_struct *napi, int budget)
1da177e4 1264{
bea3348e
SH		 1265 struct epic_private *ep = container_of(napi, struct epic_private, napi);
1266 struct net_device *dev = ep->mii.dev;
1267 int work_done = 0;
1da177e4
LT		 1268 long ioaddr = dev->base_addr;
1269
1da177e4
LT		 1270rx_action:
1271
1272 epic_tx(dev, ep);
1273
bea3348e 1274 work_done += epic_rx(dev, budget);
1da177e4
LT		 1275
1276 epic_rx_err(dev, ep);
1277
bea3348e 1278 if (netif_running(dev) && (work_done < budget)) {
1da177e4
LT		 1279 unsigned long flags;
1280 int more;
1281
1282 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1283
1284 spin_lock_irqsave(&ep->napi_lock, flags);
1285
1286 more = ep->reschedule_in_poll;
1287 if (!more) {
bea3348e 1288 __netif_rx_complete(dev, napi);
1da177e4
LT		 1289 outl(EpicNapiEvent, ioaddr + INTSTAT);
1290 epic_napi_irq_on(dev, ep);
1291 } else
1292 ep->reschedule_in_poll--;
1293
1294 spin_unlock_irqrestore(&ep->napi_lock, flags);
1295
1296 if (more)
1297 goto rx_action;
1298 }
1299
bea3348e 1300 return work_done;
1da177e4
LT		 1301}
1302
1303static int epic_close(struct net_device *dev)
1304{
1305 long ioaddr = dev->base_addr;
1306 struct epic_private *ep = dev->priv;
1307 struct sk_buff *skb;
1308 int i;
1309
1310 netif_stop_queue(dev);
bea3348e 1311 napi_disable(&ep->napi);
1da177e4
LT		 1312
1313 if (debug > 1)
1314 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1315 dev->name, (int)inl(ioaddr + INTSTAT));
1316
1317 del_timer_sync(&ep->timer);
1318
1319 epic_disable_int(dev, ep);
1320
1321 free_irq(dev->irq, dev);
1322
1323 epic_pause(dev);
1324
1325 /* Free all the skbuffs in the Rx queue. */
1326 for (i = 0; i < RX_RING_SIZE; i++) {
1327 skb = ep->rx_skbuff[i];
1328 ep->rx_skbuff[i] = NULL;
1329 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1330 ep->rx_ring[i].buflength = 0;
1331 if (skb) {
f3b197ac 1332 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1da177e4
LT		 1333 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1334 dev_kfree_skb(skb);
1335 }
1336 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1337 }
1338 for (i = 0; i < TX_RING_SIZE; i++) {
1339 skb = ep->tx_skbuff[i];
1340 ep->tx_skbuff[i] = NULL;
1341 if (!skb)
1342 continue;
f3b197ac 1343 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1da177e4
LT		 1344 skb->len, PCI_DMA_TODEVICE);
1345 dev_kfree_skb(skb);
1346 }
1347
1348 /* Green! Leave the chip in low-power mode. */
1349 outl(0x0008, ioaddr + GENCTL);
1350
1351 return 0;
1352}
1353
1354static struct net_device_stats *epic_get_stats(struct net_device *dev)
1355{
1356 struct epic_private *ep = dev->priv;
1357 long ioaddr = dev->base_addr;
1358
1359 if (netif_running(dev)) {
1360 /* Update the error counts. */
1361 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1362 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1363 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1364 }
1365
1366 return &ep->stats;
1367}
1368
1369/* Set or clear the multicast filter for this adaptor.
1370 Note that we only use exclusion around actually queueing the
1371 new frame, not around filling ep->setup_frame. This is non-deterministic
1372 when re-entered but still correct. */
1373
1374static void set_rx_mode(struct net_device *dev)
1375{
1376 long ioaddr = dev->base_addr;
1377 struct epic_private *ep = dev->priv;
1378 unsigned char mc_filter[8]; /* Multicast hash filter */
1379 int i;
1380
1381 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1382 outl(0x002C, ioaddr + RxCtrl);
1383 /* Unconditionally log net taps. */
1da177e4
LT		 1384 memset(mc_filter, 0xff, sizeof(mc_filter));
1385 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1386 /* There is apparently a chip bug, so the multicast filter
1387 is never enabled. */
1388 /* Too many to filter perfectly -- accept all multicasts. */
1389 memset(mc_filter, 0xff, sizeof(mc_filter));
1390 outl(0x000C, ioaddr + RxCtrl);
1391 } else if (dev->mc_count == 0) {
1392 outl(0x0004, ioaddr + RxCtrl);
1393 return;
1394 } else { /* Never executed, for now. */
1395 struct dev_mc_list *mclist;
1396
1397 memset(mc_filter, 0, sizeof(mc_filter));
1398 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1399 i++, mclist = mclist->next) {
1400 unsigned int bit_nr =
1401 ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f;
1402 mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1403 }
1404 }
1405 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1406 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1407 for (i = 0; i < 4; i++)
1408 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1409 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1410 }
1411 return;
1412}
1413
1414static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1415{
1416 struct epic_private *np = dev->priv;
1417
1418 strcpy (info->driver, DRV_NAME);
1419 strcpy (info->version, DRV_VERSION);
1420 strcpy (info->bus_info, pci_name(np->pci_dev));
1421}
1422
1423static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1424{
1425 struct epic_private *np = dev->priv;
1426 int rc;
1427
1428 spin_lock_irq(&np->lock);
1429 rc = mii_ethtool_gset(&np->mii, cmd);
1430 spin_unlock_irq(&np->lock);
1431
1432 return rc;
1433}
1434
1435static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1436{
1437 struct epic_private *np = dev->priv;
1438 int rc;
1439
1440 spin_lock_irq(&np->lock);
1441 rc = mii_ethtool_sset(&np->mii, cmd);
1442 spin_unlock_irq(&np->lock);
1443
1444 return rc;
1445}
1446
1447static int netdev_nway_reset(struct net_device *dev)
1448{
1449 struct epic_private *np = dev->priv;
1450 return mii_nway_restart(&np->mii);
1451}
1452
1453static u32 netdev_get_link(struct net_device *dev)
1454{
1455 struct epic_private *np = dev->priv;
1456 return mii_link_ok(&np->mii);
1457}
1458
1459static u32 netdev_get_msglevel(struct net_device *dev)
1460{
1461 return debug;
1462}
1463
1464static void netdev_set_msglevel(struct net_device *dev, u32 value)
1465{
1466 debug = value;
1467}
1468
1469static int ethtool_begin(struct net_device *dev)
1470{
1471 unsigned long ioaddr = dev->base_addr;
1472 /* power-up, if interface is down */
1473 if (! netif_running(dev)) {
1474 outl(0x0200, ioaddr + GENCTL);
1475 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1476 }
1477 return 0;
1478}
1479
1480static void ethtool_complete(struct net_device *dev)
1481{
1482 unsigned long ioaddr = dev->base_addr;
1483 /* power-down, if interface is down */
1484 if (! netif_running(dev)) {
1485 outl(0x0008, ioaddr + GENCTL);
1486 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1487 }
1488}
1489
7282d491 1490static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 1491 .get_drvinfo = netdev_get_drvinfo,
1492 .get_settings = netdev_get_settings,
1493 .set_settings = netdev_set_settings,
1494 .nway_reset = netdev_nway_reset,
1495 .get_link = netdev_get_link,
1496 .get_msglevel = netdev_get_msglevel,
1497 .set_msglevel = netdev_set_msglevel,
1498 .get_sg = ethtool_op_get_sg,
1499 .get_tx_csum = ethtool_op_get_tx_csum,
1500 .begin = ethtool_begin,
1501 .complete = ethtool_complete
1502};
1503
1504static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1505{
1506 struct epic_private *np = dev->priv;
1507 long ioaddr = dev->base_addr;
1508 struct mii_ioctl_data *data = if_mii(rq);
1509 int rc;
1510
1511 /* power-up, if interface is down */
1512 if (! netif_running(dev)) {
1513 outl(0x0200, ioaddr + GENCTL);
1514 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1515 }
1516
1517 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1518 spin_lock_irq(&np->lock);
1519 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1520 spin_unlock_irq(&np->lock);
1521
1522 /* power-down, if interface is down */
1523 if (! netif_running(dev)) {
1524 outl(0x0008, ioaddr + GENCTL);
1525 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1526 }
1527 return rc;
1528}
1529
1530
1531static void __devexit epic_remove_one (struct pci_dev *pdev)
1532{
1533 struct net_device *dev = pci_get_drvdata(pdev);
1534 struct epic_private *ep = dev->priv;
f3b197ac 1535
1da177e4
LT		 1536 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1537 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1538 unregister_netdev(dev);
1539#ifndef USE_IO_OPS
1540 iounmap((void*) dev->base_addr);
1541#endif
1542 pci_release_regions(pdev);
1543 free_netdev(dev);
1544 pci_disable_device(pdev);
1545 pci_set_drvdata(pdev, NULL);
1546 /* pci_power_off(pdev, -1); */
1547}
1548
1549
1550#ifdef CONFIG_PM
1551
1552static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1553{
1554 struct net_device *dev = pci_get_drvdata(pdev);
1555 long ioaddr = dev->base_addr;
1556
1557 if (!netif_running(dev))
1558 return 0;
1559 epic_pause(dev);
1560 /* Put the chip into low-power mode. */
1561 outl(0x0008, ioaddr + GENCTL);
1562 /* pci_power_off(pdev, -1); */
1563 return 0;
1564}
1565
1566
1567static int epic_resume (struct pci_dev *pdev)
1568{
1569 struct net_device *dev = pci_get_drvdata(pdev);
1570
1571 if (!netif_running(dev))
1572 return 0;
1573 epic_restart(dev);
1574 /* pci_power_on(pdev); */
1575 return 0;
1576}
1577
1578#endif /* CONFIG_PM */
1579
1580
1581static struct pci_driver epic_driver = {
1582 .name = DRV_NAME,
1583 .id_table = epic_pci_tbl,
1584 .probe = epic_init_one,
1585 .remove = __devexit_p(epic_remove_one),
1586#ifdef CONFIG_PM
1587 .suspend = epic_suspend,
1588 .resume = epic_resume,
1589#endif /* CONFIG_PM */
1590};
1591
1592
1593static int __init epic_init (void)
1594{
1595/* when a module, this is printed whether or not devices are found in probe */
1596#ifdef MODULE
2c2a8c53
MD		 1597 printk (KERN_INFO "%s" KERN_INFO "%s",
1598 version, version2);
1da177e4
LT		 1599#endif
1600
29917620 1601 return pci_register_driver(&epic_driver);
1da177e4
LT		 1602}
1603
1604
1605static void __exit epic_cleanup (void)
1606{
1607 pci_unregister_driver (&epic_driver);
1608}
1609
1610
1611module_init(epic_init);
1612module_exit(epic_cleanup);
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