[linux.git] / drivers / gpio / gpio-xlp.c

/*
 * Copyright (C) 2003-2015 Broadcom Corporation
 * All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/acpi.h>

/*
 * XLP GPIO has multiple 32 bit registers for each feature where each register
 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
 * require 3 32-bit registers for each feature.
 * Here we only define offset of the first register for each feature. Offset of
 * the registers for pins greater than 32 can be calculated as following(Use
 * GPIO_INT_STAT as example):
 *
 * offset = (gpio / XLP_GPIO_REGSZ) * 4;
 * reg_addr = addr + offset;
 *
 * where addr is base address of the that feature register and gpio is the pin.
 */
#define GPIO_OUTPUT_EN		0x00
#define GPIO_PADDRV		0x08
#define GPIO_INT_EN00		0x18
#define GPIO_INT_EN10		0x20
#define GPIO_INT_EN20		0x28
#define GPIO_INT_EN30		0x30
#define GPIO_INT_POL		0x38
#define GPIO_INT_TYPE		0x40
#define GPIO_INT_STAT		0x48

#define GPIO_9XX_BYTESWAP	0X00
#define GPIO_9XX_CTRL		0X04
#define GPIO_9XX_OUTPUT_EN	0x14
#define GPIO_9XX_PADDRV		0x24
/*
 * Only for 4 interrupt enable reg are defined for now,
 * total reg available are 12.
 */
#define GPIO_9XX_INT_EN00	0x44
#define GPIO_9XX_INT_EN10	0x54
#define GPIO_9XX_INT_EN20	0x64
#define GPIO_9XX_INT_EN30	0x74
#define GPIO_9XX_INT_POL	0x104
#define GPIO_9XX_INT_TYPE	0x114
#define GPIO_9XX_INT_STAT	0x124

#define GPIO_3XX_INT_EN00	0x18
#define GPIO_3XX_INT_EN10	0x20
#define GPIO_3XX_INT_EN20	0x28
#define GPIO_3XX_INT_EN30	0x30
#define GPIO_3XX_INT_POL	0x78
#define GPIO_3XX_INT_TYPE	0x80
#define GPIO_3XX_INT_STAT	0x88

/* Interrupt type register mask */
#define XLP_GPIO_IRQ_TYPE_LVL	0x0
#define XLP_GPIO_IRQ_TYPE_EDGE	0x1

/* Interrupt polarity register mask */
#define XLP_GPIO_IRQ_POL_HIGH	0x0
#define XLP_GPIO_IRQ_POL_LOW	0x1

#define XLP_GPIO_REGSZ		32
#define XLP_GPIO_IRQ_BASE	768
#define XLP_MAX_NR_GPIO		96

/* XLP variants supported by this driver */
enum {
	XLP_GPIO_VARIANT_XLP832 = 1,
	XLP_GPIO_VARIANT_XLP316,
	XLP_GPIO_VARIANT_XLP208,
	XLP_GPIO_VARIANT_XLP980,
	XLP_GPIO_VARIANT_XLP532,
	GPIO_VARIANT_VULCAN
};

struct xlp_gpio_priv {
	struct gpio_chip chip;
	DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
	void __iomem *gpio_intr_en;	/* pointer to first intr enable reg */
	void __iomem *gpio_intr_stat;	/* pointer to first intr status reg */
	void __iomem *gpio_intr_type;	/* pointer to first intr type reg */
	void __iomem *gpio_intr_pol;	/* pointer to first intr polarity reg */
	void __iomem *gpio_out_en;	/* pointer to first output enable reg */
	void __iomem *gpio_paddrv;	/* pointer to first pad drive reg */
	spinlock_t lock;
};

static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
{
	u32 pos, regset;

	pos = gpio % XLP_GPIO_REGSZ;
	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	return !!(readl(addr + regset) & BIT(pos));
}

static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
{
	u32 value, pos, regset;

	pos = gpio % XLP_GPIO_REGSZ;
	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	value = readl(addr + regset);

	if (state)
		value |= BIT(pos);
	else
		value &= ~BIT(pos);

	writel(value, addr + regset);
}

static void xlp_gpio_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static void xlp_gpio_irq_mask_ack(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static void xlp_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
	__set_bit(d->hwirq, priv->gpio_enabled_mask);
	spin_unlock_irqrestore(&priv->lock, flags);
}

static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
	int pol, irq_type;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
		pol = XLP_GPIO_IRQ_POL_HIGH;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
		pol = XLP_GPIO_IRQ_POL_LOW;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irq_type = XLP_GPIO_IRQ_TYPE_LVL;
		pol = XLP_GPIO_IRQ_POL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irq_type = XLP_GPIO_IRQ_TYPE_LVL;
		pol = XLP_GPIO_IRQ_POL_LOW;
		break;
	default:
		return -EINVAL;
	}

	xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
	xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);

	return 0;
}

static struct irq_chip xlp_gpio_irq_chip = {
	.name		= "XLP-GPIO",
	.irq_mask_ack	= xlp_gpio_irq_mask_ack,
	.irq_disable	= xlp_gpio_irq_disable,
	.irq_set_type	= xlp_gpio_set_irq_type,
	.irq_unmask	= xlp_gpio_irq_unmask,
	.flags		= IRQCHIP_ONESHOT_SAFE,
};

static void xlp_gpio_generic_handler(struct irq_desc *desc)
{
	struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	int gpio, regoff;
	u32 gpio_stat;

	regoff = -1;
	gpio_stat = 0;

	chained_irq_enter(irqchip, desc);
	for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
		if (regoff != gpio / XLP_GPIO_REGSZ) {
			regoff = gpio / XLP_GPIO_REGSZ;
			gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
		}

		if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
			generic_handle_irq(irq_find_mapping(
						priv->chip.irqdomain, gpio));
	}
	chained_irq_exit(irqchip, desc);
}

static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
{
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);

	return 0;
}

static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
{
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);

	return 0;
}

static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
{
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);

	BUG_ON(gpio >= gc->ngpio);
	return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
}

static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
{
	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);

	BUG_ON(gpio >= gc->ngpio);
	xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
}

static const struct of_device_id xlp_gpio_of_ids[] = {
	{
		.compatible = "netlogic,xlp832-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP832,
	},
	{
		.compatible = "netlogic,xlp316-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP316,
	},
	{
		.compatible = "netlogic,xlp208-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP208,
	},
	{
		.compatible = "netlogic,xlp980-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP980,
	},
	{
		.compatible = "netlogic,xlp532-gpio",
		.data	    = (void *)XLP_GPIO_VARIANT_XLP532,
	},
	{
		.compatible = "brcm,vulcan-gpio",
		.data	    = (void *)GPIO_VARIANT_VULCAN,
	},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);

static int xlp_gpio_probe(struct platform_device *pdev)
{
	struct gpio_chip *gc;
	struct resource *iores;
	struct xlp_gpio_priv *priv;
	void __iomem *gpio_base;
	int irq_base, irq, err;
	int ngpio;
	u32 soc_type;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iores)
		return -ENODEV;

	priv = devm_kzalloc(&pdev->dev,	sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	gpio_base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(gpio_base))
		return PTR_ERR(gpio_base);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	if (pdev->dev.of_node) {
		const struct of_device_id *of_id;

		of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev);
		if (!of_id) {
			dev_err(&pdev->dev, "Unable to match OF ID\n");
			return -ENODEV;
		}
		soc_type = (uintptr_t) of_id->data;
	} else {
		const struct acpi_device_id *acpi_id;

		acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
						&pdev->dev);
		if (!acpi_id || !acpi_id->driver_data) {
			dev_err(&pdev->dev, "Unable to match ACPI ID\n");
			return -ENODEV;
		}
		soc_type = (uintptr_t) acpi_id->driver_data;
	}

	switch (soc_type) {
	case XLP_GPIO_VARIANT_XLP832:
		priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
		priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
		priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
		priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
		priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
		priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
		ngpio = 41;
		break;
	case XLP_GPIO_VARIANT_XLP208:
	case XLP_GPIO_VARIANT_XLP316:
		priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
		priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
		priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
		priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
		priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
		priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;

		ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
		break;
	case XLP_GPIO_VARIANT_XLP980:
	case XLP_GPIO_VARIANT_XLP532:
	case GPIO_VARIANT_VULCAN:
		priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
		priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
		priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
		priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
		priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
		priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;

		if (soc_type == XLP_GPIO_VARIANT_XLP980)
			ngpio = 66;
		else if (soc_type == XLP_GPIO_VARIANT_XLP532)
			ngpio = 67;
		else
			ngpio = 70;
		break;
	default:
		dev_err(&pdev->dev, "Unknown Processor type!\n");
		return -ENODEV;
	}

	bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);

	gc = &priv->chip;

	gc->owner = THIS_MODULE;
	gc->label = dev_name(&pdev->dev);
	gc->base = 0;
	gc->parent = &pdev->dev;
	gc->ngpio = ngpio;
	gc->of_node = pdev->dev.of_node;
	gc->direction_output = xlp_gpio_dir_output;
	gc->direction_input = xlp_gpio_dir_input;
	gc->set = xlp_gpio_set;
	gc->get = xlp_gpio_get;

	spin_lock_init(&priv->lock);

	/* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */
	if (soc_type != GPIO_VARIANT_VULCAN) {
		irq_base = irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE, gc->ngpio, 0);
		if (irq_base < 0) {
			dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
			return irq_base;
		}
	} else {
		irq_base = 0;
	}

	err = gpiochip_add_data(gc, priv);
	if (err < 0)
		goto out_free_desc;

	err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base,
				handle_level_irq, IRQ_TYPE_NONE);
	if (err) {
		dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n");
		goto out_gpio_remove;
	}

	gpiochip_set_chained_irqchip(gc, &xlp_gpio_irq_chip, irq,
			xlp_gpio_generic_handler);

	dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);

	return 0;

out_gpio_remove:
	gpiochip_remove(gc);
out_free_desc:
	irq_free_descs(irq_base, gc->ngpio);
	return err;
}

#ifdef CONFIG_ACPI
static const struct acpi_device_id xlp_gpio_acpi_match[] = {
	{ "BRCM9006", GPIO_VARIANT_VULCAN },
	{},
};
MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
#endif

static struct platform_driver xlp_gpio_driver = {
	.driver		= {
		.name	= "xlp-gpio",
		.of_match_table = xlp_gpio_of_ids,
		.acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
	},
	.probe		= xlp_gpio_probe,
};
module_platform_driver(xlp_gpio_driver);

MODULE_AUTHOR("Kamlakant Patel <[email protected]>");
MODULE_AUTHOR("Ganesan Ramalingam <[email protected]>");
MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ff718800 KP	1	/*
	2	* Copyright (C) 2003-2015 Broadcom Corporation
	3	* All Rights Reserved
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/gpio.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/of_device.h>
	18	#include <linux/module.h>
	19	#include <linux/irq.h>
	20	#include <linux/interrupt.h>
83ea24fd	21	#include <linux/irqchip/chained_irq.h>
baa1b920	22	#include <linux/acpi.h>
ff718800 KP	23
	24	/*
	25	* XLP GPIO has multiple 32 bit registers for each feature where each register
	26	* controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
	27	* require 3 32-bit registers for each feature.
	28	* Here we only define offset of the first register for each feature. Offset of
	29	* the registers for pins greater than 32 can be calculated as following(Use
	30	* GPIO_INT_STAT as example):
	31	*
	32	* offset = (gpio / XLP_GPIO_REGSZ) * 4;
	33	* reg_addr = addr + offset;
	34	*
	35	* where addr is base address of the that feature register and gpio is the pin.
	36	*/
	37	#define GPIO_OUTPUT_EN 0x00
	38	#define GPIO_PADDRV 0x08
	39	#define GPIO_INT_EN00 0x18
	40	#define GPIO_INT_EN10 0x20
	41	#define GPIO_INT_EN20 0x28
	42	#define GPIO_INT_EN30 0x30
	43	#define GPIO_INT_POL 0x38
	44	#define GPIO_INT_TYPE 0x40
	45	#define GPIO_INT_STAT 0x48
	46
	47	#define GPIO_9XX_BYTESWAP 0X00
	48	#define GPIO_9XX_CTRL 0X04
	49	#define GPIO_9XX_OUTPUT_EN 0x14
	50	#define GPIO_9XX_PADDRV 0x24
	51	/*
	52	* Only for 4 interrupt enable reg are defined for now,
	53	* total reg available are 12.
	54	*/
	55	#define GPIO_9XX_INT_EN00 0x44
	56	#define GPIO_9XX_INT_EN10 0x54
	57	#define GPIO_9XX_INT_EN20 0x64
	58	#define GPIO_9XX_INT_EN30 0x74
	59	#define GPIO_9XX_INT_POL 0x104
	60	#define GPIO_9XX_INT_TYPE 0x114
	61	#define GPIO_9XX_INT_STAT 0x124
	62
	63	#define GPIO_3XX_INT_EN00 0x18
	64	#define GPIO_3XX_INT_EN10 0x20
	65	#define GPIO_3XX_INT_EN20 0x28
	66	#define GPIO_3XX_INT_EN30 0x30
	67	#define GPIO_3XX_INT_POL 0x78
	68	#define GPIO_3XX_INT_TYPE 0x80
	69	#define GPIO_3XX_INT_STAT 0x88
	70
	71	/* Interrupt type register mask */
	72	#define XLP_GPIO_IRQ_TYPE_LVL 0x0
	73	#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
	74
	75	/* Interrupt polarity register mask */
	76	#define XLP_GPIO_IRQ_POL_HIGH 0x0
	77	#define XLP_GPIO_IRQ_POL_LOW 0x1
	78
	79	#define XLP_GPIO_REGSZ 32
	80	#define XLP_GPIO_IRQ_BASE 768
	81	#define XLP_MAX_NR_GPIO 96
	82
	83	/* XLP variants supported by this driver */
	84	enum {
	85	XLP_GPIO_VARIANT_XLP832 = 1,
	86	XLP_GPIO_VARIANT_XLP316,
87	XLP_GPIO_VARIANT_XLP208,
88	XLP_GPIO_VARIANT_XLP980,
dd98756d KP	89	XLP_GPIO_VARIANT_XLP532,
dd98756d KP	90	GPIO_VARIANT_VULCAN
ff718800 KP	91	};
	92
	93	struct xlp_gpio_priv {
	94	struct gpio_chip chip;
	95	DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
	96	void __iomem gpio_intr_en; / pointer to first intr enable reg */
	97	void __iomem gpio_intr_stat; / pointer to first intr status reg */
	98	void __iomem gpio_intr_type; / pointer to first intr type reg */
	99	void __iomem gpio_intr_pol; / pointer to first intr polarity reg */
	100	void __iomem gpio_out_en; / pointer to first output enable reg */
	101	void __iomem gpio_paddrv; / pointer to first pad drive reg */
	102	spinlock_t lock;
	103	};
	104
ff718800 KP	105	static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
	106	{
	107	u32 pos, regset;
	108
	109	pos = gpio % XLP_GPIO_REGSZ;
	110	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	111	return !!(readl(addr + regset) & BIT(pos));
	112	}
	113
	114	static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
	115	{
	116	u32 value, pos, regset;
	117
	118	pos = gpio % XLP_GPIO_REGSZ;
	119	regset = (gpio / XLP_GPIO_REGSZ) * 4;
	120	value = readl(addr + regset);
	121
	122	if (state)
	123	value \|= BIT(pos);
	124	else
	125	value &= ~BIT(pos);
	126
	127	writel(value, addr + regset);
	128	}
	129
	130	static void xlp_gpio_irq_disable(struct irq_data *d)
	131	{
	132	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
e730a595	133	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	134	unsigned long flags;
	135
	136	spin_lock_irqsave(&priv->lock, flags);
	137	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	138	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	139	spin_unlock_irqrestore(&priv->lock, flags);
	140	}
	141
	142	static void xlp_gpio_irq_mask_ack(struct irq_data *d)
	143	{
	144	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
e730a595	145	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	146	unsigned long flags;
	147
	148	spin_lock_irqsave(&priv->lock, flags);
	149	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
	150	xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
	151	__clear_bit(d->hwirq, priv->gpio_enabled_mask);
	152	spin_unlock_irqrestore(&priv->lock, flags);
	153	}
	154
	155	static void xlp_gpio_irq_unmask(struct irq_data *d)
	156	{
	157	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
e730a595	158	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	159	unsigned long flags;
	160
	161	spin_lock_irqsave(&priv->lock, flags);
	162	xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
	163	__set_bit(d->hwirq, priv->gpio_enabled_mask);
	164	spin_unlock_irqrestore(&priv->lock, flags);
	165	}
	166
	167	static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
	168	{
	169	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
e730a595	170	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	171	int pol, irq_type;
	172
	173	switch (type) {
	174	case IRQ_TYPE_EDGE_RISING:
	175	irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
	176	pol = XLP_GPIO_IRQ_POL_HIGH;
	177	break;
	178	case IRQ_TYPE_EDGE_FALLING:
	179	irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
	180	pol = XLP_GPIO_IRQ_POL_LOW;
	181	break;
	182	case IRQ_TYPE_LEVEL_HIGH:
	183	irq_type = XLP_GPIO_IRQ_TYPE_LVL;
	184	pol = XLP_GPIO_IRQ_POL_HIGH;
	185	break;
	186	case IRQ_TYPE_LEVEL_LOW:
	187	irq_type = XLP_GPIO_IRQ_TYPE_LVL;
	188	pol = XLP_GPIO_IRQ_POL_LOW;
	189	break;
	190	default:
	191	return -EINVAL;
	192	}
	193
	194	xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
	195	xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
	196
	197	return 0;
	198	}
	199
	200	static struct irq_chip xlp_gpio_irq_chip = {
	201	.name = "XLP-GPIO",
	202	.irq_mask_ack = xlp_gpio_irq_mask_ack,
	203	.irq_disable = xlp_gpio_irq_disable,
	204	.irq_set_type = xlp_gpio_set_irq_type,
	205	.irq_unmask = xlp_gpio_irq_unmask,
	206	.flags = IRQCHIP_ONESHOT_SAFE,
	207	};
	208
83ea24fd	209	static void xlp_gpio_generic_handler(struct irq_desc *desc)
ff718800	210	{
83ea24fd KP	211	struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
83ea24fd KP	212	struct irq_chip *irqchip = irq_desc_get_chip(desc);
ff718800 KP	213	int gpio, regoff;
	214	u32 gpio_stat;
	215
	216	regoff = -1;
	217	gpio_stat = 0;
83ea24fd KP	218
83ea24fd KP	219	chained_irq_enter(irqchip, desc);
ff718800 KP	220	for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
	221	if (regoff != gpio / XLP_GPIO_REGSZ) {
	222	regoff = gpio / XLP_GPIO_REGSZ;
	223	gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
	224	}
83ea24fd	225
ff718800 KP	226	if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
	227	generic_handle_irq(irq_find_mapping(
	228	priv->chip.irqdomain, gpio));
	229	}
83ea24fd	230	chained_irq_exit(irqchip, desc);
ff718800 KP	231	}
	232
	233	static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
	234	{
e730a595	235	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	236
	237	BUG_ON(gpio >= gc->ngpio);
	238	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
	239
	240	return 0;
	241	}
	242
	243	static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
	244	{
e730a595	245	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	246
	247	BUG_ON(gpio >= gc->ngpio);
	248	xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
	249
	250	return 0;
	251	}
	252
	253	static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
	254	{
e730a595	255	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	256
	257	BUG_ON(gpio >= gc->ngpio);
	258	return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
	259	}
	260
	261	static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
	262	{
e730a595	263	struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
ff718800 KP	264
	265	BUG_ON(gpio >= gc->ngpio);
	266	xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
	267	}
	268
	269	static const struct of_device_id xlp_gpio_of_ids[] = {
	270	{
	271	.compatible = "netlogic,xlp832-gpio",
	272	.data = (void *)XLP_GPIO_VARIANT_XLP832,
	273	},
	274	{
	275	.compatible = "netlogic,xlp316-gpio",
	276	.data = (void *)XLP_GPIO_VARIANT_XLP316,
	277	},
	278	{
	279	.compatible = "netlogic,xlp208-gpio",
	280	.data = (void *)XLP_GPIO_VARIANT_XLP208,
	281	},
	282	{
	283	.compatible = "netlogic,xlp980-gpio",
	284	.data = (void *)XLP_GPIO_VARIANT_XLP980,
	285	},
	286	{
	287	.compatible = "netlogic,xlp532-gpio",
	288	.data = (void *)XLP_GPIO_VARIANT_XLP532,
	289	},
dd98756d KP	290	{
	291	.compatible = "brcm,vulcan-gpio",
	292	.data = (void *)GPIO_VARIANT_VULCAN,
	293	},
ff718800 KP	294	{ /* sentinel */ },
	295	};
	296	MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
	297
	298	static int xlp_gpio_probe(struct platform_device *pdev)
	299	{
	300	struct gpio_chip *gc;
	301	struct resource *iores;
	302	struct xlp_gpio_priv *priv;
ff718800 KP	303	void __iomem *gpio_base;
	304	int irq_base, irq, err;
	305	int ngpio;
	306	u32 soc_type;
	307
	308	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	309	if (!iores)
	310	return -ENODEV;
	311
	312	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	313	if (!priv)
	314	return -ENOMEM;
	315
	316	gpio_base = devm_ioremap_resource(&pdev->dev, iores);
	317	if (IS_ERR(gpio_base))
	318	return PTR_ERR(gpio_base);
	319
	320	irq = platform_get_irq(pdev, 0);
	321	if (irq < 0)
	322	return irq;
	323
baa1b920 KP	324	if (pdev->dev.of_node) {
baa1b920 KP	325	const struct of_device_id *of_id;
ff718800	326
baa1b920 KP	327	of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev);
	328	if (!of_id) {
	329	dev_err(&pdev->dev, "Unable to match OF ID\n");
	330	return -ENODEV;
	331	}
	332	soc_type = (uintptr_t) of_id->data;
	333	} else {
	334	const struct acpi_device_id *acpi_id;
	335
	336	acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
	337	&pdev->dev);
	338	if (!acpi_id \|\| !acpi_id->driver_data) {
	339	dev_err(&pdev->dev, "Unable to match ACPI ID\n");
	340	return -ENODEV;
	341	}
	342	soc_type = (uintptr_t) acpi_id->driver_data;
	343	}
ff718800 KP	344
	345	switch (soc_type) {
	346	case XLP_GPIO_VARIANT_XLP832:
	347	priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
	348	priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
	349	priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
	350	priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
	351	priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
	352	priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
	353	ngpio = 41;
	354	break;
	355	case XLP_GPIO_VARIANT_XLP208:
	356	case XLP_GPIO_VARIANT_XLP316:
	357	priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
	358	priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
	359	priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
	360	priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
	361	priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
	362	priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
	363
	364	ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
	365	break;
	366	case XLP_GPIO_VARIANT_XLP980:
	367	case XLP_GPIO_VARIANT_XLP532:
dd98756d	368	case GPIO_VARIANT_VULCAN:
ff718800 KP	369	priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
	370	priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
	371	priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
	372	priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
	373	priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
	374	priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
	375
dd98756d KP	376	if (soc_type == XLP_GPIO_VARIANT_XLP980)
	377	ngpio = 66;
	378	else if (soc_type == XLP_GPIO_VARIANT_XLP532)
	379	ngpio = 67;
	380	else
	381	ngpio = 70;
ff718800 KP	382	break;
	383	default:
	384	dev_err(&pdev->dev, "Unknown Processor type!\n");
	385	return -ENODEV;
	386	}
	387
	388	bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
	389
	390	gc = &priv->chip;
	391
b8a3f52e AL	392	gc->owner = THIS_MODULE;
b8a3f52e AL	393	gc->label = dev_name(&pdev->dev);
ff718800	394	gc->base = 0;
58383c78	395	gc->parent = &pdev->dev;
ff718800 KP	396	gc->ngpio = ngpio;
	397	gc->of_node = pdev->dev.of_node;
	398	gc->direction_output = xlp_gpio_dir_output;
	399	gc->direction_input = xlp_gpio_dir_input;
	400	gc->set = xlp_gpio_set;
	401	gc->get = xlp_gpio_get;
	402
	403	spin_lock_init(&priv->lock);
1630a062 KP	404
	405	/* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */
	406	if (soc_type != GPIO_VARIANT_VULCAN) {
dd98756d	407	irq_base = irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE, gc->ngpio, 0);
1630a062 KP	408	if (irq_base < 0) {
	409	dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
	410	return irq_base;
	411	}
	412	} else {
	413	irq_base = 0;
ff718800 KP	414	}
ff718800 KP	415
e730a595	416	err = gpiochip_add_data(gc, priv);
ff718800 KP	417	if (err < 0)
	418	goto out_free_desc;
	419
	420	err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base,
	421	handle_level_irq, IRQ_TYPE_NONE);
	422	if (err) {
	423	dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n");
	424	goto out_gpio_remove;
	425	}
	426
83ea24fd KP	427	gpiochip_set_chained_irqchip(gc, &xlp_gpio_irq_chip, irq,
	428	xlp_gpio_generic_handler);
	429
ff718800 KP	430	dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
	431
	432	return 0;
	433
	434	out_gpio_remove:
	435	gpiochip_remove(gc);
	436	out_free_desc:
	437	irq_free_descs(irq_base, gc->ngpio);
	438	return err;
	439	}
	440
baa1b920 KP	441	#ifdef CONFIG_ACPI
	442	static const struct acpi_device_id xlp_gpio_acpi_match[] = {
	443	{ "BRCM9006", GPIO_VARIANT_VULCAN },
	444	{},
	445	};
	446	MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
	447	#endif
	448
ff718800 KP	449	static struct platform_driver xlp_gpio_driver = {
	450	.driver = {
	451	.name = "xlp-gpio",
	452	.of_match_table = xlp_gpio_of_ids,
baa1b920	453	.acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
ff718800 KP	454	},
	455	.probe = xlp_gpio_probe,
	456	};
	457	module_platform_driver(xlp_gpio_driver);
	458
	459	MODULE_AUTHOR("Kamlakant Patel <[email protected]>");
	460	MODULE_AUTHOR("Ganesan Ramalingam <[email protected]>");
	461	MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
	462	MODULE_LICENSE("GPL v2");