[linux.git] / drivers / gpio / gpio-xgene-sb.c

/*
 * AppliedMicro X-Gene SoC GPIO-Standby Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Author:	Tin Huynh <[email protected]>.
 *		Y Vo <[email protected]>.
 *		Quan Nguyen <[email protected]>.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/module.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of_gpio.h>
#include <linux/gpio/driver.h>
#include <linux/acpi.h>

#include "gpiolib.h"

/* Common property names */
#define XGENE_NIRQ_PROPERTY		"apm,nr-irqs"
#define XGENE_NGPIO_PROPERTY		"apm,nr-gpios"
#define XGENE_IRQ_START_PROPERTY	"apm,irq-start"

#define XGENE_DFLT_MAX_NGPIO		22
#define XGENE_DFLT_MAX_NIRQ		6
#define XGENE_DFLT_IRQ_START_PIN	8
#define GPIO_MASK(x)			(1U << ((x) % 32))

#define MPA_GPIO_INT_LVL		0x0290
#define MPA_GPIO_OE_ADDR		0x029c
#define MPA_GPIO_OUT_ADDR		0x02a0
#define MPA_GPIO_IN_ADDR 		0x02a4
#define MPA_GPIO_SEL_LO 		0x0294

#define GPIO_INT_LEVEL_H	0x000001
#define GPIO_INT_LEVEL_L	0x000000

/**
 * struct xgene_gpio_sb - GPIO-Standby private data structure.
 * @gc:				memory-mapped GPIO controllers.
 * @regs:			GPIO register base offset
 * @irq_domain:			GPIO interrupt domain
 * @irq_start:			GPIO pin that start support interrupt
 * @nirq:			Number of GPIO pins that supports interrupt
 * @parent_irq_base:		Start parent HWIRQ
 */
struct xgene_gpio_sb {
	struct gpio_chip	gc;
	void __iomem		*regs;
	struct irq_domain	*irq_domain;
	u16			irq_start;
	u16			nirq;
	u16			parent_irq_base;
};

#define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
#define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)

static void xgene_gpio_set_bit(struct gpio_chip *gc,
				void __iomem *reg, u32 gpio, int val)
{
	u32 data;

	data = gc->read_reg(reg);
	if (val)
		data |= GPIO_MASK(gpio);
	else
		data &= ~GPIO_MASK(gpio);
	gc->write_reg(reg, data);
}

static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
	int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
	int lvl_type = GPIO_INT_LEVEL_H;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LEVEL_H;
		break;
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LEVEL_L;
		break;
	default:
		break;
	}

	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
			gpio * 2, 1);
	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
			d->hwirq, lvl_type);

	/* Propagate IRQ type setting to parent */
	if (type & IRQ_TYPE_EDGE_BOTH)
		return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
	else
		return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
}

static struct irq_chip xgene_gpio_sb_irq_chip = {
	.name           = "sbgpio",
	.irq_eoi	= irq_chip_eoi_parent,
	.irq_mask       = irq_chip_mask_parent,
	.irq_unmask     = irq_chip_unmask_parent,
	.irq_set_type   = xgene_gpio_sb_irq_set_type,
};

static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
{
	struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
	struct irq_fwspec fwspec;

	if ((gpio < priv->irq_start) ||
			(gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
		return -ENXIO;

	if (gc->parent->of_node)
		fwspec.fwnode = of_node_to_fwnode(gc->parent->of_node);
	else
		fwspec.fwnode = gc->parent->fwnode;
	fwspec.param_count = 2;
	fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
	fwspec.param[1] = IRQ_TYPE_NONE;
	return irq_create_fwspec_mapping(&fwspec);
}

static void xgene_gpio_sb_domain_activate(struct irq_domain *d,
		struct irq_data *irq_data)
{
	struct xgene_gpio_sb *priv = d->host_data;
	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);

	if (gpiochip_lock_as_irq(&priv->gc, gpio)) {
		dev_err(priv->gc.parent,
		"Unable to configure XGene GPIO standby pin %d as IRQ\n",
				gpio);
		return;
	}

	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
			gpio * 2, 1);
}

static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
		struct irq_data *irq_data)
{
	struct xgene_gpio_sb *priv = d->host_data;
	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);

	gpiochip_unlock_as_irq(&priv->gc, gpio);
	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
			gpio * 2, 0);
}

static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
		struct irq_fwspec *fwspec,
		unsigned long *hwirq,
		unsigned int *type)
{
	struct xgene_gpio_sb *priv = d->host_data;

	if ((fwspec->param_count != 2) ||
		(fwspec->param[0] >= priv->nirq))
		return -EINVAL;
	*hwirq = fwspec->param[0];
	*type = fwspec->param[1];
	return 0;
}

static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
					unsigned int virq,
					unsigned int nr_irqs, void *data)
{
	struct irq_fwspec *fwspec = data;
	struct irq_fwspec parent_fwspec;
	struct xgene_gpio_sb *priv = domain->host_data;
	irq_hw_number_t hwirq;
	unsigned int i;

	hwirq = fwspec->param[0];
	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
				&xgene_gpio_sb_irq_chip, priv);

	parent_fwspec.fwnode = domain->parent->fwnode;
	if (is_of_node(parent_fwspec.fwnode)) {
		parent_fwspec.param_count = 3;
		parent_fwspec.param[0] = 0;/* SPI */
		/* Skip SGIs and PPIs*/
		parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
		parent_fwspec.param[2] = fwspec->param[1];
	} else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
		parent_fwspec.param_count = 2;
		parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
		parent_fwspec.param[1] = fwspec->param[1];
	} else
		return -EINVAL;

	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
			&parent_fwspec);
}

static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
	.translate      = xgene_gpio_sb_domain_translate,
	.alloc          = xgene_gpio_sb_domain_alloc,
	.free           = irq_domain_free_irqs_common,
	.activate	= xgene_gpio_sb_domain_activate,
	.deactivate	= xgene_gpio_sb_domain_deactivate,
};

static int xgene_gpio_sb_probe(struct platform_device *pdev)
{
	struct xgene_gpio_sb *priv;
	int ret;
	struct resource *res;
	void __iomem *regs;
	struct irq_domain *parent_domain = NULL;
	struct fwnode_handle *fwnode;
	u32 val32;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	priv->regs = regs;

	ret = platform_get_irq(pdev, 0);
	if (ret > 0) {
		priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
		parent_domain = irq_get_irq_data(ret)->domain;
	}
	if (!parent_domain) {
		dev_err(&pdev->dev, "unable to obtain parent domain\n");
		return -ENODEV;
	}

	ret = bgpio_init(&priv->gc, &pdev->dev, 4,
			regs + MPA_GPIO_IN_ADDR,
			regs + MPA_GPIO_OUT_ADDR, NULL,
			regs + MPA_GPIO_OE_ADDR, NULL, 0);
        if (ret)
                return ret;

	priv->gc.to_irq = xgene_gpio_sb_to_irq;

	/* Retrieve start irq pin, use default if property not found */
	priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
	if (!device_property_read_u32(&pdev->dev,
					XGENE_IRQ_START_PROPERTY, &val32))
		priv->irq_start = val32;

	/* Retrieve number irqs, use default if property not found */
	priv->nirq = XGENE_DFLT_MAX_NIRQ;
	if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
		priv->nirq = val32;

	/* Retrieve number gpio, use default if property not found */
	priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
	if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
		priv->gc.ngpio = val32;

	dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
			priv->gc.ngpio, priv->nirq, priv->irq_start);

	platform_set_drvdata(pdev, priv);

	if (pdev->dev.of_node)
		fwnode = of_node_to_fwnode(pdev->dev.of_node);
	else
		fwnode = pdev->dev.fwnode;

	priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
					0, priv->nirq, fwnode,
					&xgene_gpio_sb_domain_ops, priv);
	if (!priv->irq_domain)
		return -ENODEV;

	priv->gc.irqdomain = priv->irq_domain;

	ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
	if (ret) {
		dev_err(&pdev->dev,
			"failed to register X-Gene GPIO Standby driver\n");
		irq_domain_remove(priv->irq_domain);
		return ret;
	}

	dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");

	if (priv->nirq > 0) {
		/* Register interrupt handlers for gpio signaled acpi events */
		acpi_gpiochip_request_interrupts(&priv->gc);
	}

	return ret;
}

static int xgene_gpio_sb_remove(struct platform_device *pdev)
{
	struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);

	if (priv->nirq > 0) {
		acpi_gpiochip_free_interrupts(&priv->gc);
	}

	irq_domain_remove(priv->irq_domain);

	return 0;
}

static const struct of_device_id xgene_gpio_sb_of_match[] = {
	{.compatible = "apm,xgene-gpio-sb", },
	{},
};
MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);

#ifdef CONFIG_ACPI
static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
	{"APMC0D15", 0},
	{},
};
MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
#endif

static struct platform_driver xgene_gpio_sb_driver = {
	.driver = {
		   .name = "xgene-gpio-sb",
		   .of_match_table = xgene_gpio_sb_of_match,
		   .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
		   },
	.probe = xgene_gpio_sb_probe,
	.remove = xgene_gpio_sb_remove,
};
module_platform_driver(xgene_gpio_sb_driver);

MODULE_AUTHOR("AppliedMicro");
MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b2b35e10 V	1	/*
	2	* AppliedMicro X-Gene SoC GPIO-Standby Driver
	3	*
	4	* Copyright (c) 2014, Applied Micro Circuits Corporation
1013fc41 QN	5	* Author: Tin Huynh <[email protected]>.
	6	* Y Vo <[email protected]>.
	7	* Quan Nguyen <[email protected]>.
b2b35e10 V	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/io.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/of_gpio.h>
b2b35e10	27	#include <linux/gpio/driver.h>
733cf014	28	#include <linux/acpi.h>
b2b35e10	29
733cf014 V	30	#include "gpiolib.h"
733cf014 V	31
1013fc41 QN	32	/* Common property names */
	33	#define XGENE_NIRQ_PROPERTY "apm,nr-irqs"
	34	#define XGENE_NGPIO_PROPERTY "apm,nr-gpios"
	35	#define XGENE_IRQ_START_PROPERTY "apm,irq-start"
b2b35e10	36
1013fc41 QN	37	#define XGENE_DFLT_MAX_NGPIO 22
	38	#define XGENE_DFLT_MAX_NIRQ 6
	39	#define XGENE_DFLT_IRQ_START_PIN 8
b2b35e10 V	40	#define GPIO_MASK(x) (1U << ((x) % 32))
	41
	42	#define MPA_GPIO_INT_LVL 0x0290
	43	#define MPA_GPIO_OE_ADDR 0x029c
	44	#define MPA_GPIO_OUT_ADDR 0x02a0
	45	#define MPA_GPIO_IN_ADDR 0x02a4
	46	#define MPA_GPIO_SEL_LO 0x0294
	47
1013fc41 QN	48	#define GPIO_INT_LEVEL_H 0x000001
	49	#define GPIO_INT_LEVEL_L 0x000000
	50
b2b35e10 V	51	/**
b2b35e10 V	52	* struct xgene_gpio_sb - GPIO-Standby private data structure.
0f4630f3	53	* @gc: memory-mapped GPIO controllers.
1013fc41 QN	54	* @regs: GPIO register base offset
	55	* @irq_domain: GPIO interrupt domain
	56	* @irq_start: GPIO pin that start support interrupt
	57	* @nirq: Number of GPIO pins that supports interrupt
	58	* @parent_irq_base: Start parent HWIRQ
b2b35e10 V	59	*/
b2b35e10 V	60	struct xgene_gpio_sb {
0f4630f3	61	struct gpio_chip gc;
1013fc41 QN	62	void __iomem *regs;
	63	struct irq_domain *irq_domain;
	64	u16 irq_start;
	65	u16 nirq;
	66	u16 parent_irq_base;
b2b35e10 V	67	};
b2b35e10 V	68
1013fc41 QN	69	#define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
	70	#define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
	71
	72	static void xgene_gpio_set_bit(struct gpio_chip *gc,
	73	void __iomem *reg, u32 gpio, int val)
b2b35e10 V	74	{
	75	u32 data;
	76
0f4630f3	77	data = gc->read_reg(reg);
b2b35e10 V	78	if (val)
	79	data \|= GPIO_MASK(gpio);
	80	else
	81	data &= ~GPIO_MASK(gpio);
0f4630f3	82	gc->write_reg(reg, data);
b2b35e10 V	83	}
b2b35e10 V	84
1013fc41 QN	85	static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
	86	{
	87	struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
	88	int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
	89	int lvl_type = GPIO_INT_LEVEL_H;
	90
	91	switch (type & IRQ_TYPE_SENSE_MASK) {
	92	case IRQ_TYPE_EDGE_RISING:
	93	case IRQ_TYPE_LEVEL_HIGH:
	94	lvl_type = GPIO_INT_LEVEL_H;
	95	break;
	96	case IRQ_TYPE_EDGE_FALLING:
	97	case IRQ_TYPE_LEVEL_LOW:
	98	lvl_type = GPIO_INT_LEVEL_L;
	99	break;
	100	default:
	101	break;
	102	}
	103
	104	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
	105	gpio * 2, 1);
	106	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
	107	d->hwirq, lvl_type);
	108
	109	/* Propagate IRQ type setting to parent */
	110	if (type & IRQ_TYPE_EDGE_BOTH)
	111	return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
	112	else
	113	return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
	114	}
	115
	116	static struct irq_chip xgene_gpio_sb_irq_chip = {
	117	.name = "sbgpio",
	118	.irq_eoi = irq_chip_eoi_parent,
	119	.irq_mask = irq_chip_mask_parent,
	120	.irq_unmask = irq_chip_unmask_parent,
	121	.irq_set_type = xgene_gpio_sb_irq_set_type,
	122	};
	123
	124	static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
b2b35e10	125	{
0f4630f3	126	struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
1013fc41 QN	127	struct irq_fwspec fwspec;
	128
	129	if ((gpio < priv->irq_start) \|\|
	130	(gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
	131	return -ENXIO;
	132
	133	if (gc->parent->of_node)
	134	fwspec.fwnode = of_node_to_fwnode(gc->parent->of_node);
	135	else
	136	fwspec.fwnode = gc->parent->fwnode;
	137	fwspec.param_count = 2;
	138	fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
	139	fwspec.param[1] = IRQ_TYPE_NONE;
	140	return irq_create_fwspec_mapping(&fwspec);
	141	}
	142
	143	static void xgene_gpio_sb_domain_activate(struct irq_domain *d,
	144	struct irq_data *irq_data)
	145	{
	146	struct xgene_gpio_sb *priv = d->host_data;
	147	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
	148
	149	if (gpiochip_lock_as_irq(&priv->gc, gpio)) {
	150	dev_err(priv->gc.parent,
	151	"Unable to configure XGene GPIO standby pin %d as IRQ\n",
	152	gpio);
	153	return;
	154	}
	155
	156	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
	157	gpio * 2, 1);
	158	}
	159
	160	static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
	161	struct irq_data *irq_data)
	162	{
	163	struct xgene_gpio_sb *priv = d->host_data;
	164	u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
	165
	166	gpiochip_unlock_as_irq(&priv->gc, gpio);
	167	xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
	168	gpio * 2, 0);
	169	}
	170
	171	static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
	172	struct irq_fwspec *fwspec,
	173	unsigned long *hwirq,
	174	unsigned int *type)
	175	{
	176	struct xgene_gpio_sb *priv = d->host_data;
b2b35e10	177
1013fc41 QN	178	if ((fwspec->param_count != 2) \|\|
	179	(fwspec->param[0] >= priv->nirq))
	180	return -EINVAL;
	181	*hwirq = fwspec->param[0];
	182	*type = fwspec->param[1];
	183	return 0;
	184	}
	185
	186	static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
	187	unsigned int virq,
	188	unsigned int nr_irqs, void *data)
	189	{
	190	struct irq_fwspec *fwspec = data;
	191	struct irq_fwspec parent_fwspec;
	192	struct xgene_gpio_sb *priv = domain->host_data;
	193	irq_hw_number_t hwirq;
	194	unsigned int i;
	195
	196	hwirq = fwspec->param[0];
	197	for (i = 0; i < nr_irqs; i++)
	198	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
	199	&xgene_gpio_sb_irq_chip, priv);
	200
	201	parent_fwspec.fwnode = domain->parent->fwnode;
	202	if (is_of_node(parent_fwspec.fwnode)) {
	203	parent_fwspec.param_count = 3;
	204	parent_fwspec.param[0] = 0;/* SPI */
	205	/* Skip SGIs and PPIs*/
	206	parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
	207	parent_fwspec.param[2] = fwspec->param[1];
	208	} else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
	209	parent_fwspec.param_count = 2;
	210	parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
	211	parent_fwspec.param[1] = fwspec->param[1];
	212	} else
	213	return -EINVAL;
	214
	215	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
	216	&parent_fwspec);
	217	}
	218
1013fc41 QN	219	static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
	220	.translate = xgene_gpio_sb_domain_translate,
	221	.alloc = xgene_gpio_sb_domain_alloc,
c6cc75fe	222	.free = irq_domain_free_irqs_common,
1013fc41 QN	223	.activate = xgene_gpio_sb_domain_activate,
	224	.deactivate = xgene_gpio_sb_domain_deactivate,
	225	};
	226
b2b35e10 V	227	static int xgene_gpio_sb_probe(struct platform_device *pdev)
	228	{
	229	struct xgene_gpio_sb *priv;
67ebb742	230	int ret;
b2b35e10 V	231	struct resource *res;
b2b35e10 V	232	void __iomem *regs;
1013fc41 QN	233	struct irq_domain *parent_domain = NULL;
	234	struct fwnode_handle *fwnode;
	235	u32 val32;
b2b35e10 V	236
	237	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	238	if (!priv)
	239	return -ENOMEM;
	240
	241	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	242	regs = devm_ioremap_resource(&pdev->dev, res);
33c07b46	243	if (IS_ERR(regs))
b2b35e10 V	244	return PTR_ERR(regs);
b2b35e10 V	245
1013fc41 QN	246	priv->regs = regs;
	247
	248	ret = platform_get_irq(pdev, 0);
	249	if (ret > 0) {
	250	priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
	251	parent_domain = irq_get_irq_data(ret)->domain;
	252	}
	253	if (!parent_domain) {
	254	dev_err(&pdev->dev, "unable to obtain parent domain\n");
	255	return -ENODEV;
	256	}
	257
0f4630f3	258	ret = bgpio_init(&priv->gc, &pdev->dev, 4,
b2b35e10 V	259	regs + MPA_GPIO_IN_ADDR,
	260	regs + MPA_GPIO_OUT_ADDR, NULL,
	261	regs + MPA_GPIO_OE_ADDR, NULL, 0);
	262	if (ret)
	263	return ret;
	264
1013fc41	265	priv->gc.to_irq = xgene_gpio_sb_to_irq;
b2b35e10	266
1013fc41 QN	267	/* Retrieve start irq pin, use default if property not found */
	268	priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
	269	if (!device_property_read_u32(&pdev->dev,
	270	XGENE_IRQ_START_PROPERTY, &val32))
	271	priv->irq_start = val32;
b2b35e10	272
1013fc41 QN	273	/* Retrieve number irqs, use default if property not found */
	274	priv->nirq = XGENE_DFLT_MAX_NIRQ;
	275	if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
	276	priv->nirq = val32;
b2b35e10	277
1013fc41 QN	278	/* Retrieve number gpio, use default if property not found */
	279	priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
	280	if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
	281	priv->gc.ngpio = val32;
	282
	283	dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
	284	priv->gc.ngpio, priv->nirq, priv->irq_start);
b2b35e10 V	285
	286	platform_set_drvdata(pdev, priv);
	287
1013fc41 QN	288	if (pdev->dev.of_node)
1013fc41 QN	289	fwnode = of_node_to_fwnode(pdev->dev.of_node);
b2b35e10	290	else
1013fc41 QN	291	fwnode = pdev->dev.fwnode;
	292
	293	priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
	294	0, priv->nirq, fwnode,
	295	&xgene_gpio_sb_domain_ops, priv);
	296	if (!priv->irq_domain)
	297	return -ENODEV;
	298
	299	priv->gc.irqdomain = priv->irq_domain;
	300
29862059	301	ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
1013fc41 QN	302	if (ret) {
	303	dev_err(&pdev->dev,
	304	"failed to register X-Gene GPIO Standby driver\n");
	305	irq_domain_remove(priv->irq_domain);
	306	return ret;
	307	}
	308
	309	dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
b2b35e10	310
733cf014 V	311	if (priv->nirq > 0) {
733cf014 V	312	/* Register interrupt handlers for gpio signaled acpi events */
0f4630f3	313	acpi_gpiochip_request_interrupts(&priv->gc);
733cf014 V	314	}
733cf014 V	315
b2b35e10 V	316	return ret;
	317	}
	318
	319	static int xgene_gpio_sb_remove(struct platform_device *pdev)
	320	{
	321	struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
	322
733cf014	323	if (priv->nirq > 0) {
0f4630f3	324	acpi_gpiochip_free_interrupts(&priv->gc);
733cf014 V	325	}
733cf014 V	326
1013fc41 QN	327	irq_domain_remove(priv->irq_domain);
1013fc41 QN	328
0f4630f3	329	return 0;
b2b35e10 V	330	}
	331
	332	static const struct of_device_id xgene_gpio_sb_of_match[] = {
	333	{.compatible = "apm,xgene-gpio-sb", },
	334	{},
	335	};
	336	MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
	337
733cf014 V	338	#ifdef CONFIG_ACPI
	339	static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
	340	{"APMC0D15", 0},
	341	{},
	342	};
	343	MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
	344	#endif
	345
b2b35e10 V	346	static struct platform_driver xgene_gpio_sb_driver = {
	347	.driver = {
	348	.name = "xgene-gpio-sb",
	349	.of_match_table = xgene_gpio_sb_of_match,
733cf014	350	.acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
b2b35e10 V	351	},
	352	.probe = xgene_gpio_sb_probe,
	353	.remove = xgene_gpio_sb_remove,
	354	};
	355	module_platform_driver(xgene_gpio_sb_driver);
	356
	357	MODULE_AUTHOR("AppliedMicro");
	358	MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
	359	MODULE_LICENSE("GPL");