[linux.git] / drivers / gpio / gpio-timberdale.c

/*
 * Timberdale FPGA GPIO driver
 * Author: Mocean Laboratories
 * Copyright (c) 2009 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Timberdale FPGA GPIO
 */

#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/timb_gpio.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#define DRIVER_NAME "timb-gpio"

#define TGPIOVAL	0x00
#define TGPIODIR	0x04
#define TGPIO_IER	0x08
#define TGPIO_ISR	0x0c
#define TGPIO_IPR	0x10
#define TGPIO_ICR	0x14
#define TGPIO_FLR	0x18
#define TGPIO_LVR	0x1c
#define TGPIO_VER	0x20
#define TGPIO_BFLR	0x24

struct timbgpio {
	void __iomem		*membase;
	spinlock_t		lock; /* mutual exclusion */
	struct gpio_chip	gpio;
	int			irq_base;
	unsigned long		last_ier;
};

static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	unsigned offset, bool enabled)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);
	u32 reg;

	spin_lock(&tgpio->lock);
	reg = ioread32(tgpio->membase + offset);

	if (enabled)
		reg |= (1 << index);
	else
		reg &= ~(1 << index);

	iowrite32(reg, tgpio->membase + offset);
	spin_unlock(&tgpio->lock);

	return 0;
}

static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
}

static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);
	u32 value;

	value = ioread32(tgpio->membase + TGPIOVAL);
	return (value & (1 << nr)) ? 1 : 0;
}

static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
						unsigned nr, int val)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
}

static void timbgpio_gpio_set(struct gpio_chip *gpio,
				unsigned nr, int val)
{
	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
}

static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);

	if (tgpio->irq_base <= 0)
		return -EINVAL;

	return tgpio->irq_base + offset;
}

/*
 * GPIO IRQ
 */
static void timbgpio_irq_disable(struct irq_data *d)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;

	spin_lock_irqsave(&tgpio->lock, flags);
	tgpio->last_ier &= ~(1UL << offset);
	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
	spin_unlock_irqrestore(&tgpio->lock, flags);
}

static void timbgpio_irq_enable(struct irq_data *d)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;

	spin_lock_irqsave(&tgpio->lock, flags);
	tgpio->last_ier |= 1UL << offset;
	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
	spin_unlock_irqrestore(&tgpio->lock, flags);
}

static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;
	u32 lvr, flr, bflr = 0;
	u32 ver;
	int ret = 0;

	if (offset < 0 || offset > tgpio->gpio.ngpio)
		return -EINVAL;

	ver = ioread32(tgpio->membase + TGPIO_VER);

	spin_lock_irqsave(&tgpio->lock, flags);

	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	flr = ioread32(tgpio->membase + TGPIO_FLR);
	if (ver > 2)
		bflr = ioread32(tgpio->membase + TGPIO_BFLR);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bflr &= ~(1 << offset);
		flr &= ~(1 << offset);
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			lvr |= 1 << offset;
		else
			lvr &= ~(1 << offset);
	}

	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		if (ver < 3) {
			ret = -EINVAL;
			goto out;
		} else {
			flr |= 1 << offset;
			bflr |= 1 << offset;
		}
	} else {
		bflr &= ~(1 << offset);
		flr |= 1 << offset;
		if (trigger & IRQ_TYPE_EDGE_FALLING)
			lvr &= ~(1 << offset);
		else
			lvr |= 1 << offset;
	}

	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	iowrite32(flr, tgpio->membase + TGPIO_FLR);
	if (ver > 2)
		iowrite32(bflr, tgpio->membase + TGPIO_BFLR);

	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);

out:
	spin_unlock_irqrestore(&tgpio->lock, flags);
	return ret;
}

static void timbgpio_irq(struct irq_desc *desc)
{
	struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
	struct irq_data *data = irq_desc_get_irq_data(desc);
	unsigned long ipr;
	int offset;

	data->chip->irq_ack(data);
	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	iowrite32(ipr, tgpio->membase + TGPIO_ICR);

	/*
	 * Some versions of the hardware trash the IER register if more than
	 * one interrupt is received simultaneously.
	 */
	iowrite32(0, tgpio->membase + TGPIO_IER);

	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
		generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));

	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
}

static struct irq_chip timbgpio_irqchip = {
	.name		= "GPIO",
	.irq_enable	= timbgpio_irq_enable,
	.irq_disable	= timbgpio_irq_disable,
	.irq_set_type	= timbgpio_irq_type,
};

static int timbgpio_probe(struct platform_device *pdev)
{
	int err, i;
	struct device *dev = &pdev->dev;
	struct gpio_chip *gc;
	struct timbgpio *tgpio;
	struct resource *iomem;
	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	int irq = platform_get_irq(pdev, 0);

	if (!pdata || pdata->nr_pins > 32) {
		dev_err(dev, "Invalid platform data\n");
		return -EINVAL;
	}

	tgpio = devm_kzalloc(dev, sizeof(struct timbgpio), GFP_KERNEL);
	if (!tgpio) {
		dev_err(dev, "Memory alloc failed\n");
		return -EINVAL;
	}
	tgpio->irq_base = pdata->irq_base;

	spin_lock_init(&tgpio->lock);

	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tgpio->membase = devm_ioremap_resource(dev, iomem);
	if (IS_ERR(tgpio->membase))
		return PTR_ERR(tgpio->membase);

	gc = &tgpio->gpio;

	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->parent = &pdev->dev;
	gc->direction_input = timbgpio_gpio_direction_input;
	gc->get = timbgpio_gpio_get;
	gc->direction_output = timbgpio_gpio_direction_output;
	gc->set = timbgpio_gpio_set;
	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	gc->dbg_show = NULL;
	gc->base = pdata->gpio_base;
	gc->ngpio = pdata->nr_pins;
	gc->can_sleep = false;

	err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
	if (err)
		return err;

	platform_set_drvdata(pdev, tgpio);

	/* make sure to disable interrupts */
	iowrite32(0x0, tgpio->membase + TGPIO_IER);

	if (irq < 0 || tgpio->irq_base <= 0)
		return 0;

	for (i = 0; i < pdata->nr_pins; i++) {
		irq_set_chip_and_handler(tgpio->irq_base + i,
			&timbgpio_irqchip, handle_simple_irq);
		irq_set_chip_data(tgpio->irq_base + i, tgpio);
		irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
	}

	irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);

	return 0;
}

static struct platform_driver timbgpio_platform_driver = {
	.driver = {
		.name			= DRIVER_NAME,
		.suppress_bind_attrs	= true,
	},
	.probe		= timbgpio_probe,
};

/*--------------------------------------------------------------------------*/

builtin_platform_driver(timbgpio_platform_driver);
Commit	Line	Data
35570ac6	1	/*
c103de24	2	* Timberdale FPGA GPIO driver
52ad9053	3	* Author: Mocean Laboratories
35570ac6 RR	4	* Copyright (c) 2009 Intel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
	20	/* Supports:
	21	* Timberdale FPGA GPIO
	22	*/
	23
52ad9053	24	#include <linux/init.h>
35570ac6 RR	25	#include <linux/gpio.h>
35570ac6 RR	26	#include <linux/platform_device.h>
e3cb91ce	27	#include <linux/irq.h>
35570ac6 RR	28	#include <linux/io.h>
	29	#include <linux/timb_gpio.h>
	30	#include <linux/interrupt.h>
5a0e3ad6	31	#include <linux/slab.h>
35570ac6 RR	32
	33	#define DRIVER_NAME "timb-gpio"
	34
	35	#define TGPIOVAL 0x00
	36	#define TGPIODIR 0x04
	37	#define TGPIO_IER 0x08
	38	#define TGPIO_ISR 0x0c
	39	#define TGPIO_IPR 0x10
	40	#define TGPIO_ICR 0x14
	41	#define TGPIO_FLR 0x18
	42	#define TGPIO_LVR 0x1c
8c35c89a RR	43	#define TGPIO_VER 0x20
8c35c89a RR	44	#define TGPIO_BFLR 0x24
35570ac6 RR	45
	46	struct timbgpio {
	47	void __iomem *membase;
	48	spinlock_t lock; /* mutual exclusion */
	49	struct gpio_chip gpio;
	50	int irq_base;
76d800a5	51	unsigned long last_ier;
35570ac6 RR	52	};
	53
	54	static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	55	unsigned offset, bool enabled)
	56	{
92a41e2f	57	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	58	u32 reg;
	59
	60	spin_lock(&tgpio->lock);
	61	reg = ioread32(tgpio->membase + offset);
	62
	63	if (enabled)
	64	reg \|= (1 << index);
	65	else
	66	reg &= ~(1 << index);
	67
	68	iowrite32(reg, tgpio->membase + offset);
	69	spin_unlock(&tgpio->lock);
	70
	71	return 0;
	72	}
	73
	74	static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	75	{
	76	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
	77	}
	78
	79	static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
	80	{
92a41e2f	81	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	82	u32 value;
	83
	84	value = ioread32(tgpio->membase + TGPIOVAL);
	85	return (value & (1 << nr)) ? 1 : 0;
	86	}
	87
	88	static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
	89	unsigned nr, int val)
	90	{
	91	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
	92	}
	93
	94	static void timbgpio_gpio_set(struct gpio_chip *gpio,
	95	unsigned nr, int val)
	96	{
	97	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
	98	}
	99
	100	static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	101	{
92a41e2f	102	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	103
	104	if (tgpio->irq_base <= 0)
	105	return -EINVAL;
	106
	107	return tgpio->irq_base + offset;
	108	}
	109
	110	/*
	111	* GPIO IRQ
	112	*/
a1f5f22a	113	static void timbgpio_irq_disable(struct irq_data *d)
35570ac6	114	{
a1f5f22a LB	115	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	116	int offset = d->irq - tgpio->irq_base;
76d800a5	117	unsigned long flags;
35570ac6	118
76d800a5	119	spin_lock_irqsave(&tgpio->lock, flags);
d79550a7	120	tgpio->last_ier &= ~(1UL << offset);
76d800a5 TH	121	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
76d800a5 TH	122	spin_unlock_irqrestore(&tgpio->lock, flags);
35570ac6 RR	123	}
35570ac6 RR	124
a1f5f22a	125	static void timbgpio_irq_enable(struct irq_data *d)
35570ac6	126	{
a1f5f22a LB	127	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	128	int offset = d->irq - tgpio->irq_base;
76d800a5	129	unsigned long flags;
35570ac6	130
76d800a5	131	spin_lock_irqsave(&tgpio->lock, flags);
d79550a7	132	tgpio->last_ier \|= 1UL << offset;
76d800a5 TH	133	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
76d800a5 TH	134	spin_unlock_irqrestore(&tgpio->lock, flags);
35570ac6 RR	135	}
35570ac6 RR	136
a1f5f22a	137	static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
35570ac6	138	{
a1f5f22a LB	139	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	140	int offset = d->irq - tgpio->irq_base;
35570ac6	141	unsigned long flags;
8c35c89a RR	142	u32 lvr, flr, bflr = 0;
8c35c89a RR	143	u32 ver;
2a481800	144	int ret = 0;
35570ac6 RR	145
	146	if (offset < 0 \|\| offset > tgpio->gpio.ngpio)
	147	return -EINVAL;
	148
8c35c89a RR	149	ver = ioread32(tgpio->membase + TGPIO_VER);
8c35c89a RR	150
35570ac6 RR	151	spin_lock_irqsave(&tgpio->lock, flags);
	152
	153	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	154	flr = ioread32(tgpio->membase + TGPIO_FLR);
8c35c89a RR	155	if (ver > 2)
8c35c89a RR	156	bflr = ioread32(tgpio->membase + TGPIO_BFLR);
35570ac6 RR	157
35570ac6 RR	158	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
8c35c89a	159	bflr &= ~(1 << offset);
35570ac6 RR	160	flr &= ~(1 << offset);
	161	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	162	lvr \|= 1 << offset;
	163	else
	164	lvr &= ~(1 << offset);
	165	}
	166
8c35c89a	167	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
2a481800 JL	168	if (ver < 3) {
	169	ret = -EINVAL;
	170	goto out;
8a29a409	171	} else {
8c35c89a RR	172	flr \|= 1 << offset;
	173	bflr \|= 1 << offset;
	174	}
	175	} else {
	176	bflr &= ~(1 << offset);
35570ac6	177	flr \|= 1 << offset;
35570ac6	178	if (trigger & IRQ_TYPE_EDGE_FALLING)
35570ac6	179	lvr &= ~(1 << offset);
8c35c89a RR	180	else
8c35c89a RR	181	lvr \|= 1 << offset;
35570ac6 RR	182	}
	183
	184	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	185	iowrite32(flr, tgpio->membase + TGPIO_FLR);
8c35c89a RR	186	if (ver > 2)
	187	iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
	188
35570ac6	189	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
35570ac6	190
2a481800 JL	191	out:
	192	spin_unlock_irqrestore(&tgpio->lock, flags);
	193	return ret;
35570ac6 RR	194	}
35570ac6 RR	195
bd0b9ac4	196	static void timbgpio_irq(struct irq_desc *desc)
35570ac6	197	{
476f8b4c JL	198	struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
476f8b4c JL	199	struct irq_data *data = irq_desc_get_irq_data(desc);
35570ac6 RR	200	unsigned long ipr;
	201	int offset;
	202
476f8b4c	203	data->chip->irq_ack(data);
35570ac6 RR	204	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	205	iowrite32(ipr, tgpio->membase + TGPIO_ICR);
	206
76d800a5 TH	207	/*
	208	* Some versions of the hardware trash the IER register if more than
	209	* one interrupt is received simultaneously.
	210	*/
	211	iowrite32(0, tgpio->membase + TGPIO_IER);
	212
984b3f57	213	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
35570ac6	214	generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
76d800a5 TH	215
76d800a5 TH	216	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
35570ac6 RR	217	}
	218
	219	static struct irq_chip timbgpio_irqchip = {
	220	.name = "GPIO",
a1f5f22a LB	221	.irq_enable = timbgpio_irq_enable,
	222	.irq_disable = timbgpio_irq_disable,
	223	.irq_set_type = timbgpio_irq_type,
35570ac6 RR	224	};
35570ac6 RR	225
3836309d	226	static int timbgpio_probe(struct platform_device *pdev)
35570ac6 RR	227	{
35570ac6 RR	228	int err, i;
0ed3398e	229	struct device *dev = &pdev->dev;
35570ac6 RR	230	struct gpio_chip *gc;
	231	struct timbgpio *tgpio;
	232	struct resource *iomem;
e56aee18	233	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
35570ac6 RR	234	int irq = platform_get_irq(pdev, 0);
	235
	236	if (!pdata \|\| pdata->nr_pins > 32) {
0ed3398e	237	dev_err(dev, "Invalid platform data\n");
0ed3398e	238	return -EINVAL;
35570ac6 RR	239	}
35570ac6 RR	240
0ed3398e	241	tgpio = devm_kzalloc(dev, sizeof(struct timbgpio), GFP_KERNEL);
35570ac6	242	if (!tgpio) {
0ed3398e	243	dev_err(dev, "Memory alloc failed\n");
0ed3398e	244	return -EINVAL;
35570ac6 RR	245	}
	246	tgpio->irq_base = pdata->irq_base;
	247
	248	spin_lock_init(&tgpio->lock);
	249
fa283db7 AKC	250	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	251	tgpio->membase = devm_ioremap_resource(dev, iomem);
	252	if (IS_ERR(tgpio->membase))
	253	return PTR_ERR(tgpio->membase);
35570ac6 RR	254
	255	gc = &tgpio->gpio;
	256
	257	gc->label = dev_name(&pdev->dev);
	258	gc->owner = THIS_MODULE;
58383c78	259	gc->parent = &pdev->dev;
35570ac6 RR	260	gc->direction_input = timbgpio_gpio_direction_input;
	261	gc->get = timbgpio_gpio_get;
	262	gc->direction_output = timbgpio_gpio_direction_output;
	263	gc->set = timbgpio_gpio_set;
	264	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	265	gc->dbg_show = NULL;
	266	gc->base = pdata->gpio_base;
	267	gc->ngpio = pdata->nr_pins;
9fb1f39e	268	gc->can_sleep = false;
35570ac6	269
43fad832	270	err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
35570ac6	271	if (err)
0ed3398e	272	return err;
35570ac6 RR	273
	274	platform_set_drvdata(pdev, tgpio);
	275
	276	/* make sure to disable interrupts */
	277	iowrite32(0x0, tgpio->membase + TGPIO_IER);
	278
	279	if (irq < 0 \|\| tgpio->irq_base <= 0)
	280	return 0;
	281
	282	for (i = 0; i < pdata->nr_pins; i++) {
e5428a68 LW	283	irq_set_chip_and_handler(tgpio->irq_base + i,
e5428a68 LW	284	&timbgpio_irqchip, handle_simple_irq);
b51804bc	285	irq_set_chip_data(tgpio->irq_base + i, tgpio);
23393d49	286	irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST \| IRQ_NOPROBE);
35570ac6 RR	287	}
35570ac6 RR	288
8a52211a	289	irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
35570ac6 RR	290
35570ac6 RR	291	return 0;
35570ac6 RR	292	}
35570ac6 RR	293
35570ac6 RR	294	static struct platform_driver timbgpio_platform_driver = {
35570ac6 RR	295	.driver = {
52ad9053 PG	296	.name = DRIVER_NAME,
52ad9053 PG	297	.suppress_bind_attrs = true,
35570ac6 RR	298	},
35570ac6 RR	299	.probe = timbgpio_probe,
35570ac6 RR	300	};
	301
	302	/--------------------------------------------------------------------------/
	303
52ad9053	304	builtin_platform_driver(timbgpio_platform_driver);