[linux.git] / drivers / gpio / gpio-sta2x11.c

/*
 * STMicroelectronics ConneXt (STA2X11) GPIO driver
 *
 * Copyright 2012 ST Microelectronics (Alessandro Rubini)
 * Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
 * Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/mfd/sta2x11-mfd.h>

struct gsta_regs {
	u32 dat;		/* 0x00 */
	u32 dats;
	u32 datc;
	u32 pdis;
	u32 dir;		/* 0x10 */
	u32 dirs;
	u32 dirc;
	u32 unused_1c;
	u32 afsela;		/* 0x20 */
	u32 unused_24[7];
	u32 rimsc;		/* 0x40 */
	u32 fimsc;
	u32 is;
	u32 ic;
};

struct gsta_gpio {
	spinlock_t			lock;
	struct device			*dev;
	void __iomem			*reg_base;
	struct gsta_regs __iomem	*regs[GSTA_NR_BLOCKS];
	struct gpio_chip		gpio;
	int				irq_base;
	/* FIXME: save the whole config here (AF, ...) */
	unsigned			irq_type[GSTA_NR_GPIO];
};

static inline struct gsta_regs __iomem *__regs(struct gsta_gpio *chip, int nr)
{
	return chip->regs[nr / GSTA_GPIO_PER_BLOCK];
}

static inline u32 __bit(int nr)
{
	return 1U << (nr % GSTA_GPIO_PER_BLOCK);
}

/*
 * gpio methods
 */

static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	struct gsta_regs __iomem *regs = __regs(chip, nr);
	u32 bit = __bit(nr);

	if (val)
		writel(bit, &regs->dats);
	else
		writel(bit, &regs->datc);
}

static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	struct gsta_regs __iomem *regs = __regs(chip, nr);
	u32 bit = __bit(nr);

	return !!(readl(&regs->dat) & bit);
}

static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
				      int val)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	struct gsta_regs __iomem *regs = __regs(chip, nr);
	u32 bit = __bit(nr);

	writel(bit, &regs->dirs);
	/* Data register after direction, otherwise pullup/down is selected */
	if (val)
		writel(bit, &regs->dats);
	else
		writel(bit, &regs->datc);
	return 0;
}

static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	struct gsta_regs __iomem *regs = __regs(chip, nr);
	u32 bit = __bit(nr);

	writel(bit, &regs->dirc);
	return 0;
}

static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	return chip->irq_base + offset;
}

static void gsta_gpio_setup(struct gsta_gpio *chip) /* called from probe */
{
	struct gpio_chip *gpio = &chip->gpio;

	/*
	 * ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
	 * from the end. However, for compatibility, we need the first
	 * ConneXt device to start from gpio 0: it's the main chipset
	 * on most boards so documents and drivers assume gpio0..gpio127
	 */
	static int gpio_base;

	gpio->label = dev_name(chip->dev);
	gpio->owner = THIS_MODULE;
	gpio->direction_input = gsta_gpio_direction_input;
	gpio->get = gsta_gpio_get;
	gpio->direction_output = gsta_gpio_direction_output;
	gpio->set = gsta_gpio_set;
	gpio->dbg_show = NULL;
	gpio->base = gpio_base;
	gpio->ngpio = GSTA_NR_GPIO;
	gpio->can_sleep = false;
	gpio->to_irq = gsta_gpio_to_irq;

	/*
	 * After the first device, turn to dynamic gpio numbers.
	 * For example, with ARCH_NR_GPIOS = 256 we can fit two cards
	 */
	if (!gpio_base)
		gpio_base = -1;
}

/*
 * Special method: alternate functions and pullup/pulldown. This is only
 * invoked on startup to configure gpio's according to platform data.
 * FIXME : this functionality shall be managed (and exported to other drivers)
 * via the pin control subsystem.
 */
static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
{
	struct gsta_regs __iomem *regs = __regs(chip, nr);
	unsigned long flags;
	u32 bit = __bit(nr);
	u32 val;
	int err = 0;

	pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);

	if (cfg == PINMUX_TYPE_NONE)
		return;

	/* Alternate function or not? */
	spin_lock_irqsave(&chip->lock, flags);
	val = readl(&regs->afsela);
	if (cfg == PINMUX_TYPE_FUNCTION)
		val |= bit;
	else
		val &= ~bit;
	writel(val | bit, &regs->afsela);
	if (cfg == PINMUX_TYPE_FUNCTION) {
		spin_unlock_irqrestore(&chip->lock, flags);
		return;
	}

	/* not alternate function: set details */
	switch (cfg) {
	case PINMUX_TYPE_OUTPUT_LOW:
		writel(bit, &regs->dirs);
		writel(bit, &regs->datc);
		break;
	case PINMUX_TYPE_OUTPUT_HIGH:
		writel(bit, &regs->dirs);
		writel(bit, &regs->dats);
		break;
	case PINMUX_TYPE_INPUT:
		writel(bit, &regs->dirc);
		val = readl(&regs->pdis) | bit;
		writel(val, &regs->pdis);
		break;
	case PINMUX_TYPE_INPUT_PULLUP:
		writel(bit, &regs->dirc);
		val = readl(&regs->pdis) & ~bit;
		writel(val, &regs->pdis);
		writel(bit, &regs->dats);
		break;
	case PINMUX_TYPE_INPUT_PULLDOWN:
		writel(bit, &regs->dirc);
		val = readl(&regs->pdis) & ~bit;
		writel(val, &regs->pdis);
		writel(bit, &regs->datc);
		break;
	default:
		err = 1;
	}
	spin_unlock_irqrestore(&chip->lock, flags);
	if (err)
		pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
		       __func__, chip, nr, cfg);
}

/*
 * Irq methods
 */

static void gsta_irq_disable(struct irq_data *data)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	struct gsta_gpio *chip = gc->private;
	int nr = data->irq - chip->irq_base;
	struct gsta_regs __iomem *regs = __regs(chip, nr);
	u32 bit = __bit(nr);
	u32 val;
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);
	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
		val = readl(&regs->rimsc) & ~bit;
		writel(val, &regs->rimsc);
	}
	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
		val = readl(&regs->fimsc) & ~bit;
		writel(val, &regs->fimsc);
	}
	spin_unlock_irqrestore(&chip->lock, flags);
	return;
}

static void gsta_irq_enable(struct irq_data *data)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	struct gsta_gpio *chip = gc->private;
	int nr = data->irq - chip->irq_base;
	struct gsta_regs __iomem *regs = __regs(chip, nr);
	u32 bit = __bit(nr);
	u32 val;
	int type;
	unsigned long flags;

	type = chip->irq_type[nr];

	spin_lock_irqsave(&chip->lock, flags);
	val = readl(&regs->rimsc);
	if (type & IRQ_TYPE_EDGE_RISING)
		writel(val | bit, &regs->rimsc);
	else
		writel(val & ~bit, &regs->rimsc);
	val = readl(&regs->rimsc);
	if (type & IRQ_TYPE_EDGE_FALLING)
		writel(val | bit, &regs->fimsc);
	else
		writel(val & ~bit, &regs->fimsc);
	spin_unlock_irqrestore(&chip->lock, flags);
	return;
}

static int gsta_irq_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct gsta_gpio *chip = gc->private;
	int nr = d->irq - chip->irq_base;

	/* We only support edge interrupts */
	if (!(type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) {
		pr_debug("%s: unsupported type 0x%x\n", __func__, type);
		return -EINVAL;
	}

	chip->irq_type[nr] = type; /* used for enable/disable */

	gsta_irq_enable(d);
	return 0;
}

static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
{
	struct gsta_gpio *chip = dev_id;
	struct gsta_regs __iomem *regs;
	u32 is;
	int i, nr, base;
	irqreturn_t ret = IRQ_NONE;

	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
		regs = chip->regs[i];
		base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
		while ((is = readl(&regs->is))) {
			nr = __ffs(is);
			irq = base + nr;
			generic_handle_irq(irq);
			writel(1 << nr, &regs->ic);
			ret = IRQ_HANDLED;
		}
	}
	return ret;
}

static void gsta_alloc_irq_chip(struct gsta_gpio *chip)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip(KBUILD_MODNAME, 1, chip->irq_base,
				     chip->reg_base, handle_simple_irq);
	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_set_type = gsta_irq_type;
	ct->chip.irq_disable = gsta_irq_disable;
	ct->chip.irq_enable = gsta_irq_enable;

	/* FIXME: this makes at most 32 interrupts. Request 0 by now */
	irq_setup_generic_chip(gc, 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */, 0,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);

	/* Set up all all 128 interrupts: code from setup_generic_chip */
	{
		struct irq_chip_type *ct = gc->chip_types;
		int i, j;
		for (j = 0; j < GSTA_NR_GPIO; j++) {
			i = chip->irq_base + j;
			irq_set_chip_and_handler(i, &ct->chip, ct->handler);
			irq_set_chip_data(i, gc);
			irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
		}
		gc->irq_cnt = i - gc->irq_base;
	}
}

/* The platform device used here is instantiated by the MFD device */
static int gsta_probe(struct platform_device *dev)
{
	int i, err;
	struct pci_dev *pdev;
	struct sta2x11_gpio_pdata *gpio_pdata;
	struct gsta_gpio *chip;
	struct resource *res;

	pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
	gpio_pdata = dev_get_platdata(&pdev->dev);

	if (gpio_pdata == NULL)
		dev_err(&dev->dev, "no gpio config\n");
	pr_debug("gpio config: %p\n", gpio_pdata);

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);

	chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;
	chip->dev = &dev->dev;
	chip->reg_base = devm_ioremap_resource(&dev->dev, res);
	if (IS_ERR(chip->reg_base))
		return PTR_ERR(chip->reg_base);

	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
		chip->regs[i] = chip->reg_base + i * 4096;
		/* disable all irqs */
		writel(0, &chip->regs[i]->rimsc);
		writel(0, &chip->regs[i]->fimsc);
		writel(~0, &chip->regs[i]->ic);
	}
	spin_lock_init(&chip->lock);
	gsta_gpio_setup(chip);
	if (gpio_pdata)
		for (i = 0; i < GSTA_NR_GPIO; i++)
			gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);

	/* 384 was used in previous code: be compatible for other drivers */
	err = irq_alloc_descs(-1, 384, GSTA_NR_GPIO, NUMA_NO_NODE);
	if (err < 0) {
		dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
			 -err);
		return err;
	}
	chip->irq_base = err;
	gsta_alloc_irq_chip(chip);

	err = request_irq(pdev->irq, gsta_gpio_handler,
			     IRQF_SHARED, KBUILD_MODNAME, chip);
	if (err < 0) {
		dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
			-err);
		goto err_free_descs;
	}

	err = devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip);
	if (err < 0) {
		dev_err(&dev->dev, "sta2x11 gpio: Can't register (%i)\n",
			-err);
		goto err_free_irq;
	}

	platform_set_drvdata(dev, chip);
	return 0;

err_free_irq:
	free_irq(pdev->irq, chip);
err_free_descs:
	irq_free_descs(chip->irq_base, GSTA_NR_GPIO);
	return err;
}

static struct platform_driver sta2x11_gpio_platform_driver = {
	.driver = {
		.name	= "sta2x11-gpio",
	},
	.probe = gsta_probe,
};
builtin_platform_driver(sta2x11_gpio_platform_driver);
Commit	Line	Data
7b0d44f3 AR	1	/*
	2	* STMicroelectronics ConneXt (STA2X11) GPIO driver
	3	*
	4	* Copyright 2012 ST Microelectronics (Alessandro Rubini)
	5	* Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
	6	* Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	15	* See the GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*
	21	*/
	22
3c90c6d6	23	#include <linux/init.h>
7b0d44f3 AR	24	#include <linux/kernel.h>
	25	#include <linux/slab.h>
	26	#include <linux/gpio.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/irq.h>
	29	#include <linux/pci.h>
	30	#include <linux/platform_device.h>
	31	#include <linux/mfd/sta2x11-mfd.h>
	32
	33	struct gsta_regs {
	34	u32 dat; /* 0x00 */
	35	u32 dats;
	36	u32 datc;
	37	u32 pdis;
	38	u32 dir; /* 0x10 */
	39	u32 dirs;
	40	u32 dirc;
	41	u32 unused_1c;
	42	u32 afsela; /* 0x20 */
	43	u32 unused_24[7];
	44	u32 rimsc; /* 0x40 */
	45	u32 fimsc;
	46	u32 is;
	47	u32 ic;
	48	};
	49
	50	struct gsta_gpio {
	51	spinlock_t lock;
	52	struct device *dev;
	53	void __iomem *reg_base;
	54	struct gsta_regs __iomem *regs[GSTA_NR_BLOCKS];
	55	struct gpio_chip gpio;
	56	int irq_base;
	57	/* FIXME: save the whole config here (AF, ...) */
	58	unsigned irq_type[GSTA_NR_GPIO];
	59	};
	60
	61	static inline struct gsta_regs __iomem __regs(struct gsta_gpio chip, int nr)
	62	{
	63	return chip->regs[nr / GSTA_GPIO_PER_BLOCK];
	64	}
	65
	66	static inline u32 __bit(int nr)
	67	{
	68	return 1U << (nr % GSTA_GPIO_PER_BLOCK);
	69	}
	70
	71	/*
	72	* gpio methods
	73	*/
	74
	75	static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
	76	{
0b2c529a	77	struct gsta_gpio *chip = gpiochip_get_data(gpio);
7b0d44f3 AR	78	struct gsta_regs __iomem *regs = __regs(chip, nr);
	79	u32 bit = __bit(nr);
	80
	81	if (val)
	82	writel(bit, &regs->dats);
	83	else
	84	writel(bit, &regs->datc);
	85	}
	86
	87	static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
	88	{
0b2c529a	89	struct gsta_gpio *chip = gpiochip_get_data(gpio);
7b0d44f3 AR	90	struct gsta_regs __iomem *regs = __regs(chip, nr);
	91	u32 bit = __bit(nr);
	92
8a240c31	93	return !!(readl(&regs->dat) & bit);
7b0d44f3 AR	94	}
	95
	96	static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	97	int val)
	98	{
0b2c529a	99	struct gsta_gpio *chip = gpiochip_get_data(gpio);
7b0d44f3 AR	100	struct gsta_regs __iomem *regs = __regs(chip, nr);
	101	u32 bit = __bit(nr);
	102
	103	writel(bit, &regs->dirs);
	104	/* Data register after direction, otherwise pullup/down is selected */
	105	if (val)
	106	writel(bit, &regs->dats);
	107	else
	108	writel(bit, &regs->datc);
	109	return 0;
	110	}
	111
	112	static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	113	{
0b2c529a	114	struct gsta_gpio *chip = gpiochip_get_data(gpio);
7b0d44f3 AR	115	struct gsta_regs __iomem *regs = __regs(chip, nr);
	116	u32 bit = __bit(nr);
	117
	118	writel(bit, &regs->dirc);
	119	return 0;
	120	}
	121
	122	static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	123	{
0b2c529a	124	struct gsta_gpio *chip = gpiochip_get_data(gpio);
7b0d44f3 AR	125	return chip->irq_base + offset;
	126	}
	127
	128	static void gsta_gpio_setup(struct gsta_gpio chip) / called from probe */
	129	{
	130	struct gpio_chip *gpio = &chip->gpio;
	131
	132	/*
	133	* ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
	134	* from the end. However, for compatibility, we need the first
	135	* ConneXt device to start from gpio 0: it's the main chipset
	136	* on most boards so documents and drivers assume gpio0..gpio127
	137	*/
	138	static int gpio_base;
	139
	140	gpio->label = dev_name(chip->dev);
	141	gpio->owner = THIS_MODULE;
	142	gpio->direction_input = gsta_gpio_direction_input;
	143	gpio->get = gsta_gpio_get;
	144	gpio->direction_output = gsta_gpio_direction_output;
	145	gpio->set = gsta_gpio_set;
	146	gpio->dbg_show = NULL;
	147	gpio->base = gpio_base;
	148	gpio->ngpio = GSTA_NR_GPIO;
9fb1f39e	149	gpio->can_sleep = false;
7b0d44f3 AR	150	gpio->to_irq = gsta_gpio_to_irq;
	151
	152	/*
	153	* After the first device, turn to dynamic gpio numbers.
	154	* For example, with ARCH_NR_GPIOS = 256 we can fit two cards
	155	*/
	156	if (!gpio_base)
	157	gpio_base = -1;
	158	}
	159
	160	/*
	161	* Special method: alternate functions and pullup/pulldown. This is only
	162	* invoked on startup to configure gpio's according to platform data.
	163	* FIXME : this functionality shall be managed (and exported to other drivers)
	164	* via the pin control subsystem.
	165	*/
	166	static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
	167	{
	168	struct gsta_regs __iomem *regs = __regs(chip, nr);
	169	unsigned long flags;
	170	u32 bit = __bit(nr);
	171	u32 val;
	172	int err = 0;
	173
	174	pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);
	175
	176	if (cfg == PINMUX_TYPE_NONE)
	177	return;
	178
	179	/* Alternate function or not? */
	180	spin_lock_irqsave(&chip->lock, flags);
	181	val = readl(&regs->afsela);
	182	if (cfg == PINMUX_TYPE_FUNCTION)
	183	val \|= bit;
	184	else
	185	val &= ~bit;
	186	writel(val \| bit, &regs->afsela);
	187	if (cfg == PINMUX_TYPE_FUNCTION) {
	188	spin_unlock_irqrestore(&chip->lock, flags);
	189	return;
	190	}
	191
	192	/* not alternate function: set details */
	193	switch (cfg) {
	194	case PINMUX_TYPE_OUTPUT_LOW:
	195	writel(bit, &regs->dirs);
	196	writel(bit, &regs->datc);
	197	break;
	198	case PINMUX_TYPE_OUTPUT_HIGH:
	199	writel(bit, &regs->dirs);
	200	writel(bit, &regs->dats);
	201	break;
	202	case PINMUX_TYPE_INPUT:
	203	writel(bit, &regs->dirc);
	204	val = readl(&regs->pdis) \| bit;
	205	writel(val, &regs->pdis);
	206	break;
	207	case PINMUX_TYPE_INPUT_PULLUP:
	208	writel(bit, &regs->dirc);
	209	val = readl(&regs->pdis) & ~bit;
	210	writel(val, &regs->pdis);
	211	writel(bit, &regs->dats);
	212	break;
	213	case PINMUX_TYPE_INPUT_PULLDOWN:
214	writel(bit, &regs->dirc);
215	val = readl(&regs->pdis) & ~bit;
216	writel(val, &regs->pdis);
217	writel(bit, &regs->datc);
218	break;
219	default:
220	err = 1;
221	}
222	spin_unlock_irqrestore(&chip->lock, flags);
223	if (err)
224	pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
225	__func__, chip, nr, cfg);
226	}
227
228	/*
229	* Irq methods
230	*/
231
232	static void gsta_irq_disable(struct irq_data *data)
233	{
234	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
235	struct gsta_gpio *chip = gc->private;
236	int nr = data->irq - chip->irq_base;
237	struct gsta_regs __iomem *regs = __regs(chip, nr);
238	u32 bit = __bit(nr);
239	u32 val;
240	unsigned long flags;
241
242	spin_lock_irqsave(&chip->lock, flags);
243	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
244	val = readl(&regs->rimsc) & ~bit;
245	writel(val, &regs->rimsc);
246	}
247	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
248	val = readl(&regs->fimsc) & ~bit;
249	writel(val, &regs->fimsc);
250	}
251	spin_unlock_irqrestore(&chip->lock, flags);
252	return;
253	}
254
255	static void gsta_irq_enable(struct irq_data *data)
256	{
257	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
258	struct gsta_gpio *chip = gc->private;
259	int nr = data->irq - chip->irq_base;
260	struct gsta_regs __iomem *regs = __regs(chip, nr);
261	u32 bit = __bit(nr);
262	u32 val;
263	int type;
264	unsigned long flags;
265
266	type = chip->irq_type[nr];
267
268	spin_lock_irqsave(&chip->lock, flags);
269	val = readl(&regs->rimsc);
270	if (type & IRQ_TYPE_EDGE_RISING)
271	writel(val \| bit, &regs->rimsc);
272	else
273	writel(val & ~bit, &regs->rimsc);
274	val = readl(&regs->rimsc);
275	if (type & IRQ_TYPE_EDGE_FALLING)
276	writel(val \| bit, &regs->fimsc);
277	else
278	writel(val & ~bit, &regs->fimsc);
279	spin_unlock_irqrestore(&chip->lock, flags);
280	return;
281	}
282
283	static int gsta_irq_type(struct irq_data *d, unsigned int type)
284	{
285	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
286	struct gsta_gpio *chip = gc->private;
287	int nr = d->irq - chip->irq_base;
288
289	/* We only support edge interrupts */
290	if (!(type & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING))) {
291	pr_debug("%s: unsupported type 0x%x\n", __func__, type);
292	return -EINVAL;
293	}
294
295	chip->irq_type[nr] = type; /* used for enable/disable */
296
297	gsta_irq_enable(d);
298	return 0;
299	}
300
301	static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
302	{
303	struct gsta_gpio *chip = dev_id;
304	struct gsta_regs __iomem *regs;
305	u32 is;
306	int i, nr, base;
307	irqreturn_t ret = IRQ_NONE;
308
309	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
310	regs = chip->regs[i];
311	base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
312	while ((is = readl(&regs->is))) {
313	nr = __ffs(is);
314	irq = base + nr;
315	generic_handle_irq(irq);
316	writel(1 << nr, &regs->ic);
317	ret = IRQ_HANDLED;
318	}
319	}
320	return ret;
321	}
322
3836309d	323	static void gsta_alloc_irq_chip(struct gsta_gpio *chip)
7b0d44f3 AR	324	{
	325	struct irq_chip_generic *gc;
	326	struct irq_chip_type *ct;
	327
	328	gc = irq_alloc_generic_chip(KBUILD_MODNAME, 1, chip->irq_base,
	329	chip->reg_base, handle_simple_irq);
	330	gc->private = chip;
	331	ct = gc->chip_types;
	332
	333	ct->chip.irq_set_type = gsta_irq_type;
	334	ct->chip.irq_disable = gsta_irq_disable;
	335	ct->chip.irq_enable = gsta_irq_enable;
	336
	337	/* FIXME: this makes at most 32 interrupts. Request 0 by now */
	338	irq_setup_generic_chip(gc, 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */, 0,
	339	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
	340
	341	/* Set up all all 128 interrupts: code from setup_generic_chip */
	342	{
	343	struct irq_chip_type *ct = gc->chip_types;
	344	int i, j;
	345	for (j = 0; j < GSTA_NR_GPIO; j++) {
	346	i = chip->irq_base + j;
	347	irq_set_chip_and_handler(i, &ct->chip, ct->handler);
	348	irq_set_chip_data(i, gc);
23393d49	349	irq_clear_status_flags(i, IRQ_NOREQUEST \| IRQ_NOPROBE);
7b0d44f3 AR	350	}
	351	gc->irq_cnt = i - gc->irq_base;
	352	}
	353	}
	354
	355	/* The platform device used here is instantiated by the MFD device */
3836309d	356	static int gsta_probe(struct platform_device *dev)
7b0d44f3 AR	357	{
	358	int i, err;
	359	struct pci_dev *pdev;
	360	struct sta2x11_gpio_pdata *gpio_pdata;
	361	struct gsta_gpio *chip;
	362	struct resource *res;
	363
e56aee18	364	pdev = (struct pci_dev *)dev_get_platdata(&dev->dev);
7b0d44f3 AR	365	gpio_pdata = dev_get_platdata(&pdev->dev);
	366
	367	if (gpio_pdata == NULL)
	368	dev_err(&dev->dev, "no gpio config\n");
	369	pr_debug("gpio config: %p\n", gpio_pdata);
	370
	371	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	372
	373	chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
cd738916 SK	374	if (!chip)
cd738916 SK	375	return -ENOMEM;
7b0d44f3	376	chip->dev = &dev->dev;
62ffac14 TB	377	chip->reg_base = devm_ioremap_resource(&dev->dev, res);
	378	if (IS_ERR(chip->reg_base))
	379	return PTR_ERR(chip->reg_base);
7b0d44f3 AR	380
	381	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
	382	chip->regs[i] = chip->reg_base + i * 4096;
	383	/* disable all irqs */
	384	writel(0, &chip->regs[i]->rimsc);
	385	writel(0, &chip->regs[i]->fimsc);
	386	writel(~0, &chip->regs[i]->ic);
	387	}
	388	spin_lock_init(&chip->lock);
	389	gsta_gpio_setup(chip);
2e2070c8 AR	390	if (gpio_pdata)
	391	for (i = 0; i < GSTA_NR_GPIO; i++)
	392	gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);
7b0d44f3 AR	393
	394	/* 384 was used in previous code: be compatible for other drivers */
	395	err = irq_alloc_descs(-1, 384, GSTA_NR_GPIO, NUMA_NO_NODE);
	396	if (err < 0) {
	397	dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
	398	-err);
	399	return err;
	400	}
	401	chip->irq_base = err;
	402	gsta_alloc_irq_chip(chip);
	403
	404	err = request_irq(pdev->irq, gsta_gpio_handler,
	405	IRQF_SHARED, KBUILD_MODNAME, chip);
	406	if (err < 0) {
	407	dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
	408	-err);
	409	goto err_free_descs;
	410	}
	411
5fa734cc	412	err = devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip);
7b0d44f3 AR	413	if (err < 0) {
	414	dev_err(&dev->dev, "sta2x11 gpio: Can't register (%i)\n",
	415	-err);
	416	goto err_free_irq;
	417	}
	418
	419	platform_set_drvdata(dev, chip);
	420	return 0;
	421
	422	err_free_irq:
	423	free_irq(pdev->irq, chip);
	424	err_free_descs:
	425	irq_free_descs(chip->irq_base, GSTA_NR_GPIO);
	426	return err;
	427	}
	428
	429	static struct platform_driver sta2x11_gpio_platform_driver = {
	430	.driver = {
	431	.name = "sta2x11-gpio",
7b0d44f3 AR	432	},
	433	.probe = gsta_probe,
	434	};
3c90c6d6	435	builtin_platform_driver(sta2x11_gpio_platform_driver);