[linux.git] / drivers / gpio / gpio-lpc32xx.c

/*
 * GPIO driver for LPC32xx SoC
 *
 * Author: Kevin Wells <[email protected]>
 *
 * Copyright (C) 2010 NXP Semiconductors
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/platform_data/gpio-lpc32xx.h>

#include <mach/hardware.h>
#include <mach/platform.h>

#define LPC32XX_GPIO_P3_INP_STATE		_GPREG(0x000)
#define LPC32XX_GPIO_P3_OUTP_SET		_GPREG(0x004)
#define LPC32XX_GPIO_P3_OUTP_CLR		_GPREG(0x008)
#define LPC32XX_GPIO_P3_OUTP_STATE		_GPREG(0x00C)
#define LPC32XX_GPIO_P2_DIR_SET			_GPREG(0x010)
#define LPC32XX_GPIO_P2_DIR_CLR			_GPREG(0x014)
#define LPC32XX_GPIO_P2_DIR_STATE		_GPREG(0x018)
#define LPC32XX_GPIO_P2_INP_STATE		_GPREG(0x01C)
#define LPC32XX_GPIO_P2_OUTP_SET		_GPREG(0x020)
#define LPC32XX_GPIO_P2_OUTP_CLR		_GPREG(0x024)
#define LPC32XX_GPIO_P2_MUX_SET			_GPREG(0x028)
#define LPC32XX_GPIO_P2_MUX_CLR			_GPREG(0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE		_GPREG(0x030)
#define LPC32XX_GPIO_P0_INP_STATE		_GPREG(0x040)
#define LPC32XX_GPIO_P0_OUTP_SET		_GPREG(0x044)
#define LPC32XX_GPIO_P0_OUTP_CLR		_GPREG(0x048)
#define LPC32XX_GPIO_P0_OUTP_STATE		_GPREG(0x04C)
#define LPC32XX_GPIO_P0_DIR_SET			_GPREG(0x050)
#define LPC32XX_GPIO_P0_DIR_CLR			_GPREG(0x054)
#define LPC32XX_GPIO_P0_DIR_STATE		_GPREG(0x058)
#define LPC32XX_GPIO_P1_INP_STATE		_GPREG(0x060)
#define LPC32XX_GPIO_P1_OUTP_SET		_GPREG(0x064)
#define LPC32XX_GPIO_P1_OUTP_CLR		_GPREG(0x068)
#define LPC32XX_GPIO_P1_OUTP_STATE		_GPREG(0x06C)
#define LPC32XX_GPIO_P1_DIR_SET			_GPREG(0x070)
#define LPC32XX_GPIO_P1_DIR_CLR			_GPREG(0x074)
#define LPC32XX_GPIO_P1_DIR_STATE		_GPREG(0x078)

#define GPIO012_PIN_TO_BIT(x)			(1 << (x))
#define GPIO3_PIN_TO_BIT(x)			(1 << ((x) + 25))
#define GPO3_PIN_TO_BIT(x)			(1 << (x))
#define GPIO012_PIN_IN_SEL(x, y)		(((x) >> (y)) & 1)
#define GPIO3_PIN_IN_SHIFT(x)			((x) == 5 ? 24 : 10 + (x))
#define GPIO3_PIN_IN_SEL(x, y)			(((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
#define GPIO3_PIN5_IN_SEL(x)			(((x) >> 24) & 1)
#define GPI3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
#define GPO3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)

struct gpio_regs {
	void __iomem *inp_state;
	void __iomem *outp_state;
	void __iomem *outp_set;
	void __iomem *outp_clr;
	void __iomem *dir_set;
	void __iomem *dir_clr;
};

/*
 * GPIO names
 */
static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
	"p0.0", "p0.1", "p0.2", "p0.3",
	"p0.4", "p0.5", "p0.6", "p0.7"
};

static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
	"p1.0", "p1.1", "p1.2", "p1.3",
	"p1.4", "p1.5", "p1.6", "p1.7",
	"p1.8", "p1.9", "p1.10", "p1.11",
	"p1.12", "p1.13", "p1.14", "p1.15",
	"p1.16", "p1.17", "p1.18", "p1.19",
	"p1.20", "p1.21", "p1.22", "p1.23",
};

static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
	"p2.0", "p2.1", "p2.2", "p2.3",
	"p2.4", "p2.5", "p2.6", "p2.7",
	"p2.8", "p2.9", "p2.10", "p2.11",
	"p2.12"
};

static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
	"gpio00", "gpio01", "gpio02", "gpio03",
	"gpio04", "gpio05"
};

static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
	"gpi00", "gpi01", "gpi02", "gpi03",
	"gpi04", "gpi05", "gpi06", "gpi07",
	"gpi08", "gpi09",  NULL,    NULL,
	 NULL,    NULL,    NULL,   "gpi15",
	"gpi16", "gpi17", "gpi18", "gpi19",
	"gpi20", "gpi21", "gpi22", "gpi23",
	"gpi24", "gpi25", "gpi26", "gpi27",
	"gpi28"
};

static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
	"gpo00", "gpo01", "gpo02", "gpo03",
	"gpo04", "gpo05", "gpo06", "gpo07",
	"gpo08", "gpo09", "gpo10", "gpo11",
	"gpo12", "gpo13", "gpo14", "gpo15",
	"gpo16", "gpo17", "gpo18", "gpo19",
	"gpo20", "gpo21", "gpo22", "gpo23"
};

static struct gpio_regs gpio_grp_regs_p0 = {
	.inp_state	= LPC32XX_GPIO_P0_INP_STATE,
	.outp_set	= LPC32XX_GPIO_P0_OUTP_SET,
	.outp_clr	= LPC32XX_GPIO_P0_OUTP_CLR,
	.dir_set	= LPC32XX_GPIO_P0_DIR_SET,
	.dir_clr	= LPC32XX_GPIO_P0_DIR_CLR,
};

static struct gpio_regs gpio_grp_regs_p1 = {
	.inp_state	= LPC32XX_GPIO_P1_INP_STATE,
	.outp_set	= LPC32XX_GPIO_P1_OUTP_SET,
	.outp_clr	= LPC32XX_GPIO_P1_OUTP_CLR,
	.dir_set	= LPC32XX_GPIO_P1_DIR_SET,
	.dir_clr	= LPC32XX_GPIO_P1_DIR_CLR,
};

static struct gpio_regs gpio_grp_regs_p2 = {
	.inp_state	= LPC32XX_GPIO_P2_INP_STATE,
	.outp_set	= LPC32XX_GPIO_P2_OUTP_SET,
	.outp_clr	= LPC32XX_GPIO_P2_OUTP_CLR,
	.dir_set	= LPC32XX_GPIO_P2_DIR_SET,
	.dir_clr	= LPC32XX_GPIO_P2_DIR_CLR,
};

static struct gpio_regs gpio_grp_regs_p3 = {
	.inp_state	= LPC32XX_GPIO_P3_INP_STATE,
	.outp_state	= LPC32XX_GPIO_P3_OUTP_STATE,
	.outp_set	= LPC32XX_GPIO_P3_OUTP_SET,
	.outp_clr	= LPC32XX_GPIO_P3_OUTP_CLR,
	.dir_set	= LPC32XX_GPIO_P2_DIR_SET,
	.dir_clr	= LPC32XX_GPIO_P2_DIR_CLR,
};

struct lpc32xx_gpio_chip {
	struct gpio_chip	chip;
	struct gpio_regs	*gpio_grp;
};

static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
	unsigned pin, int input)
{
	if (input)
		__raw_writel(GPIO012_PIN_TO_BIT(pin),
			group->gpio_grp->dir_clr);
	else
		__raw_writel(GPIO012_PIN_TO_BIT(pin),
			group->gpio_grp->dir_set);
}

static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin, int input)
{
	u32 u = GPIO3_PIN_TO_BIT(pin);

	if (input)
		__raw_writel(u, group->gpio_grp->dir_clr);
	else
		__raw_writel(u, group->gpio_grp->dir_set);
}

static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
	unsigned pin, int high)
{
	if (high)
		__raw_writel(GPIO012_PIN_TO_BIT(pin),
			group->gpio_grp->outp_set);
	else
		__raw_writel(GPIO012_PIN_TO_BIT(pin),
			group->gpio_grp->outp_clr);
}

static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin, int high)
{
	u32 u = GPIO3_PIN_TO_BIT(pin);

	if (high)
		__raw_writel(u, group->gpio_grp->outp_set);
	else
		__raw_writel(u, group->gpio_grp->outp_clr);
}

static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin, int high)
{
	if (high)
		__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
	else
		__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
}

static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
	unsigned pin)
{
	return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
		pin);
}

static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin)
{
	int state = __raw_readl(group->gpio_grp->inp_state);

	/*
	 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
	 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
	 */
	return GPIO3_PIN_IN_SEL(state, pin);
}

static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin)
{
	return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
}

static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin)
{
	return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
}

/*
 * GPIO primitives.
 */
static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
	unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_dir_p012(group, pin, 1);

	return 0;
}

static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
	unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_dir_p3(group, pin, 1);

	return 0;
}

static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
	unsigned pin)
{
	return 0;
}

static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	return !!__get_gpio_state_p012(group, pin);
}

static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	return !!__get_gpio_state_p3(group, pin);
}

static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	return !!__get_gpi_state_p3(group, pin);
}

static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_level_p012(group, pin, value);
	__set_gpio_dir_p012(group, pin, 0);

	return 0;
}

static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_level_p3(group, pin, value);
	__set_gpio_dir_p3(group, pin, 0);

	return 0;
}

static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpo_level_p3(group, pin, value);
	return 0;
}

static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_level_p012(group, pin, value);
}

static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_level_p3(group, pin, value);
}

static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpo_level_p3(group, pin, value);
}

static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	return !!__get_gpo_state_p3(group, pin);
}

static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
{
	if (pin < chip->ngpio)
		return 0;

	return -EINVAL;
}

static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
{
	return -ENXIO;
}

static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
{
	return -ENXIO;
}

static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
{
	return -ENXIO;
}

static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
	{
		.chip = {
			.label			= "gpio_p0",
			.direction_input	= lpc32xx_gpio_dir_input_p012,
			.get			= lpc32xx_gpio_get_value_p012,
			.direction_output	= lpc32xx_gpio_dir_output_p012,
			.set			= lpc32xx_gpio_set_value_p012,
			.request		= lpc32xx_gpio_request,
			.to_irq			= lpc32xx_gpio_to_irq_p01,
			.base			= LPC32XX_GPIO_P0_GRP,
			.ngpio			= LPC32XX_GPIO_P0_MAX,
			.names			= gpio_p0_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p0,
	},
	{
		.chip = {
			.label			= "gpio_p1",
			.direction_input	= lpc32xx_gpio_dir_input_p012,
			.get			= lpc32xx_gpio_get_value_p012,
			.direction_output	= lpc32xx_gpio_dir_output_p012,
			.set			= lpc32xx_gpio_set_value_p012,
			.request		= lpc32xx_gpio_request,
			.to_irq			= lpc32xx_gpio_to_irq_p01,
			.base			= LPC32XX_GPIO_P1_GRP,
			.ngpio			= LPC32XX_GPIO_P1_MAX,
			.names			= gpio_p1_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p1,
	},
	{
		.chip = {
			.label			= "gpio_p2",
			.direction_input	= lpc32xx_gpio_dir_input_p012,
			.get			= lpc32xx_gpio_get_value_p012,
			.direction_output	= lpc32xx_gpio_dir_output_p012,
			.set			= lpc32xx_gpio_set_value_p012,
			.request		= lpc32xx_gpio_request,
			.base			= LPC32XX_GPIO_P2_GRP,
			.ngpio			= LPC32XX_GPIO_P2_MAX,
			.names			= gpio_p2_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p2,
	},
	{
		.chip = {
			.label			= "gpio_p3",
			.direction_input	= lpc32xx_gpio_dir_input_p3,
			.get			= lpc32xx_gpio_get_value_p3,
			.direction_output	= lpc32xx_gpio_dir_output_p3,
			.set			= lpc32xx_gpio_set_value_p3,
			.request		= lpc32xx_gpio_request,
			.to_irq			= lpc32xx_gpio_to_irq_gpio_p3,
			.base			= LPC32XX_GPIO_P3_GRP,
			.ngpio			= LPC32XX_GPIO_P3_MAX,
			.names			= gpio_p3_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p3,
	},
	{
		.chip = {
			.label			= "gpi_p3",
			.direction_input	= lpc32xx_gpio_dir_in_always,
			.get			= lpc32xx_gpi_get_value,
			.request		= lpc32xx_gpio_request,
			.to_irq			= lpc32xx_gpio_to_irq_gpi_p3,
			.base			= LPC32XX_GPI_P3_GRP,
			.ngpio			= LPC32XX_GPI_P3_MAX,
			.names			= gpi_p3_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p3,
	},
	{
		.chip = {
			.label			= "gpo_p3",
			.direction_output	= lpc32xx_gpio_dir_out_always,
			.set			= lpc32xx_gpo_set_value,
			.get			= lpc32xx_gpo_get_value,
			.request		= lpc32xx_gpio_request,
			.base			= LPC32XX_GPO_P3_GRP,
			.ngpio			= LPC32XX_GPO_P3_MAX,
			.names			= gpo_p3_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p3,
	},
};

static int lpc32xx_of_xlate(struct gpio_chip *gc,
			    const struct of_phandle_args *gpiospec, u32 *flags)
{
	/* Is this the correct bank? */
	u32 bank = gpiospec->args[0];
	if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
	    (gc != &lpc32xx_gpiochip[bank].chip)))
		return -EINVAL;

	if (flags)
		*flags = gpiospec->args[2];
	return gpiospec->args[1];
}

static int lpc32xx_gpio_probe(struct platform_device *pdev)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
		if (pdev->dev.of_node) {
			lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
			lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
			lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
		}
		devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
				  &lpc32xx_gpiochip[i]);
	}

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id lpc32xx_gpio_of_match[] = {
	{ .compatible = "nxp,lpc3220-gpio", },
	{ },
};
#endif

static struct platform_driver lpc32xx_gpio_driver = {
	.driver		= {
		.name	= "lpc32xx-gpio",
		.of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
	},
	.probe		= lpc32xx_gpio_probe,
};

module_platform_driver(lpc32xx_gpio_driver);
Commit	Line	Data
c4a0208f	1	/*
da03d740	2	* GPIO driver for LPC32xx SoC
c4a0208f KW	3	*
	4	* Author: Kevin Wells <[email protected]>
	5	*
	6	* Copyright (C) 2010 NXP Semiconductors
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/io.h>
	22	#include <linux/errno.h>
	23	#include <linux/gpio.h>
831cbd7a	24	#include <linux/of.h>
e92935e1 RS	25	#include <linux/of_gpio.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/module.h>
eef80f33	28	#include <linux/platform_data/gpio-lpc32xx.h>
c4a0208f KW	29
	30	#include <mach/hardware.h>
	31	#include <mach/platform.h>
c4a0208f KW	32
	33	#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
	34	#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
	35	#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
	36	#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
	37	#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
	38	#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
	39	#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
	40	#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
	41	#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
	42	#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
	43	#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
	44	#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
	45	#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
	46	#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
	47	#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
	48	#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
	49	#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
	50	#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
	51	#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
	52	#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
	53	#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
	54	#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
	55	#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
	56	#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
	57	#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
	58	#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
	59	#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
	60
	61	#define GPIO012_PIN_TO_BIT(x) (1 << (x))
	62	#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
	63	#define GPO3_PIN_TO_BIT(x) (1 << (x))
	64	#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
	65	#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
8e5fb37b	66	#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
c4a0208f KW	67	#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
c4a0208f KW	68	#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
46158aad	69	#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
c4a0208f KW	70
	71	struct gpio_regs {
	72	void __iomem *inp_state;
46158aad	73	void __iomem *outp_state;
c4a0208f KW	74	void __iomem *outp_set;
	75	void __iomem *outp_clr;
	76	void __iomem *dir_set;
	77	void __iomem *dir_clr;
	78	};
	79
	80	/*
	81	* GPIO names
	82	*/
	83	static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
	84	"p0.0", "p0.1", "p0.2", "p0.3",
	85	"p0.4", "p0.5", "p0.6", "p0.7"
	86	};
	87
	88	static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
	89	"p1.0", "p1.1", "p1.2", "p1.3",
	90	"p1.4", "p1.5", "p1.6", "p1.7",
	91	"p1.8", "p1.9", "p1.10", "p1.11",
	92	"p1.12", "p1.13", "p1.14", "p1.15",
	93	"p1.16", "p1.17", "p1.18", "p1.19",
	94	"p1.20", "p1.21", "p1.22", "p1.23",
	95	};
	96
	97	static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
	98	"p2.0", "p2.1", "p2.2", "p2.3",
	99	"p2.4", "p2.5", "p2.6", "p2.7",
	100	"p2.8", "p2.9", "p2.10", "p2.11",
	101	"p2.12"
	102	};
	103
	104	static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
95120d5d	105	"gpio00", "gpio01", "gpio02", "gpio03",
c4a0208f KW	106	"gpio04", "gpio05"
	107	};
	108
	109	static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
	110	"gpi00", "gpi01", "gpi02", "gpi03",
	111	"gpi04", "gpi05", "gpi06", "gpi07",
	112	"gpi08", "gpi09", NULL, NULL,
	113	NULL, NULL, NULL, "gpi15",
	114	"gpi16", "gpi17", "gpi18", "gpi19",
	115	"gpi20", "gpi21", "gpi22", "gpi23",
71fde000 RS	116	"gpi24", "gpi25", "gpi26", "gpi27",
71fde000 RS	117	"gpi28"
c4a0208f KW	118	};
	119
	120	static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
	121	"gpo00", "gpo01", "gpo02", "gpo03",
	122	"gpo04", "gpo05", "gpo06", "gpo07",
	123	"gpo08", "gpo09", "gpo10", "gpo11",
	124	"gpo12", "gpo13", "gpo14", "gpo15",
	125	"gpo16", "gpo17", "gpo18", "gpo19",
	126	"gpo20", "gpo21", "gpo22", "gpo23"
	127	};
	128
	129	static struct gpio_regs gpio_grp_regs_p0 = {
	130	.inp_state = LPC32XX_GPIO_P0_INP_STATE,
	131	.outp_set = LPC32XX_GPIO_P0_OUTP_SET,
	132	.outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
	133	.dir_set = LPC32XX_GPIO_P0_DIR_SET,
	134	.dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
	135	};
	136
	137	static struct gpio_regs gpio_grp_regs_p1 = {
	138	.inp_state = LPC32XX_GPIO_P1_INP_STATE,
	139	.outp_set = LPC32XX_GPIO_P1_OUTP_SET,
	140	.outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
	141	.dir_set = LPC32XX_GPIO_P1_DIR_SET,
	142	.dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
	143	};
	144
	145	static struct gpio_regs gpio_grp_regs_p2 = {
	146	.inp_state = LPC32XX_GPIO_P2_INP_STATE,
	147	.outp_set = LPC32XX_GPIO_P2_OUTP_SET,
	148	.outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
	149	.dir_set = LPC32XX_GPIO_P2_DIR_SET,
	150	.dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
	151	};
	152
	153	static struct gpio_regs gpio_grp_regs_p3 = {
	154	.inp_state = LPC32XX_GPIO_P3_INP_STATE,
46158aad	155	.outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
c4a0208f KW	156	.outp_set = LPC32XX_GPIO_P3_OUTP_SET,
	157	.outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
	158	.dir_set = LPC32XX_GPIO_P2_DIR_SET,
	159	.dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
	160	};
	161
	162	struct lpc32xx_gpio_chip {
	163	struct gpio_chip chip;
	164	struct gpio_regs *gpio_grp;
	165	};
	166
c4a0208f KW	167	static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
	168	unsigned pin, int input)
	169	{
	170	if (input)
	171	__raw_writel(GPIO012_PIN_TO_BIT(pin),
	172	group->gpio_grp->dir_clr);
	173	else
	174	__raw_writel(GPIO012_PIN_TO_BIT(pin),
	175	group->gpio_grp->dir_set);
	176	}
	177
	178	static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
	179	unsigned pin, int input)
	180	{
	181	u32 u = GPIO3_PIN_TO_BIT(pin);
	182
	183	if (input)
	184	__raw_writel(u, group->gpio_grp->dir_clr);
	185	else
	186	__raw_writel(u, group->gpio_grp->dir_set);
	187	}
	188
	189	static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
	190	unsigned pin, int high)
	191	{
	192	if (high)
	193	__raw_writel(GPIO012_PIN_TO_BIT(pin),
	194	group->gpio_grp->outp_set);
	195	else
	196	__raw_writel(GPIO012_PIN_TO_BIT(pin),
	197	group->gpio_grp->outp_clr);
	198	}
	199
	200	static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
	201	unsigned pin, int high)
	202	{
	203	u32 u = GPIO3_PIN_TO_BIT(pin);
	204
	205	if (high)
	206	__raw_writel(u, group->gpio_grp->outp_set);
	207	else
	208	__raw_writel(u, group->gpio_grp->outp_clr);
	209	}
	210
	211	static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
	212	unsigned pin, int high)
	213	{
	214	if (high)
	215	__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
	216	else
	217	__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
	218	}
	219
	220	static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
	221	unsigned pin)
	222	{
	223	return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
	224	pin);
	225	}
	226
	227	static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
	228	unsigned pin)
	229	{
	230	int state = __raw_readl(group->gpio_grp->inp_state);
231
232	/*
233	* P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
234	* to bits 10..14, while GPIOP3-5 is mapped to bit 24.
235	*/
236	return GPIO3_PIN_IN_SEL(state, pin);
237	}
238
239	static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
240	unsigned pin)
241	{
242	return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
243	}
244
46158aad RS	245	static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
	246	unsigned pin)
	247	{
	248	return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
	249	}
	250
c4a0208f	251	/*
7fd2bf3d	252	* GPIO primitives.
c4a0208f KW	253	*/
	254	static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
	255	unsigned pin)
	256	{
a9bc97e4	257	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	258
	259	__set_gpio_dir_p012(group, pin, 1);
	260
	261	return 0;
	262	}
	263
	264	static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
	265	unsigned pin)
	266	{
a9bc97e4	267	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	268
	269	__set_gpio_dir_p3(group, pin, 1);
	270
	271	return 0;
	272	}
	273
	274	static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
	275	unsigned pin)
	276	{
	277	return 0;
	278	}
	279
	280	static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
	281	{
a9bc97e4	282	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	283
2e6d8456	284	return !!__get_gpio_state_p012(group, pin);
c4a0208f KW	285	}
	286
	287	static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
	288	{
a9bc97e4	289	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	290
2e6d8456	291	return !!__get_gpio_state_p3(group, pin);
c4a0208f KW	292	}
	293
	294	static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
	295	{
a9bc97e4	296	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	297
2e6d8456	298	return !!__get_gpi_state_p3(group, pin);
c4a0208f KW	299	}
	300
	301	static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
	302	int value)
	303	{
a9bc97e4	304	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	305
b1268d37	306	__set_gpio_level_p012(group, pin, value);
c4a0208f KW	307	__set_gpio_dir_p012(group, pin, 0);
	308
	309	return 0;
	310	}
	311
	312	static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
	313	int value)
	314	{
a9bc97e4	315	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	316
b1268d37	317	__set_gpio_level_p3(group, pin, value);
c4a0208f KW	318	__set_gpio_dir_p3(group, pin, 0);
	319
	320	return 0;
	321	}
	322
	323	static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
	324	int value)
	325	{
a9bc97e4	326	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
b1268d37 RS	327
b1268d37 RS	328	__set_gpo_level_p3(group, pin, value);
c4a0208f KW	329	return 0;
	330	}
	331
	332	static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
	333	int value)
	334	{
a9bc97e4	335	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	336
	337	__set_gpio_level_p012(group, pin, value);
	338	}
	339
	340	static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
	341	int value)
	342	{
a9bc97e4	343	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	344
	345	__set_gpio_level_p3(group, pin, value);
	346	}
	347
	348	static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
	349	int value)
	350	{
a9bc97e4	351	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	352
	353	__set_gpo_level_p3(group, pin, value);
	354	}
	355
46158aad RS	356	static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
46158aad RS	357	{
a9bc97e4	358	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
46158aad	359
2e6d8456	360	return !!__get_gpo_state_p3(group, pin);
46158aad RS	361	}
46158aad RS	362
c4a0208f KW	363	static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
	364	{
	365	if (pin < chip->ngpio)
	366	return 0;
	367
	368	return -EINVAL;
	369	}
	370
0bdfeddc RS	371	static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
0bdfeddc RS	372	{
320a6480	373	return -ENXIO;
0bdfeddc RS	374	}
0bdfeddc RS	375
0bdfeddc RS	376	static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
0bdfeddc RS	377	{
0bdfeddc RS	378	return -ENXIO;
	379	}
	380
0bdfeddc RS	381	static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
0bdfeddc RS	382	{
0bdfeddc RS	383	return -ENXIO;
	384	}
	385
c4a0208f KW	386	static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
	387	{
	388	.chip = {
	389	.label = "gpio_p0",
	390	.direction_input = lpc32xx_gpio_dir_input_p012,
	391	.get = lpc32xx_gpio_get_value_p012,
	392	.direction_output = lpc32xx_gpio_dir_output_p012,
	393	.set = lpc32xx_gpio_set_value_p012,
	394	.request = lpc32xx_gpio_request,
0bdfeddc	395	.to_irq = lpc32xx_gpio_to_irq_p01,
c4a0208f KW	396	.base = LPC32XX_GPIO_P0_GRP,
	397	.ngpio = LPC32XX_GPIO_P0_MAX,
	398	.names = gpio_p0_names,
9fb1f39e	399	.can_sleep = false,
c4a0208f KW	400	},
	401	.gpio_grp = &gpio_grp_regs_p0,
	402	},
	403	{
	404	.chip = {
	405	.label = "gpio_p1",
	406	.direction_input = lpc32xx_gpio_dir_input_p012,
	407	.get = lpc32xx_gpio_get_value_p012,
	408	.direction_output = lpc32xx_gpio_dir_output_p012,
	409	.set = lpc32xx_gpio_set_value_p012,
	410	.request = lpc32xx_gpio_request,
0bdfeddc	411	.to_irq = lpc32xx_gpio_to_irq_p01,
c4a0208f KW	412	.base = LPC32XX_GPIO_P1_GRP,
	413	.ngpio = LPC32XX_GPIO_P1_MAX,
	414	.names = gpio_p1_names,
9fb1f39e	415	.can_sleep = false,
c4a0208f KW	416	},
	417	.gpio_grp = &gpio_grp_regs_p1,
	418	},
	419	{
	420	.chip = {
	421	.label = "gpio_p2",
	422	.direction_input = lpc32xx_gpio_dir_input_p012,
	423	.get = lpc32xx_gpio_get_value_p012,
	424	.direction_output = lpc32xx_gpio_dir_output_p012,
	425	.set = lpc32xx_gpio_set_value_p012,
	426	.request = lpc32xx_gpio_request,
	427	.base = LPC32XX_GPIO_P2_GRP,
	428	.ngpio = LPC32XX_GPIO_P2_MAX,
	429	.names = gpio_p2_names,
9fb1f39e	430	.can_sleep = false,
c4a0208f KW	431	},
	432	.gpio_grp = &gpio_grp_regs_p2,
	433	},
	434	{
	435	.chip = {
	436	.label = "gpio_p3",
	437	.direction_input = lpc32xx_gpio_dir_input_p3,
	438	.get = lpc32xx_gpio_get_value_p3,
	439	.direction_output = lpc32xx_gpio_dir_output_p3,
	440	.set = lpc32xx_gpio_set_value_p3,
	441	.request = lpc32xx_gpio_request,
0bdfeddc	442	.to_irq = lpc32xx_gpio_to_irq_gpio_p3,
c4a0208f KW	443	.base = LPC32XX_GPIO_P3_GRP,
	444	.ngpio = LPC32XX_GPIO_P3_MAX,
	445	.names = gpio_p3_names,
9fb1f39e	446	.can_sleep = false,
c4a0208f KW	447	},
	448	.gpio_grp = &gpio_grp_regs_p3,
	449	},
	450	{
	451	.chip = {
	452	.label = "gpi_p3",
	453	.direction_input = lpc32xx_gpio_dir_in_always,
	454	.get = lpc32xx_gpi_get_value,
	455	.request = lpc32xx_gpio_request,
0bdfeddc	456	.to_irq = lpc32xx_gpio_to_irq_gpi_p3,
c4a0208f KW	457	.base = LPC32XX_GPI_P3_GRP,
	458	.ngpio = LPC32XX_GPI_P3_MAX,
	459	.names = gpi_p3_names,
9fb1f39e	460	.can_sleep = false,
c4a0208f KW	461	},
	462	.gpio_grp = &gpio_grp_regs_p3,
	463	},
	464	{
	465	.chip = {
	466	.label = "gpo_p3",
	467	.direction_output = lpc32xx_gpio_dir_out_always,
	468	.set = lpc32xx_gpo_set_value,
46158aad	469	.get = lpc32xx_gpo_get_value,
c4a0208f KW	470	.request = lpc32xx_gpio_request,
	471	.base = LPC32XX_GPO_P3_GRP,
	472	.ngpio = LPC32XX_GPO_P3_MAX,
	473	.names = gpo_p3_names,
9fb1f39e	474	.can_sleep = false,
c4a0208f KW	475	},
	476	.gpio_grp = &gpio_grp_regs_p3,
	477	},
	478	};
	479
e92935e1 RS	480	static int lpc32xx_of_xlate(struct gpio_chip *gc,
	481	const struct of_phandle_args gpiospec, u32 flags)
	482	{
	483	/* Is this the correct bank? */
	484	u32 bank = gpiospec->args[0];
fdc7a9f8	485	if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) \|\|
e92935e1 RS	486	(gc != &lpc32xx_gpiochip[bank].chip)))
	487	return -EINVAL;
	488
	489	if (flags)
	490	*flags = gpiospec->args[2];
	491	return gpiospec->args[1];
	492	}
	493
3836309d	494	static int lpc32xx_gpio_probe(struct platform_device *pdev)
c4a0208f KW	495	{
	496	int i;
	497
e92935e1 RS	498	for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
	499	if (pdev->dev.of_node) {
	500	lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
	501	lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
	502	lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
	503	}
69c0a0a5	504	devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
a9bc97e4	505	&lpc32xx_gpiochip[i]);
e92935e1 RS	506	}
	507
	508	return 0;
c4a0208f	509	}
e92935e1 RS	510
e92935e1 RS	511	#ifdef CONFIG_OF
e95c7c45	512	static const struct of_device_id lpc32xx_gpio_of_match[] = {
e92935e1 RS	513	{ .compatible = "nxp,lpc3220-gpio", },
	514	{ },
	515	};
	516	#endif
	517
	518	static struct platform_driver lpc32xx_gpio_driver = {
	519	.driver = {
	520	.name = "lpc32xx-gpio",
e92935e1 RS	521	.of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
	522	},
	523	.probe = lpc32xx_gpio_probe,
	524	};
	525
	526	module_platform_driver(lpc32xx_gpio_driver);