[linux.git] / drivers / gpio / gpio-ich.c

/*
 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
 *
 * Copyright (C) 2010 Extreme Engineering Solutions.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/mfd/lpc_ich.h>

#define DRV_NAME "gpio_ich"

/*
 * GPIO register offsets in GPIO I/O space.
 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
 * LVLx registers.  Logic in the read/write functions takes a register and
 * an absolute bit number and determines the proper register offset and bit
 * number in that register.  For example, to read the value of GPIO bit 50
 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
 * bit 18 (50%32).
 */
enum GPIO_REG {
	GPIO_USE_SEL = 0,
	GPIO_IO_SEL,
	GPIO_LVL,
	GPO_BLINK
};

static const u8 ichx_regs[4][3] = {
	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
	{0x18, 0x18, 0x18},	/* BLINK offset */
};

static const u8 ichx_reglen[3] = {
	0x30, 0x10, 0x10,
};

static const u8 avoton_regs[4][3] = {
	{0x00, 0x80, 0x00},
	{0x04, 0x84, 0x00},
	{0x08, 0x88, 0x00},
};

static const u8 avoton_reglen[3] = {
	0x10, 0x10, 0x00,
};

#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)

struct ichx_desc {
	/* Max GPIO pins the chipset can have */
	uint ngpio;

	/* chipset registers */
	const u8 (*regs)[3];
	const u8 *reglen;

	/* GPO_BLINK is available on this chipset */
	bool have_blink;

	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	bool uses_gpe0;

	/* USE_SEL is bogus on some chipsets, eg 3100 */
	u32 use_sel_ignore[3];

	/* Some chipsets have quirks, let these use their own request/get */
	int (*request)(struct gpio_chip *chip, unsigned offset);
	int (*get)(struct gpio_chip *chip, unsigned offset);

	/*
	 * Some chipsets don't let reading output values on GPIO_LVL register
	 * this option allows driver caching written output values
	 */
	bool use_outlvl_cache;
};

static struct {
	spinlock_t lock;
	struct platform_device *dev;
	struct gpio_chip chip;
	struct resource *gpio_base;	/* GPIO IO base */
	struct resource *pm_base;	/* Power Mangagment IO base */
	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
	u8 use_gpio;		/* Which GPIO groups are usable */
	int outlvl_cache[3];	/* cached output values */
} ichx_priv;

static int modparam_gpiobase = -1;	/* dynamic */
module_param_named(gpiobase, modparam_gpiobase, int, 0444);
MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
			   "which is the default.");

static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
{
	unsigned long flags;
	u32 data, tmp;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;
	int ret = 0;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		data = ichx_priv.outlvl_cache[reg_nr];
	else
		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
				 ichx_priv.gpio_base);

	if (val)
		data |= 1 << bit;
	else
		data &= ~(1 << bit);
	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);
	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		ichx_priv.outlvl_cache[reg_nr] = data;

	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			ichx_priv.gpio_base);
	if (verify && data != tmp)
		ret = -EPERM;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return ret;
}

static int ichx_read_bit(int reg, unsigned nr)
{
	unsigned long flags;
	u32 data;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
			 ichx_priv.gpio_base);

	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
		data = ichx_priv.outlvl_cache[reg_nr] | data;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return data & (1 << bit) ? 1 : 0;
}

static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
{
	return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
}

static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
{
	return ichx_read_bit(GPIO_IO_SEL, nr) ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
}

static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	/*
	 * Try setting pin as an input and verify it worked since many pins
	 * are output-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
					int val)
{
	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
	if (nr < 32 && ichx_priv.desc->have_blink)
		ichx_write_bit(GPO_BLINK, nr, 0, 0);

	/* Set GPIO output value. */
	ichx_write_bit(GPIO_LVL, nr, val, 0);

	/*
	 * Try setting pin as an output and verify it worked since many pins
	 * are input-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	return ichx_read_bit(GPIO_LVL, nr);
}

static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	unsigned long flags;
	u32 data;

	/*
	 * GPI 0 - 15 need to be read from the power management registers on
	 * a ICH6/3100 bridge.
	 */
	if (nr < 16) {
		if (!ichx_priv.pm_base)
			return -ENXIO;

		spin_lock_irqsave(&ichx_priv.lock, flags);

		/* GPI 0 - 15 are latched, write 1 to clear*/
		ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
		data = ICHX_READ(0, ichx_priv.pm_base);

		spin_unlock_irqrestore(&ichx_priv.lock, flags);

		return (data >> 16) & (1 << nr) ? 1 : 0;
	} else {
		return ichx_gpio_get(chip, nr);
	}
}

static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	if (!ichx_gpio_check_available(chip, nr))
		return -ENXIO;

	/*
	 * Note we assume the BIOS properly set a bridge's USE value.  Some
	 * chips (eg Intel 3100) have bogus USE values though, so first see if
	 * the chipset's USE value can be trusted for this specific bit.
	 * If it can't be trusted, assume that the pin can be used as a GPIO.
	 */
	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
		return 0;

	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
}

static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	/*
	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	 * bridge as they are controlled by USE register bits 0 and 1.  See
	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	 * additional info.
	 */
	if (nr == 16 || nr == 17)
		nr -= 16;

	return ichx_gpio_request(chip, nr);
}

static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
{
	ichx_write_bit(GPIO_LVL, nr, val, 0);
}

static void ichx_gpiolib_setup(struct gpio_chip *chip)
{
	chip->owner = THIS_MODULE;
	chip->label = DRV_NAME;
	chip->parent = &ichx_priv.dev->dev;

	/* Allow chip-specific overrides of request()/get() */
	chip->request = ichx_priv.desc->request ?
		ichx_priv.desc->request : ichx_gpio_request;
	chip->get = ichx_priv.desc->get ?
		ichx_priv.desc->get : ichx_gpio_get;

	chip->set = ichx_gpio_set;
	chip->get_direction = ichx_gpio_get_direction;
	chip->direction_input = ichx_gpio_direction_input;
	chip->direction_output = ichx_gpio_direction_output;
	chip->base = modparam_gpiobase;
	chip->ngpio = ichx_priv.desc->ngpio;
	chip->can_sleep = false;
	chip->dbg_show = NULL;
}

/* ICH6-based, 631xesb-based */
static struct ichx_desc ich6_desc = {
	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Intel 3100 */
static struct ichx_desc i3100_desc = {
	/*
	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
	 * Datasheet for more info.
	 */
	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},

	/* The 3100 needs fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH7 and ICH8-based */
static struct ichx_desc ich7_desc = {
	.ngpio = 50,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH9-based */
static struct ichx_desc ich9_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
static struct ichx_desc ich10_cons_desc = {
	.ngpio = 61,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};
static struct ichx_desc ich10_corp_desc = {
	.ngpio = 72,
	.have_blink = true,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Intel 5 series, 6 series, 3400 series, and C200 series */
static struct ichx_desc intel5_desc = {
	.ngpio = 76,
	.regs = ichx_regs,
	.reglen = ichx_reglen,
};

/* Avoton */
static struct ichx_desc avoton_desc = {
	/* Avoton has only 59 GPIOs, but we assume the first set of register
	 * (Core) has 32 instead of 31 to keep gpio-ich compliance
	 */
	.ngpio = 60,
	.regs = avoton_regs,
	.reglen = avoton_reglen,
	.use_outlvl_cache = true,
};

static int ichx_gpio_request_regions(struct device *dev,
	struct resource *res_base, const char *name, u8 use_gpio)
{
	int i;

	if (!res_base || !res_base->start || !res_base->end)
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
		if (!(use_gpio & (1 << i)))
			continue;
		if (!devm_request_region(dev,
				res_base->start + ichx_priv.desc->regs[0][i],
				ichx_priv.desc->reglen[i], name))
			return -EBUSY;
	}
	return 0;
}

static int ichx_gpio_probe(struct platform_device *pdev)
{
	struct resource *res_base, *res_pm;
	int err;
	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);

	if (!ich_info)
		return -ENODEV;

	ichx_priv.dev = pdev;

	switch (ich_info->gpio_version) {
	case ICH_I3100_GPIO:
		ichx_priv.desc = &i3100_desc;
		break;
	case ICH_V5_GPIO:
		ichx_priv.desc = &intel5_desc;
		break;
	case ICH_V6_GPIO:
		ichx_priv.desc = &ich6_desc;
		break;
	case ICH_V7_GPIO:
		ichx_priv.desc = &ich7_desc;
		break;
	case ICH_V9_GPIO:
		ichx_priv.desc = &ich9_desc;
		break;
	case ICH_V10CORP_GPIO:
		ichx_priv.desc = &ich10_corp_desc;
		break;
	case ICH_V10CONS_GPIO:
		ichx_priv.desc = &ich10_cons_desc;
		break;
	case AVOTON_GPIO:
		ichx_priv.desc = &avoton_desc;
		break;
	default:
		return -ENODEV;
	}

	spin_lock_init(&ichx_priv.lock);
	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
	ichx_priv.use_gpio = ich_info->use_gpio;
	err = ichx_gpio_request_regions(&pdev->dev, res_base, pdev->name,
					ichx_priv.use_gpio);
	if (err)
		return err;

	ichx_priv.gpio_base = res_base;

	/*
	 * If necessary, determine the I/O address of ACPI/power management
	 * registers which are needed to read the the GPE0 register for GPI pins
	 * 0 - 15 on some chipsets.
	 */
	if (!ichx_priv.desc->uses_gpe0)
		goto init;

	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	if (!res_pm) {
		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
		goto init;
	}

	if (!devm_request_region(&pdev->dev, res_pm->start,
			resource_size(res_pm), pdev->name)) {
		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
		goto init;
	}

	ichx_priv.pm_base = res_pm;

init:
	ichx_gpiolib_setup(&ichx_priv.chip);
	err = gpiochip_add_data(&ichx_priv.chip, NULL);
	if (err) {
		pr_err("Failed to register GPIOs\n");
		return err;
	}

	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);

	return 0;
}

static int ichx_gpio_remove(struct platform_device *pdev)
{
	gpiochip_remove(&ichx_priv.chip);

	return 0;
}

static struct platform_driver ichx_gpio_driver = {
	.driver		= {
		.name	= DRV_NAME,
	},
	.probe		= ichx_gpio_probe,
	.remove		= ichx_gpio_remove,
};

module_platform_driver(ichx_gpio_driver);

MODULE_AUTHOR("Peter Tyser <[email protected]>");
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:"DRV_NAME);
Commit	Line	Data
6ed9f9c4	1	/*
3b923189	2	* Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
6ed9f9c4 PT	3	*
	4	* Copyright (C) 2010 Extreme Engineering Solutions.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
8a06b08e	23	#include <linux/ioport.h>
6ed9f9c4 PT	24	#include <linux/module.h>
	25	#include <linux/pci.h>
	26	#include <linux/gpio.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/mfd/lpc_ich.h>
	29
	30	#define DRV_NAME "gpio_ich"
	31
	32	/*
	33	* GPIO register offsets in GPIO I/O space.
	34	* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
	35	* LVLx registers. Logic in the read/write functions takes a register and
	36	* an absolute bit number and determines the proper register offset and bit
	37	* number in that register. For example, to read the value of GPIO bit 50
	38	* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
	39	* bit 18 (50%32).
	40	*/
	41	enum GPIO_REG {
	42	GPIO_USE_SEL = 0,
	43	GPIO_IO_SEL,
	44	GPIO_LVL,
7f6569f5	45	GPO_BLINK
6ed9f9c4 PT	46	};
6ed9f9c4 PT	47
7f6569f5	48	static const u8 ichx_regs[4][3] = {
6ed9f9c4 PT	49	{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
	50	{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
	51	{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
7f6569f5	52	{0x18, 0x18, 0x18}, /* BLINK offset */
6ed9f9c4 PT	53	};
6ed9f9c4 PT	54
4f600ada JD	55	static const u8 ichx_reglen[3] = {
	56	0x30, 0x10, 0x10,
	57	};
	58
3b923189 VD	59	static const u8 avoton_regs[4][3] = {
	60	{0x00, 0x80, 0x00},
	61	{0x04, 0x84, 0x00},
	62	{0x08, 0x88, 0x00},
	63	};
	64
	65	static const u8 avoton_reglen[3] = {
	66	0x10, 0x10, 0x00,
	67	};
	68
6ed9f9c4 PT	69	#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
	70	#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
	71
	72	struct ichx_desc {
	73	/* Max GPIO pins the chipset can have */
	74	uint ngpio;
	75
bb62a35b VD	76	/* chipset registers */
	77	const u8 (*regs)[3];
	78	const u8 *reglen;
	79
ba7f74fe VD	80	/* GPO_BLINK is available on this chipset */
	81	bool have_blink;
	82
6ed9f9c4 PT	83	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	84	bool uses_gpe0;
	85
	86	/* USE_SEL is bogus on some chipsets, eg 3100 */
	87	u32 use_sel_ignore[3];
	88
	89	/* Some chipsets have quirks, let these use their own request/get */
	90	int (request)(struct gpio_chip chip, unsigned offset);
	91	int (get)(struct gpio_chip chip, unsigned offset);
e6540f33 VD	92
	93	/*
	94	* Some chipsets don't let reading output values on GPIO_LVL register
	95	* this option allows driver caching written output values
	96	*/
	97	bool use_outlvl_cache;
6ed9f9c4 PT	98	};
	99
	100	static struct {
	101	spinlock_t lock;
	102	struct platform_device *dev;
	103	struct gpio_chip chip;
	104	struct resource gpio_base; / GPIO IO base */
	105	struct resource pm_base; / Power Mangagment IO base */
	106	struct ichx_desc desc; / Pointer to chipset-specific description */
	107	u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
4f600ada	108	u8 use_gpio; /* Which GPIO groups are usable */
e6540f33	109	int outlvl_cache[3]; /* cached output values */
6ed9f9c4 PT	110	} ichx_priv;
	111
	112	static int modparam_gpiobase = -1; /* dynamic */
	113	module_param_named(gpiobase, modparam_gpiobase, int, 0444);
	114	MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
	115	"which is the default.");
	116
	117	static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
	118	{
	119	unsigned long flags;
	120	u32 data, tmp;
	121	int reg_nr = nr / 32;
	122	int bit = nr & 0x1f;
	123	int ret = 0;
	124
	125	spin_lock_irqsave(&ichx_priv.lock, flags);
	126
e6540f33 VD	127	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	128	data = ichx_priv.outlvl_cache[reg_nr];
	129	else
	130	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
	131	ichx_priv.gpio_base);
	132
6ed9f9c4 PT	133	if (val)
	134	data \|= 1 << bit;
	135	else
	136	data &= ~(1 << bit);
bb62a35b VD	137	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	138	ichx_priv.gpio_base);
e6540f33 VD	139	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	140	ichx_priv.outlvl_cache[reg_nr] = data;
	141
bb62a35b VD	142	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	143	ichx_priv.gpio_base);
6ed9f9c4 PT	144	if (verify && data != tmp)
	145	ret = -EPERM;
	146
	147	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	148
	149	return ret;
	150	}
	151
	152	static int ichx_read_bit(int reg, unsigned nr)
	153	{
	154	unsigned long flags;
	155	u32 data;
	156	int reg_nr = nr / 32;
	157	int bit = nr & 0x1f;
	158
	159	spin_lock_irqsave(&ichx_priv.lock, flags);
	160
bb62a35b VD	161	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
bb62a35b VD	162	ichx_priv.gpio_base);
6ed9f9c4	163
e6540f33 VD	164	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
	165	data = ichx_priv.outlvl_cache[reg_nr] \| data;
	166
6ed9f9c4 PT	167	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	168
	169	return data & (1 << bit) ? 1 : 0;
	170	}
	171
e97f9b52	172	static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
4f600ada	173	{
61d793bb	174	return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
4f600ada JD	175	}
4f600ada JD	176
62e08f25 AS	177	static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr)
	178	{
	179	return ichx_read_bit(GPIO_IO_SEL, nr) ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
	180	}
	181
6ed9f9c4 PT	182	static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	183	{
	184	/*
	185	* Try setting pin as an input and verify it worked since many pins
	186	* are output-only.
	187	*/
	188	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
	189	return -EINVAL;
	190
	191	return 0;
	192	}
	193
	194	static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	195	int val)
	196	{
7f6569f5	197	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
ba7f74fe	198	if (nr < 32 && ichx_priv.desc->have_blink)
7f6569f5 VD	199	ichx_write_bit(GPO_BLINK, nr, 0, 0);
7f6569f5 VD	200
6ed9f9c4 PT	201	/* Set GPIO output value. */
	202	ichx_write_bit(GPIO_LVL, nr, val, 0);
	203
	204	/*
	205	* Try setting pin as an output and verify it worked since many pins
	206	* are input-only.
	207	*/
	208	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
	209	return -EINVAL;
	210
	211	return 0;
	212	}
	213
	214	static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
	215	{
	216	return ichx_read_bit(GPIO_LVL, nr);
	217	}
	218
	219	static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
	220	{
	221	unsigned long flags;
	222	u32 data;
	223
	224	/*
	225	* GPI 0 - 15 need to be read from the power management registers on
	226	* a ICH6/3100 bridge.
	227	*/
	228	if (nr < 16) {
	229	if (!ichx_priv.pm_base)
	230	return -ENXIO;
	231
	232	spin_lock_irqsave(&ichx_priv.lock, flags);
	233
	234	/* GPI 0 - 15 are latched, write 1 to clear*/
	235	ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
	236	data = ICHX_READ(0, ichx_priv.pm_base);
	237
	238	spin_unlock_irqrestore(&ichx_priv.lock, flags);
	239
	240	return (data >> 16) & (1 << nr) ? 1 : 0;
	241	} else {
	242	return ichx_gpio_get(chip, nr);
	243	}
	244	}
	245
	246	static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
	247	{
25f27db4 JD	248	if (!ichx_gpio_check_available(chip, nr))
	249	return -ENXIO;
	250
6ed9f9c4 PT	251	/*
	252	* Note we assume the BIOS properly set a bridge's USE value. Some
	253	* chips (eg Intel 3100) have bogus USE values though, so first see if
	254	* the chipset's USE value can be trusted for this specific bit.
	255	* If it can't be trusted, assume that the pin can be used as a GPIO.
	256	*/
	257	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
2ab3a749	258	return 0;
6ed9f9c4 PT	259
	260	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
	261	}
	262
	263	static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
	264	{
	265	/*
	266	* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	267	* bridge as they are controlled by USE register bits 0 and 1. See
	268	* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	269	* additional info.
	270	*/
	271	if (nr == 16 \|\| nr == 17)
	272	nr -= 16;
	273
	274	return ichx_gpio_request(chip, nr);
	275	}
	276
	277	static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
	278	{
	279	ichx_write_bit(GPIO_LVL, nr, val, 0);
	280	}
	281
3836309d	282	static void ichx_gpiolib_setup(struct gpio_chip *chip)
6ed9f9c4 PT	283	{
	284	chip->owner = THIS_MODULE;
	285	chip->label = DRV_NAME;
58383c78	286	chip->parent = &ichx_priv.dev->dev;
6ed9f9c4 PT	287
	288	/* Allow chip-specific overrides of request()/get() */
	289	chip->request = ichx_priv.desc->request ?
	290	ichx_priv.desc->request : ichx_gpio_request;
	291	chip->get = ichx_priv.desc->get ?
	292	ichx_priv.desc->get : ichx_gpio_get;
	293
	294	chip->set = ichx_gpio_set;
62e08f25	295	chip->get_direction = ichx_gpio_get_direction;
6ed9f9c4 PT	296	chip->direction_input = ichx_gpio_direction_input;
	297	chip->direction_output = ichx_gpio_direction_output;
	298	chip->base = modparam_gpiobase;
	299	chip->ngpio = ichx_priv.desc->ngpio;
9fb1f39e	300	chip->can_sleep = false;
6ed9f9c4 PT	301	chip->dbg_show = NULL;
	302	}
	303
	304	/* ICH6-based, 631xesb-based */
	305	static struct ichx_desc ich6_desc = {
	306	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	307	.request = ich6_gpio_request,
	308	.get = ich6_gpio_get,
	309
	310	/* GPIO 0-15 are read in the GPE0_STS PM register */
	311	.uses_gpe0 = true,
	312
	313	.ngpio = 50,
ba7f74fe	314	.have_blink = true,
a7008ee1 VD	315	.regs = ichx_regs,
a7008ee1 VD	316	.reglen = ichx_reglen,
6ed9f9c4 PT	317	};
	318
	319	/* Intel 3100 */
	320	static struct ichx_desc i3100_desc = {
	321	/*
	322	* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	323	* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
	324	* Datasheet for more info.
	325	*/
	326	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
	327
	328	/* The 3100 needs fixups for GPIO 0 - 17 */
	329	.request = ich6_gpio_request,
	330	.get = ich6_gpio_get,
	331
	332	/* GPIO 0-15 are read in the GPE0_STS PM register */
	333	.uses_gpe0 = true,
	334
	335	.ngpio = 50,
a7008ee1 VD	336	.regs = ichx_regs,
a7008ee1 VD	337	.reglen = ichx_reglen,
6ed9f9c4 PT	338	};
	339
	340	/* ICH7 and ICH8-based */
	341	static struct ichx_desc ich7_desc = {
	342	.ngpio = 50,
ba7f74fe	343	.have_blink = true,
bb62a35b VD	344	.regs = ichx_regs,
bb62a35b VD	345	.reglen = ichx_reglen,
6ed9f9c4 PT	346	};
	347
	348	/* ICH9-based */
	349	static struct ichx_desc ich9_desc = {
	350	.ngpio = 61,
ba7f74fe	351	.have_blink = true,
bb62a35b VD	352	.regs = ichx_regs,
bb62a35b VD	353	.reglen = ichx_reglen,
6ed9f9c4 PT	354	};
	355
	356	/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
	357	static struct ichx_desc ich10_cons_desc = {
	358	.ngpio = 61,
ba7f74fe	359	.have_blink = true,
bb62a35b VD	360	.regs = ichx_regs,
bb62a35b VD	361	.reglen = ichx_reglen,
6ed9f9c4 PT	362	};
	363	static struct ichx_desc ich10_corp_desc = {
	364	.ngpio = 72,
ba7f74fe	365	.have_blink = true,
bb62a35b VD	366	.regs = ichx_regs,
bb62a35b VD	367	.reglen = ichx_reglen,
6ed9f9c4 PT	368	};
	369
	370	/* Intel 5 series, 6 series, 3400 series, and C200 series */
	371	static struct ichx_desc intel5_desc = {
	372	.ngpio = 76,
bb62a35b VD	373	.regs = ichx_regs,
bb62a35b VD	374	.reglen = ichx_reglen,
6ed9f9c4 PT	375	};
6ed9f9c4 PT	376
3b923189 VD	377	/* Avoton */
	378	static struct ichx_desc avoton_desc = {
	379	/* Avoton has only 59 GPIOs, but we assume the first set of register
	380	* (Core) has 32 instead of 31 to keep gpio-ich compliance
	381	*/
	382	.ngpio = 60,
	383	.regs = avoton_regs,
	384	.reglen = avoton_reglen,
	385	.use_outlvl_cache = true,
	386	};
	387
8a06b08e WBG	388	static int ichx_gpio_request_regions(struct device *dev,
8a06b08e WBG	389	struct resource res_base, const char name, u8 use_gpio)
4f600ada JD	390	{
	391	int i;
	392
	393	if (!res_base \|\| !res_base->start \|\| !res_base->end)
	394	return -ENODEV;
	395
bb62a35b	396	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
4f600ada JD	397	if (!(use_gpio & (1 << i)))
4f600ada JD	398	continue;
8a06b08e	399	if (!devm_request_region(dev,
bb62a35b VD	400	res_base->start + ichx_priv.desc->regs[0][i],
bb62a35b VD	401	ichx_priv.desc->reglen[i], name))
8a06b08e	402	return -EBUSY;
4f600ada JD	403	}
4f600ada JD	404	return 0;
4f600ada JD	405	}
4f600ada JD	406
3836309d	407	static int ichx_gpio_probe(struct platform_device *pdev)
6ed9f9c4 PT	408	{
	409	struct resource res_base, res_pm;
	410	int err;
e56aee18	411	struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
6ed9f9c4 PT	412
	413	if (!ich_info)
	414	return -ENODEV;
	415
	416	ichx_priv.dev = pdev;
	417
	418	switch (ich_info->gpio_version) {
	419	case ICH_I3100_GPIO:
	420	ichx_priv.desc = &i3100_desc;
	421	break;
	422	case ICH_V5_GPIO:
	423	ichx_priv.desc = &intel5_desc;
	424	break;
	425	case ICH_V6_GPIO:
	426	ichx_priv.desc = &ich6_desc;
	427	break;
	428	case ICH_V7_GPIO:
	429	ichx_priv.desc = &ich7_desc;
	430	break;
	431	case ICH_V9_GPIO:
	432	ichx_priv.desc = &ich9_desc;
	433	break;
	434	case ICH_V10CORP_GPIO:
	435	ichx_priv.desc = &ich10_corp_desc;
	436	break;
	437	case ICH_V10CONS_GPIO:
	438	ichx_priv.desc = &ich10_cons_desc;
	439	break;
3b923189 VD	440	case AVOTON_GPIO:
	441	ichx_priv.desc = &avoton_desc;
	442	break;
6ed9f9c4 PT	443	default:
	444	return -ENODEV;
	445	}
	446
d39a948f	447	spin_lock_init(&ichx_priv.lock);
6ed9f9c4	448	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
4f600ada	449	ichx_priv.use_gpio = ich_info->use_gpio;
8a06b08e	450	err = ichx_gpio_request_regions(&pdev->dev, res_base, pdev->name,
4f600ada JD	451	ichx_priv.use_gpio);
	452	if (err)
	453	return err;
6ed9f9c4 PT	454
	455	ichx_priv.gpio_base = res_base;
	456
	457	/*
	458	* If necessary, determine the I/O address of ACPI/power management
	459	* registers which are needed to read the the GPE0 register for GPI pins
	460	* 0 - 15 on some chipsets.
	461	*/
	462	if (!ichx_priv.desc->uses_gpe0)
	463	goto init;
	464
	465	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	466	if (!res_pm) {
	467	pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
	468	goto init;
	469	}
	470
8a06b08e WBG	471	if (!devm_request_region(&pdev->dev, res_pm->start,
8a06b08e WBG	472	resource_size(res_pm), pdev->name)) {
6ed9f9c4 PT	473	pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
	474	goto init;
	475	}
	476
	477	ichx_priv.pm_base = res_pm;
	478
	479	init:
	480	ichx_gpiolib_setup(&ichx_priv.chip);
4eab22e7	481	err = gpiochip_add_data(&ichx_priv.chip, NULL);
6ed9f9c4 PT	482	if (err) {
6ed9f9c4 PT	483	pr_err("Failed to register GPIOs\n");
8a06b08e	484	return err;
6ed9f9c4 PT	485	}
	486
	487	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	488	ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
	489
	490	return 0;
6ed9f9c4 PT	491	}
6ed9f9c4 PT	492
206210ce	493	static int ichx_gpio_remove(struct platform_device *pdev)
6ed9f9c4	494	{
9f5132ae	495	gpiochip_remove(&ichx_priv.chip);
6ed9f9c4	496
6ed9f9c4 PT	497	return 0;
	498	}
	499
	500	static struct platform_driver ichx_gpio_driver = {
	501	.driver = {
6ed9f9c4 PT	502	.name = DRV_NAME,
	503	},
	504	.probe = ichx_gpio_probe,
8283c4ff	505	.remove = ichx_gpio_remove,
6ed9f9c4 PT	506	};
	507
	508	module_platform_driver(ichx_gpio_driver);
	509
	510	MODULE_AUTHOR("Peter Tyser <[email protected]>");
	511	MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
	512	MODULE_LICENSE("GPL");
	513	MODULE_ALIAS("platform:"DRV_NAME);