[linux.git] / drivers / gpio / gpio-ep93xx.c

/*
 * Generic EP93xx GPIO handling
 *
 * Copyright (c) 2008 Ryan Mallon
 * Copyright (c) 2011 H Hartley Sweeten <[email protected]>
 *
 * Based on code originally from:
 *  linux/arch/arm/mach-ep93xx/core.c
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
/* FIXME: this is here for gpio_to_irq() - get rid of this! */
#include <linux/gpio.h>

#include <mach/hardware.h>
#include <mach/gpio-ep93xx.h>

#define irq_to_gpio(irq)	((irq) - gpio_to_irq(0))

struct ep93xx_gpio {
	void __iomem		*mmio_base;
	struct gpio_chip	gc[8];
};

/*************************************************************************
 * Interrupt handling for EP93xx on-chip GPIOs
 *************************************************************************/
static unsigned char gpio_int_unmasked[3];
static unsigned char gpio_int_enabled[3];
static unsigned char gpio_int_type1[3];
static unsigned char gpio_int_type2[3];
static unsigned char gpio_int_debounce[3];

/* Port ordering is: A B F */
static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };

static void ep93xx_gpio_update_int_params(unsigned port)
{
	BUG_ON(port > 2);

	writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));

	writeb_relaxed(gpio_int_type2[port],
		EP93XX_GPIO_REG(int_type2_register_offset[port]));

	writeb_relaxed(gpio_int_type1[port],
		EP93XX_GPIO_REG(int_type1_register_offset[port]));

	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
		EP93XX_GPIO_REG(int_en_register_offset[port]));
}

static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (enable)
		gpio_int_debounce[port] |= port_mask;
	else
		gpio_int_debounce[port] &= ~port_mask;

	writeb(gpio_int_debounce[port],
		EP93XX_GPIO_REG(int_debounce_register_offset[port]));
}

static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
{
	unsigned char status;
	int i;

	status = readb(EP93XX_GPIO_A_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}

	status = readb(EP93XX_GPIO_B_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}
}

static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
{
	/*
	 * map discontiguous hw irq range to continuous sw irq range:
	 *
	 *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	 */
	unsigned int irq = irq_desc_get_irq(desc);
	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;

	generic_handle_irq(gpio_irq);
}

static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
		ep93xx_gpio_update_int_params(port);
	}

	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */

	gpio_int_unmasked[port] &= ~port_mask;
	ep93xx_gpio_update_int_params(port);

	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;

	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	ep93xx_gpio_update_int_params(port);
}

static void ep93xx_gpio_irq_unmask(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;

	gpio_int_unmasked[port] |= 1 << (line & 7);
	ep93xx_gpio_update_int_params(port);
}

/*
 * gpio_int_type1 controls whether the interrupt is level (0) or
 * edge (1) triggered, while gpio_int_type2 controls whether it
 * triggers on low/falling (0) or high/rising (1).
 */
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	const int gpio = irq_to_gpio(d->irq);
	const int port = gpio >> 3;
	const int port_mask = 1 << (gpio & 7);
	irq_flow_handler_t handler;

	gpio_direction_input(gpio);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_edge_irq;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] |= port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] &= ~port_mask;
		handler = handle_level_irq;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		gpio_int_type1[port] |= port_mask;
		/* set initial polarity based on current input level */
		if (gpio_get_value(gpio))
			gpio_int_type2[port] &= ~port_mask; /* falling */
		else
			gpio_int_type2[port] |= port_mask; /* rising */
		handler = handle_edge_irq;
		break;
	default:
		return -EINVAL;
	}

	irq_set_handler_locked(d, handler);

	gpio_int_enabled[port] |= port_mask;

	ep93xx_gpio_update_int_params(port);

	return 0;
}

static struct irq_chip ep93xx_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= ep93xx_gpio_irq_ack,
	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
	.irq_mask	= ep93xx_gpio_irq_mask,
	.irq_unmask	= ep93xx_gpio_irq_unmask,
	.irq_set_type	= ep93xx_gpio_irq_type,
};

static void ep93xx_gpio_init_irq(void)
{
	int gpio_irq;

	for (gpio_irq = gpio_to_irq(0);
	     gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
		irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
					 handle_level_irq);
		irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
	}

	irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
				ep93xx_gpio_ab_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
				ep93xx_gpio_f_irq_handler);
	irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
				ep93xx_gpio_f_irq_handler);
}


/*************************************************************************
 * gpiolib interface for EP93xx on-chip GPIOs
 *************************************************************************/
struct ep93xx_gpio_bank {
	const char	*label;
	int		data;
	int		dir;
	int		base;
	bool		has_debounce;
};

#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce)	\
	{							\
		.label		= _label,			\
		.data		= _data,			\
		.dir		= _dir,				\
		.base		= _base,			\
		.has_debounce	= _debounce,			\
	}

static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
};

static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
				    unsigned offset, unsigned debounce)
{
	int gpio = chip->base + offset;
	int irq = gpio_to_irq(gpio);

	if (irq < 0)
		return -EINVAL;

	ep93xx_gpio_int_debounce(irq, debounce ? true : false);

	return 0;
}

/*
 * Map GPIO A0..A7  (0..7)  to irq 64..71,
 *          B0..B7  (7..15) to irq 72..79, and
 *          F0..F7 (16..24) to irq 80..87.
 */
static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	int gpio = chip->base + offset;

	if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
		return -EINVAL;

	return 64 + gpio;
}

static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
	void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
{
	void __iomem *data = mmio_base + bank->data;
	void __iomem *dir =  mmio_base + bank->dir;
	int err;

	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
	if (err)
		return err;

	gc->label = bank->label;
	gc->base = bank->base;

	if (bank->has_debounce) {
		gc->set_debounce = ep93xx_gpio_set_debounce;
		gc->to_irq = ep93xx_gpio_to_irq;
	}

	return devm_gpiochip_add_data(dev, gc, NULL);
}

static int ep93xx_gpio_probe(struct platform_device *pdev)
{
	struct ep93xx_gpio *ep93xx_gpio;
	struct resource *res;
	int i;
	struct device *dev = &pdev->dev;

	ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL);
	if (!ep93xx_gpio)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(ep93xx_gpio->mmio_base))
		return PTR_ERR(ep93xx_gpio->mmio_base);

	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
		struct gpio_chip *gc = &ep93xx_gpio->gc[i];
		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];

		if (ep93xx_gpio_add_bank(gc, &pdev->dev,
					 ep93xx_gpio->mmio_base, bank))
			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
				bank->label);
	}

	ep93xx_gpio_init_irq();

	return 0;
}

static struct platform_driver ep93xx_gpio_driver = {
	.driver		= {
		.name	= "gpio-ep93xx",
	},
	.probe		= ep93xx_gpio_probe,
};

static int __init ep93xx_gpio_init(void)
{
	return platform_driver_register(&ep93xx_gpio_driver);
}
postcore_initcall(ep93xx_gpio_init);

MODULE_AUTHOR("Ryan Mallon <[email protected]> "
		"H Hartley Sweeten <[email protected]>");
MODULE_DESCRIPTION("EP93XX GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b685004f	1	/*
b685004f RM	2	* Generic EP93xx GPIO handling
b685004f RM	3	*
1c5454ee	4	* Copyright (c) 2008 Ryan Mallon
1e4c8842	5	* Copyright (c) 2011 H Hartley Sweeten <[email protected]>
b685004f RM	6	*
	7	* Based on code originally from:
	8	* linux/arch/arm/mach-ep93xx/core.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/init.h>
bb207ef1	16	#include <linux/module.h>
1e4c8842	17	#include <linux/platform_device.h>
fced80c7	18	#include <linux/io.h>
595c050d	19	#include <linux/irq.h>
1e4c8842	20	#include <linux/slab.h>
0f4630f3 LW	21	#include <linux/gpio/driver.h>
	22	/* FIXME: this is here for gpio_to_irq() - get rid of this! */
	23	#include <linux/gpio.h>
b685004f	24
ddf4f3d9	25	#include <mach/hardware.h>
bd5f12a2 LW	26	#include <mach/gpio-ep93xx.h>
	27
	28	#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
b685004f	29
1e4c8842 HS	30	struct ep93xx_gpio {
1e4c8842 HS	31	void __iomem *mmio_base;
0f4630f3	32	struct gpio_chip gc[8];
1e4c8842 HS	33	};
1e4c8842 HS	34
d056ab78	35	/*************************************************************************
4742723c	36	* Interrupt handling for EP93xx on-chip GPIOs
d056ab78 HS	37	*************************************************************************/
	38	static unsigned char gpio_int_unmasked[3];
	39	static unsigned char gpio_int_enabled[3];
	40	static unsigned char gpio_int_type1[3];
	41	static unsigned char gpio_int_type2[3];
	42	static unsigned char gpio_int_debounce[3];
	43
	44	/* Port ordering is: A B F */
	45	static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
	46	static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
	47	static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
	48	static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
	49	static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
	50
4742723c	51	static void ep93xx_gpio_update_int_params(unsigned port)
d056ab78 HS	52	{
	53	BUG_ON(port > 2);
	54
d27e06ac	55	writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
d056ab78	56
d27e06ac	57	writeb_relaxed(gpio_int_type2[port],
d056ab78 HS	58	EP93XX_GPIO_REG(int_type2_register_offset[port]));
d056ab78 HS	59
d27e06ac	60	writeb_relaxed(gpio_int_type1[port],
d056ab78 HS	61	EP93XX_GPIO_REG(int_type1_register_offset[port]));
d056ab78 HS	62
d27e06ac	63	writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
d056ab78 HS	64	EP93XX_GPIO_REG(int_en_register_offset[port]));
	65	}
	66
5d046af0	67	static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
d056ab78 HS	68	{
	69	int line = irq_to_gpio(irq);
	70	int port = line >> 3;
	71	int port_mask = 1 << (line & 7);
	72
	73	if (enable)
	74	gpio_int_debounce[port] \|= port_mask;
	75	else
	76	gpio_int_debounce[port] &= ~port_mask;
	77
d27e06ac	78	writeb(gpio_int_debounce[port],
d056ab78 HS	79	EP93XX_GPIO_REG(int_debounce_register_offset[port]));
d056ab78 HS	80	}
d056ab78	81
bd0b9ac4	82	static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
d056ab78 HS	83	{
	84	unsigned char status;
	85	int i;
	86
d27e06ac	87	status = readb(EP93XX_GPIO_A_INT_STATUS);
d056ab78 HS	88	for (i = 0; i < 8; i++) {
	89	if (status & (1 << i)) {
	90	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
	91	generic_handle_irq(gpio_irq);
	92	}
	93	}
	94
d27e06ac	95	status = readb(EP93XX_GPIO_B_INT_STATUS);
d056ab78 HS	96	for (i = 0; i < 8; i++) {
	97	if (status & (1 << i)) {
	98	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
	99	generic_handle_irq(gpio_irq);
	100	}
	101	}
	102	}
	103
bd0b9ac4	104	static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
d056ab78 HS	105	{
d056ab78 HS	106	/*
25985edc	107	* map discontiguous hw irq range to continuous sw irq range:
d056ab78 HS	108	*
	109	* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	110	*/
e43ea7a7	111	unsigned int irq = irq_desc_get_irq(desc);
d056ab78 HS	112	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	113	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
	114
	115	generic_handle_irq(gpio_irq);
	116	}
	117
c0afc916	118	static void ep93xx_gpio_irq_ack(struct irq_data *d)
d056ab78	119	{
c0afc916	120	int line = irq_to_gpio(d->irq);
d056ab78 HS	121	int port = line >> 3;
	122	int port_mask = 1 << (line & 7);
	123
d1735a2e	124	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
d056ab78 HS	125	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	126	ep93xx_gpio_update_int_params(port);
	127	}
	128
d27e06ac	129	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
d056ab78 HS	130	}
d056ab78 HS	131
c0afc916	132	static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
d056ab78	133	{
c0afc916	134	int line = irq_to_gpio(d->irq);
d056ab78 HS	135	int port = line >> 3;
	136	int port_mask = 1 << (line & 7);
	137
d1735a2e	138	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
d056ab78 HS	139	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	140
	141	gpio_int_unmasked[port] &= ~port_mask;
	142	ep93xx_gpio_update_int_params(port);
	143
d27e06ac	144	writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
d056ab78 HS	145	}
d056ab78 HS	146
c0afc916	147	static void ep93xx_gpio_irq_mask(struct irq_data *d)
d056ab78	148	{
c0afc916	149	int line = irq_to_gpio(d->irq);
d056ab78 HS	150	int port = line >> 3;
	151
	152	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	153	ep93xx_gpio_update_int_params(port);
	154	}
	155
c0afc916	156	static void ep93xx_gpio_irq_unmask(struct irq_data *d)
d056ab78	157	{
c0afc916	158	int line = irq_to_gpio(d->irq);
d056ab78 HS	159	int port = line >> 3;
	160
	161	gpio_int_unmasked[port] \|= 1 << (line & 7);
	162	ep93xx_gpio_update_int_params(port);
	163	}
	164
	165	/*
	166	* gpio_int_type1 controls whether the interrupt is level (0) or
	167	* edge (1) triggered, while gpio_int_type2 controls whether it
	168	* triggers on low/falling (0) or high/rising (1).
	169	*/
c0afc916	170	static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
d056ab78	171	{
c0afc916	172	const int gpio = irq_to_gpio(d->irq);
d056ab78 HS	173	const int port = gpio >> 3;
d056ab78 HS	174	const int port_mask = 1 << (gpio & 7);
d1735a2e	175	irq_flow_handler_t handler;
d056ab78 HS	176
	177	gpio_direction_input(gpio);
	178
	179	switch (type) {
	180	case IRQ_TYPE_EDGE_RISING:
	181	gpio_int_type1[port] \|= port_mask;
	182	gpio_int_type2[port] \|= port_mask;
d1735a2e	183	handler = handle_edge_irq;
d056ab78 HS	184	break;
	185	case IRQ_TYPE_EDGE_FALLING:
	186	gpio_int_type1[port] \|= port_mask;
	187	gpio_int_type2[port] &= ~port_mask;
d1735a2e	188	handler = handle_edge_irq;
d056ab78 HS	189	break;
	190	case IRQ_TYPE_LEVEL_HIGH:
	191	gpio_int_type1[port] &= ~port_mask;
	192	gpio_int_type2[port] \|= port_mask;
d1735a2e	193	handler = handle_level_irq;
d056ab78 HS	194	break;
	195	case IRQ_TYPE_LEVEL_LOW:
	196	gpio_int_type1[port] &= ~port_mask;
	197	gpio_int_type2[port] &= ~port_mask;
d1735a2e	198	handler = handle_level_irq;
d056ab78 HS	199	break;
	200	case IRQ_TYPE_EDGE_BOTH:
	201	gpio_int_type1[port] \|= port_mask;
	202	/* set initial polarity based on current input level */
	203	if (gpio_get_value(gpio))
	204	gpio_int_type2[port] &= ~port_mask; /* falling */
	205	else
	206	gpio_int_type2[port] \|= port_mask; /* rising */
d1735a2e	207	handler = handle_edge_irq;
d056ab78 HS	208	break;
d056ab78 HS	209	default:
d056ab78 HS	210	return -EINVAL;
	211	}
	212
72b2a9ef	213	irq_set_handler_locked(d, handler);
d056ab78	214
d1735a2e	215	gpio_int_enabled[port] \|= port_mask;
d056ab78 HS	216
	217	ep93xx_gpio_update_int_params(port);
	218
	219	return 0;
	220	}
	221
	222	static struct irq_chip ep93xx_gpio_irq_chip = {
	223	.name = "GPIO",
c0afc916 LB	224	.irq_ack = ep93xx_gpio_irq_ack,
	225	.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
	226	.irq_mask = ep93xx_gpio_irq_mask,
	227	.irq_unmask = ep93xx_gpio_irq_unmask,
	228	.irq_set_type = ep93xx_gpio_irq_type,
d056ab78 HS	229	};
d056ab78 HS	230
1e4c8842	231	static void ep93xx_gpio_init_irq(void)
d056ab78 HS	232	{
	233	int gpio_irq;
	234
	235	for (gpio_irq = gpio_to_irq(0);
	236	gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
f38c02f3 TG	237	irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
f38c02f3 TG	238	handle_level_irq);
23393d49	239	irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
d056ab78 HS	240	}
d056ab78 HS	241
6845664a TG	242	irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
	243	ep93xx_gpio_ab_irq_handler);
	244	irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
	245	ep93xx_gpio_f_irq_handler);
	246	irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
	247	ep93xx_gpio_f_irq_handler);
	248	irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
	249	ep93xx_gpio_f_irq_handler);
	250	irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
	251	ep93xx_gpio_f_irq_handler);
	252	irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
	253	ep93xx_gpio_f_irq_handler);
	254	irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
	255	ep93xx_gpio_f_irq_handler);
	256	irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
	257	ep93xx_gpio_f_irq_handler);
	258	irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
	259	ep93xx_gpio_f_irq_handler);
d056ab78 HS	260	}
	261
	262
	263	/*************************************************************************
	264	* gpiolib interface for EP93xx on-chip GPIOs
	265	*************************************************************************/
1e4c8842 HS	266	struct ep93xx_gpio_bank {
	267	const char *label;
	268	int data;
	269	int dir;
	270	int base;
	271	bool has_debounce;
b685004f RM	272	};
b685004f RM	273
1e4c8842 HS	274	#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
	275	{ \
	276	.label = _label, \
	277	.data = _data, \
	278	.dir = _dir, \
	279	.base = _base, \
	280	.has_debounce = _debounce, \
	281	}
b685004f	282
1e4c8842 HS	283	static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
	284	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
	285	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
	286	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
	287	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
	288	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
	289	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
	290	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
	291	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
	292	};
	293
	294	static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
	295	unsigned offset, unsigned debounce)
b685004f	296	{
1e4c8842 HS	297	int gpio = chip->base + offset;
1e4c8842 HS	298	int irq = gpio_to_irq(gpio);
b685004f	299
1e4c8842 HS	300	if (irq < 0)
	301	return -EINVAL;
	302
	303	ep93xx_gpio_int_debounce(irq, debounce ? true : false);
b685004f RM	304
	305	return 0;
	306	}
	307
257af9f9 LW	308	/*
	309	* Map GPIO A0..A7 (0..7) to irq 64..71,
	310	* B0..B7 (7..15) to irq 72..79, and
	311	* F0..F7 (16..24) to irq 80..87.
	312	*/
	313	static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	314	{
	315	int gpio = chip->base + offset;
	316
	317	if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
	318	return -EINVAL;
	319
	320	return 64 + gpio;
	321	}
	322
0f4630f3	323	static int ep93xx_gpio_add_bank(struct gpio_chip gc, struct device dev,
1e4c8842	324	void __iomem mmio_base, struct ep93xx_gpio_bank bank)
b685004f	325	{
1e4c8842 HS	326	void __iomem *data = mmio_base + bank->data;
	327	void __iomem *dir = mmio_base + bank->dir;
	328	int err;
b685004f	329
0f4630f3	330	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
1e4c8842 HS	331	if (err)
1e4c8842 HS	332	return err;
b685004f	333
0f4630f3 LW	334	gc->label = bank->label;
0f4630f3 LW	335	gc->base = bank->base;
b685004f	336
257af9f9	337	if (bank->has_debounce) {
0f4630f3 LW	338	gc->set_debounce = ep93xx_gpio_set_debounce;
0f4630f3 LW	339	gc->to_irq = ep93xx_gpio_to_irq;
257af9f9	340	}
b685004f	341
4cb220e2	342	return devm_gpiochip_add_data(dev, gc, NULL);
b685004f RM	343	}
b685004f RM	344
3836309d	345	static int ep93xx_gpio_probe(struct platform_device *pdev)
b685004f	346	{
1e4c8842 HS	347	struct ep93xx_gpio *ep93xx_gpio;
1e4c8842 HS	348	struct resource *res;
1e4c8842	349	int i;
1aeede0b	350	struct device *dev = &pdev->dev;
b685004f	351
1aeede0b	352	ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL);
1e4c8842 HS	353	if (!ep93xx_gpio)
1e4c8842 HS	354	return -ENOMEM;
b685004f	355
1e4c8842	356	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c829f956	357	ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
1aeede0b	358	if (IS_ERR(ep93xx_gpio->mmio_base))
1aeede0b	359	return PTR_ERR(ep93xx_gpio->mmio_base);
5d046af0	360
1e4c8842	361	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
0f4630f3	362	struct gpio_chip *gc = &ep93xx_gpio->gc[i];
1e4c8842	363	struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
5d046af0	364
0f4630f3	365	if (ep93xx_gpio_add_bank(gc, &pdev->dev,
1aeede0b	366	ep93xx_gpio->mmio_base, bank))
1e4c8842 HS	367	dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
1e4c8842 HS	368	bank->label);
b685004f RM	369	}
b685004f RM	370
1e4c8842	371	ep93xx_gpio_init_irq();
b685004f	372
1e4c8842	373	return 0;
1e4c8842	374	}
fd015480	375
1e4c8842 HS	376	static struct platform_driver ep93xx_gpio_driver = {
	377	.driver = {
	378	.name = "gpio-ep93xx",
1e4c8842 HS	379	},
	380	.probe = ep93xx_gpio_probe,
	381	};
	382
	383	static int __init ep93xx_gpio_init(void)
	384	{
1e4c8842	385	return platform_driver_register(&ep93xx_gpio_driver);
b685004f	386	}
1e4c8842 HS	387	postcore_initcall(ep93xx_gpio_init);
	388
	389	MODULE_AUTHOR("Ryan Mallon <[email protected]> "
	390	"H Hartley Sweeten <[email protected]>");
	391	MODULE_DESCRIPTION("EP93XX GPIO driver");
	392	MODULE_LICENSE("GPL");