[linux.git] / drivers / gpio / gpio-brcmstb.c

/*
 * Copyright (C) 2015 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>

#define GIO_BANK_SIZE           0x20
#define GIO_ODEN(bank)          (((bank) * GIO_BANK_SIZE) + 0x00)
#define GIO_DATA(bank)          (((bank) * GIO_BANK_SIZE) + 0x04)
#define GIO_IODIR(bank)         (((bank) * GIO_BANK_SIZE) + 0x08)
#define GIO_EC(bank)            (((bank) * GIO_BANK_SIZE) + 0x0c)
#define GIO_EI(bank)            (((bank) * GIO_BANK_SIZE) + 0x10)
#define GIO_MASK(bank)          (((bank) * GIO_BANK_SIZE) + 0x14)
#define GIO_LEVEL(bank)         (((bank) * GIO_BANK_SIZE) + 0x18)
#define GIO_STAT(bank)          (((bank) * GIO_BANK_SIZE) + 0x1c)

struct brcmstb_gpio_bank {
	struct list_head node;
	int id;
	struct gpio_chip gc;
	struct brcmstb_gpio_priv *parent_priv;
	u32 width;
	struct irq_chip irq_chip;
};

struct brcmstb_gpio_priv {
	struct list_head bank_list;
	void __iomem *reg_base;
	struct platform_device *pdev;
	int parent_irq;
	int gpio_base;
	bool can_wake;
	int parent_wake_irq;
	struct notifier_block reboot_notifier;
};

#define MAX_GPIO_PER_BANK           32
#define GPIO_BANK(gpio)         ((gpio) >> 5)
/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
#define GPIO_BIT(gpio)          ((gpio) & (MAX_GPIO_PER_BANK - 1))

static inline struct brcmstb_gpio_priv *
brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
{
	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
	return bank->parent_priv;
}

static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
		unsigned int offset, bool enable)
{
	struct gpio_chip *gc = &bank->gc;
	struct brcmstb_gpio_priv *priv = bank->parent_priv;
	u32 mask = gc->pin2mask(gc, offset);
	u32 imask;
	unsigned long flags;

	spin_lock_irqsave(&gc->bgpio_lock, flags);
	imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
	if (enable)
		imask |= mask;
	else
		imask &= ~mask;
	gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}

/* -------------------- IRQ chip functions -------------------- */

static void brcmstb_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

	brcmstb_gpio_set_imask(bank, d->hwirq, false);
}

static void brcmstb_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);

	brcmstb_gpio_set_imask(bank, d->hwirq, true);
}

static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
	struct brcmstb_gpio_priv *priv = bank->parent_priv;
	u32 mask = BIT(d->hwirq);
	u32 edge_insensitive, iedge_insensitive;
	u32 edge_config, iedge_config;
	u32 level, ilevel;
	unsigned long flags;

	switch (type) {
	case IRQ_TYPE_LEVEL_LOW:
		level = 0;
		edge_config = 0;
		edge_insensitive = 0;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		level = mask;
		edge_config = 0;
		edge_insensitive = 0;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		level = 0;
		edge_config = 0;
		edge_insensitive = 0;
		break;
	case IRQ_TYPE_EDGE_RISING:
		level = 0;
		edge_config = mask;
		edge_insensitive = 0;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		level = 0;
		edge_config = 0;  /* don't care, but want known value */
		edge_insensitive = mask;
		break;
	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);

	iedge_config = bank->gc.read_reg(priv->reg_base +
			GIO_EC(bank->id)) & ~mask;
	iedge_insensitive = bank->gc.read_reg(priv->reg_base +
			GIO_EI(bank->id)) & ~mask;
	ilevel = bank->gc.read_reg(priv->reg_base +
			GIO_LEVEL(bank->id)) & ~mask;

	bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
			iedge_config | edge_config);
	bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
			iedge_insensitive | edge_insensitive);
	bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
			ilevel | level);

	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
	return 0;
}

static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
		unsigned int enable)
{
	int ret = 0;

	/*
	 * Only enable wake IRQ once for however many hwirqs can wake
	 * since they all use the same wake IRQ.  Mask will be set
	 * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
	 */
	if (enable)
		ret = enable_irq_wake(priv->parent_wake_irq);
	else
		ret = disable_irq_wake(priv->parent_wake_irq);
	if (ret)
		dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
				enable ? "enable" : "disable");
	return ret;
}

static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);

	return brcmstb_gpio_priv_set_wake(priv, enable);
}

static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
{
	struct brcmstb_gpio_priv *priv = data;

	if (!priv || irq != priv->parent_wake_irq)
		return IRQ_NONE;
	pm_wakeup_event(&priv->pdev->dev, 0);
	return IRQ_HANDLED;
}

static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
{
	struct brcmstb_gpio_priv *priv = bank->parent_priv;
	struct irq_domain *irq_domain = bank->gc.irqdomain;
	void __iomem *reg_base = priv->reg_base;
	unsigned long status;
	unsigned long flags;

	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
	while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
			 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
		int bit;

		for_each_set_bit(bit, &status, 32) {
			u32 stat = bank->gc.read_reg(reg_base +
						      GIO_STAT(bank->id));
			if (bit >= bank->width)
				dev_warn(&priv->pdev->dev,
					 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
					 bank->id, bit);
			bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
					    stat | BIT(bit));
			generic_handle_irq(irq_find_mapping(irq_domain, bit));
		}
	}
	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
}

/* Each UPG GIO block has one IRQ for all banks */
static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct brcmstb_gpio_bank *bank;

	/* Interrupts weren't properly cleared during probe */
	BUG_ON(!priv || !chip);

	chained_irq_enter(chip, desc);
	list_for_each_entry(bank, &priv->bank_list, node)
		brcmstb_gpio_irq_bank_handler(bank);
	chained_irq_exit(chip, desc);
}

static int brcmstb_gpio_reboot(struct notifier_block *nb,
		unsigned long action, void *data)
{
	struct brcmstb_gpio_priv *priv =
		container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);

	/* Enable GPIO for S5 cold boot */
	if (action == SYS_POWER_OFF)
		brcmstb_gpio_priv_set_wake(priv, 1);

	return NOTIFY_DONE;
}

/* Make sure that the number of banks matches up between properties */
static int brcmstb_gpio_sanity_check_banks(struct device *dev,
		struct device_node *np, struct resource *res)
{
	int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
	int num_banks =
		of_property_count_u32_elems(np, "brcm,gpio-bank-widths");

	if (res_num_banks != num_banks) {
		dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
				res_num_banks, num_banks);
		return -EINVAL;
	} else {
		return 0;
	}
}

static int brcmstb_gpio_remove(struct platform_device *pdev)
{
	struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
	struct brcmstb_gpio_bank *bank;
	int ret = 0;

	if (!priv) {
		dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
		return -EFAULT;
	}

	/*
	 * You can lose return values below, but we report all errors, and it's
	 * more important to actually perform all of the steps.
	 */
	list_for_each_entry(bank, &priv->bank_list, node)
		gpiochip_remove(&bank->gc);

	if (priv->reboot_notifier.notifier_call) {
		ret = unregister_reboot_notifier(&priv->reboot_notifier);
		if (ret)
			dev_err(&pdev->dev,
				"failed to unregister reboot notifier\n");
	}
	return ret;
}

static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
		const struct of_phandle_args *gpiospec, u32 *flags)
{
	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
	int offset;

	if (gc->of_gpio_n_cells != 2) {
		WARN_ON(1);
		return -EINVAL;
	}

	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
		return -EINVAL;

	offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
	if (offset >= gc->ngpio || offset < 0)
		return -EINVAL;

	if (unlikely(offset >= bank->width)) {
		dev_warn_ratelimited(&priv->pdev->dev,
			"Received request for invalid GPIO offset %d\n",
			gpiospec->args[0]);
	}

	if (flags)
		*flags = gpiospec->args[1];

	return offset;
}

/* Before calling, must have bank->parent_irq set and gpiochip registered */
static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
		struct brcmstb_gpio_bank *bank)
{
	struct brcmstb_gpio_priv *priv = bank->parent_priv;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;

	bank->irq_chip.name = dev_name(dev);
	bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
	bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
	bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;

	/* Ensures that all non-wakeup IRQs are disabled at suspend */
	bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;

	if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
			of_property_read_bool(np, "wakeup-source")) {
		priv->parent_wake_irq = platform_get_irq(pdev, 1);
		if (priv->parent_wake_irq < 0) {
			dev_warn(dev,
				"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
		} else {
			int err;

			/*
			 * Set wakeup capability before requesting wakeup
			 * interrupt, so we can process boot-time "wakeups"
			 * (e.g., from S5 cold boot)
			 */
			device_set_wakeup_capable(dev, true);
			device_wakeup_enable(dev);
			err = devm_request_irq(dev, priv->parent_wake_irq,
					brcmstb_gpio_wake_irq_handler, 0,
					"brcmstb-gpio-wake", priv);

			if (err < 0) {
				dev_err(dev, "Couldn't request wake IRQ");
				return err;
			}

			priv->reboot_notifier.notifier_call =
				brcmstb_gpio_reboot;
			register_reboot_notifier(&priv->reboot_notifier);
			priv->can_wake = true;
		}
	}

	if (priv->can_wake)
		bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;

	gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
			handle_simple_irq, IRQ_TYPE_NONE);
	gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
			priv->parent_irq, brcmstb_gpio_irq_handler);

	return 0;
}

static int brcmstb_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	void __iomem *reg_base;
	struct brcmstb_gpio_priv *priv;
	struct resource *res;
	struct property *prop;
	const __be32 *p;
	u32 bank_width;
	int num_banks = 0;
	int err;
	static int gpio_base;
	unsigned long flags = 0;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;
	platform_set_drvdata(pdev, priv);
	INIT_LIST_HEAD(&priv->bank_list);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(reg_base))
		return PTR_ERR(reg_base);

	priv->gpio_base = gpio_base;
	priv->reg_base = reg_base;
	priv->pdev = pdev;

	if (of_property_read_bool(np, "interrupt-controller")) {
		priv->parent_irq = platform_get_irq(pdev, 0);
		if (priv->parent_irq <= 0) {
			dev_err(dev, "Couldn't get IRQ");
			return -ENOENT;
		}
	} else {
		priv->parent_irq = -ENOENT;
	}

	if (brcmstb_gpio_sanity_check_banks(dev, np, res))
		return -EINVAL;

	/*
	 * MIPS endianness is configured by boot strap, which also reverses all
	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
	 * endian I/O).
	 *
	 * Other architectures (e.g., ARM) either do not support big endian, or
	 * else leave I/O in little endian mode.
	 */
#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
	flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
#endif

	of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
			bank_width) {
		struct brcmstb_gpio_bank *bank;
		struct gpio_chip *gc;

		bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
		if (!bank) {
			err = -ENOMEM;
			goto fail;
		}

		bank->parent_priv = priv;
		bank->id = num_banks;
		if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
			dev_err(dev, "Invalid bank width %d\n", bank_width);
			err = -EINVAL;
			goto fail;
		} else {
			bank->width = bank_width;
		}

		/*
		 * Regs are 4 bytes wide, have data reg, no set/clear regs,
		 * and direction bits have 0 = output and 1 = input
		 */
		gc = &bank->gc;
		err = bgpio_init(gc, dev, 4,
				reg_base + GIO_DATA(bank->id),
				NULL, NULL, NULL,
				reg_base + GIO_IODIR(bank->id), flags);
		if (err) {
			dev_err(dev, "bgpio_init() failed\n");
			goto fail;
		}

		gc->of_node = np;
		gc->owner = THIS_MODULE;
		gc->label = np->full_name;
		gc->base = gpio_base;
		gc->of_gpio_n_cells = 2;
		gc->of_xlate = brcmstb_gpio_of_xlate;
		/* not all ngpio lines are valid, will use bank width later */
		gc->ngpio = MAX_GPIO_PER_BANK;

		/*
		 * Mask all interrupts by default, since wakeup interrupts may
		 * be retained from S5 cold boot
		 */
		gc->write_reg(reg_base + GIO_MASK(bank->id), 0);

		err = gpiochip_add_data(gc, bank);
		if (err) {
			dev_err(dev, "Could not add gpiochip for bank %d\n",
					bank->id);
			goto fail;
		}
		gpio_base += gc->ngpio;

		if (priv->parent_irq > 0) {
			err = brcmstb_gpio_irq_setup(pdev, bank);
			if (err)
				goto fail;
		}

		dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
			gc->base, gc->ngpio, bank->width);

		/* Everything looks good, so add bank to list */
		list_add(&bank->node, &priv->bank_list);

		num_banks++;
	}

	dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
			num_banks, priv->gpio_base, gpio_base - 1);

	return 0;

fail:
	(void) brcmstb_gpio_remove(pdev);
	return err;
}

static const struct of_device_id brcmstb_gpio_of_match[] = {
	{ .compatible = "brcm,brcmstb-gpio" },
	{},
};

MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);

static struct platform_driver brcmstb_gpio_driver = {
	.driver = {
		.name = "brcmstb-gpio",
		.of_match_table = brcmstb_gpio_of_match,
	},
	.probe = brcmstb_gpio_probe,
	.remove = brcmstb_gpio_remove,
};
module_platform_driver(brcmstb_gpio_driver);

MODULE_AUTHOR("Gregory Fong");
MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
3b0213d5 GF	1	/*
	2	* Copyright (C) 2015 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation version 2.
	7	*
	8	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	9	* kind, whether express or implied; without even the implied warranty
	10	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/bitops.h>
	15	#include <linux/gpio/driver.h>
	16	#include <linux/of_device.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/module.h>
19a7b694 GF	19	#include <linux/irqdomain.h>
	20	#include <linux/irqchip/chained_irq.h>
	21	#include <linux/interrupt.h>
3afa129a	22	#include <linux/reboot.h>
3b0213d5 GF	23
	24	#define GIO_BANK_SIZE 0x20
	25	#define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
	26	#define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
	27	#define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
	28	#define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
	29	#define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
	30	#define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
	31	#define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
	32	#define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
	33
	34	struct brcmstb_gpio_bank {
	35	struct list_head node;
	36	int id;
0f4630f3	37	struct gpio_chip gc;
3b0213d5 GF	38	struct brcmstb_gpio_priv *parent_priv;
3b0213d5 GF	39	u32 width;
19a7b694	40	struct irq_chip irq_chip;
3b0213d5 GF	41	};
	42
	43	struct brcmstb_gpio_priv {
	44	struct list_head bank_list;
	45	void __iomem *reg_base;
3b0213d5	46	struct platform_device *pdev;
19a7b694	47	int parent_irq;
3b0213d5	48	int gpio_base;
19a7b694 GF	49	bool can_wake;
19a7b694 GF	50	int parent_wake_irq;
3afa129a	51	struct notifier_block reboot_notifier;
3b0213d5 GF	52	};
	53
	54	#define MAX_GPIO_PER_BANK 32
	55	#define GPIO_BANK(gpio) ((gpio) >> 5)
	56	/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
	57	#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
	58
3b0213d5 GF	59	static inline struct brcmstb_gpio_priv *
	60	brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
	61	{
0f4630f3	62	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
3b0213d5 GF	63	return bank->parent_priv;
	64	}
	65
19a7b694 GF	66	static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
	67	unsigned int offset, bool enable)
	68	{
0f4630f3	69	struct gpio_chip *gc = &bank->gc;
19a7b694	70	struct brcmstb_gpio_priv *priv = bank->parent_priv;
0f4630f3	71	u32 mask = gc->pin2mask(gc, offset);
19a7b694 GF	72	u32 imask;
	73	unsigned long flags;
	74
0f4630f3 LW	75	spin_lock_irqsave(&gc->bgpio_lock, flags);
0f4630f3 LW	76	imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
19a7b694 GF	77	if (enable)
	78	imask \|= mask;
	79	else
	80	imask &= ~mask;
0f4630f3 LW	81	gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
0f4630f3 LW	82	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
19a7b694 GF	83	}
	84
	85	/* -------------------- IRQ chip functions -------------------- */
	86
	87	static void brcmstb_gpio_irq_mask(struct irq_data *d)
	88	{
	89	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0f4630f3	90	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
19a7b694 GF	91
	92	brcmstb_gpio_set_imask(bank, d->hwirq, false);
	93	}
	94
	95	static void brcmstb_gpio_irq_unmask(struct irq_data *d)
	96	{
	97	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0f4630f3	98	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
19a7b694 GF	99
	100	brcmstb_gpio_set_imask(bank, d->hwirq, true);
	101	}
	102
	103	static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
	104	{
	105	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0f4630f3	106	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
19a7b694 GF	107	struct brcmstb_gpio_priv *priv = bank->parent_priv;
	108	u32 mask = BIT(d->hwirq);
	109	u32 edge_insensitive, iedge_insensitive;
	110	u32 edge_config, iedge_config;
	111	u32 level, ilevel;
	112	unsigned long flags;
	113
	114	switch (type) {
	115	case IRQ_TYPE_LEVEL_LOW:
	116	level = 0;
	117	edge_config = 0;
	118	edge_insensitive = 0;
	119	break;
	120	case IRQ_TYPE_LEVEL_HIGH:
	121	level = mask;
	122	edge_config = 0;
	123	edge_insensitive = 0;
	124	break;
	125	case IRQ_TYPE_EDGE_FALLING:
	126	level = 0;
	127	edge_config = 0;
	128	edge_insensitive = 0;
	129	break;
	130	case IRQ_TYPE_EDGE_RISING:
	131	level = 0;
	132	edge_config = mask;
	133	edge_insensitive = 0;
	134	break;
	135	case IRQ_TYPE_EDGE_BOTH:
	136	level = 0;
	137	edge_config = 0; /* don't care, but want known value */
	138	edge_insensitive = mask;
	139	break;
	140	default:
	141	return -EINVAL;
	142	}
	143
0f4630f3	144	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
19a7b694	145
0f4630f3	146	iedge_config = bank->gc.read_reg(priv->reg_base +
19a7b694	147	GIO_EC(bank->id)) & ~mask;
0f4630f3	148	iedge_insensitive = bank->gc.read_reg(priv->reg_base +
19a7b694	149	GIO_EI(bank->id)) & ~mask;
0f4630f3	150	ilevel = bank->gc.read_reg(priv->reg_base +
19a7b694 GF	151	GIO_LEVEL(bank->id)) & ~mask;
19a7b694 GF	152
0f4630f3	153	bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
19a7b694	154	iedge_config \| edge_config);
0f4630f3	155	bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
19a7b694	156	iedge_insensitive \| edge_insensitive);
0f4630f3	157	bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
19a7b694 GF	158	ilevel \| level);
19a7b694 GF	159
0f4630f3	160	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
19a7b694 GF	161	return 0;
	162	}
	163
3afa129a GF	164	static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
3afa129a GF	165	unsigned int enable)
19a7b694	166	{
19a7b694 GF	167	int ret = 0;
	168
	169	/*
	170	* Only enable wake IRQ once for however many hwirqs can wake
	171	* since they all use the same wake IRQ. Mask will be set
	172	* up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
	173	*/
	174	if (enable)
	175	ret = enable_irq_wake(priv->parent_wake_irq);
	176	else
	177	ret = disable_irq_wake(priv->parent_wake_irq);
	178	if (ret)
	179	dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
	180	enable ? "enable" : "disable");
	181	return ret;
	182	}
	183
3afa129a GF	184	static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
	185	{
	186	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	187	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
	188
	189	return brcmstb_gpio_priv_set_wake(priv, enable);
	190	}
	191
19a7b694 GF	192	static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
	193	{
	194	struct brcmstb_gpio_priv *priv = data;
	195
	196	if (!priv \|\| irq != priv->parent_wake_irq)
	197	return IRQ_NONE;
	198	pm_wakeup_event(&priv->pdev->dev, 0);
	199	return IRQ_HANDLED;
	200	}
	201
	202	static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
	203	{
	204	struct brcmstb_gpio_priv *priv = bank->parent_priv;
0f4630f3	205	struct irq_domain *irq_domain = bank->gc.irqdomain;
19a7b694 GF	206	void __iomem *reg_base = priv->reg_base;
	207	unsigned long status;
	208	unsigned long flags;
	209
0f4630f3 LW	210	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
	211	while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
	212	bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
19a7b694 GF	213	int bit;
	214
	215	for_each_set_bit(bit, &status, 32) {
0f4630f3	216	u32 stat = bank->gc.read_reg(reg_base +
19a7b694 GF	217	GIO_STAT(bank->id));
	218	if (bit >= bank->width)
	219	dev_warn(&priv->pdev->dev,
	220	"IRQ for invalid GPIO (bank=%d, offset=%d)\n",
	221	bank->id, bit);
0f4630f3	222	bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
19a7b694 GF	223	stat \| BIT(bit));
	224	generic_handle_irq(irq_find_mapping(irq_domain, bit));
	225	}
	226	}
0f4630f3	227	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
19a7b694 GF	228	}
	229
	230	/* Each UPG GIO block has one IRQ for all banks */
bd0b9ac4	231	static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
19a7b694 GF	232	{
	233	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	234	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
	235	struct irq_chip *chip = irq_desc_get_chip(desc);
b178e7ea	236	struct brcmstb_gpio_bank *bank;
19a7b694 GF	237
	238	/* Interrupts weren't properly cleared during probe */
	239	BUG_ON(!priv \|\| !chip);
	240
	241	chained_irq_enter(chip, desc);
b178e7ea	242	list_for_each_entry(bank, &priv->bank_list, node)
19a7b694	243	brcmstb_gpio_irq_bank_handler(bank);
19a7b694 GF	244	chained_irq_exit(chip, desc);
	245	}
	246
3afa129a GF	247	static int brcmstb_gpio_reboot(struct notifier_block *nb,
	248	unsigned long action, void *data)
	249	{
	250	struct brcmstb_gpio_priv *priv =
	251	container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
	252
	253	/* Enable GPIO for S5 cold boot */
	254	if (action == SYS_POWER_OFF)
	255	brcmstb_gpio_priv_set_wake(priv, 1);
	256
	257	return NOTIFY_DONE;
	258	}
	259
3b0213d5 GF	260	/* Make sure that the number of banks matches up between properties */
	261	static int brcmstb_gpio_sanity_check_banks(struct device *dev,
	262	struct device_node np, struct resource res)
	263	{
	264	int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
	265	int num_banks =
	266	of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
	267
	268	if (res_num_banks != num_banks) {
	269	dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
	270	res_num_banks, num_banks);
	271	return -EINVAL;
	272	} else {
	273	return 0;
	274	}
	275	}
	276
	277	static int brcmstb_gpio_remove(struct platform_device *pdev)
	278	{
	279	struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
3b0213d5 GF	280	struct brcmstb_gpio_bank *bank;
	281	int ret = 0;
	282
2252607d GF	283	if (!priv) {
	284	dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
	285	return -EFAULT;
	286	}
	287
	288	/*
	289	* You can lose return values below, but we report all errors, and it's
	290	* more important to actually perform all of the steps.
	291	*/
b178e7ea	292	list_for_each_entry(bank, &priv->bank_list, node)
0f4630f3	293	gpiochip_remove(&bank->gc);
b178e7ea	294
3afa129a GF	295	if (priv->reboot_notifier.notifier_call) {
	296	ret = unregister_reboot_notifier(&priv->reboot_notifier);
	297	if (ret)
	298	dev_err(&pdev->dev,
	299	"failed to unregister reboot notifier\n");
	300	}
3b0213d5 GF	301	return ret;
	302	}
	303
	304	static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
	305	const struct of_phandle_args gpiospec, u32 flags)
	306	{
	307	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
0f4630f3	308	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
3b0213d5 GF	309	int offset;
	310
	311	if (gc->of_gpio_n_cells != 2) {
	312	WARN_ON(1);
	313	return -EINVAL;
	314	}
	315
	316	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
	317	return -EINVAL;
	318
	319	offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
19a7b694	320	if (offset >= gc->ngpio \|\| offset < 0)
3b0213d5 GF	321	return -EINVAL;
	322
	323	if (unlikely(offset >= bank->width)) {
	324	dev_warn_ratelimited(&priv->pdev->dev,
	325	"Received request for invalid GPIO offset %d\n",
	326	gpiospec->args[0]);
	327	}
	328
	329	if (flags)
	330	*flags = gpiospec->args[1];
	331
	332	return offset;
	333	}
	334
19a7b694 GF	335	/* Before calling, must have bank->parent_irq set and gpiochip registered */
	336	static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
	337	struct brcmstb_gpio_bank *bank)
	338	{
	339	struct brcmstb_gpio_priv *priv = bank->parent_priv;
	340	struct device *dev = &pdev->dev;
	341	struct device_node *np = dev->of_node;
	342
	343	bank->irq_chip.name = dev_name(dev);
	344	bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
	345	bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
	346	bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
	347
	348	/* Ensures that all non-wakeup IRQs are disabled at suspend */
	349	bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
	350
	351	if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
	352	of_property_read_bool(np, "wakeup-source")) {
	353	priv->parent_wake_irq = platform_get_irq(pdev, 1);
	354	if (priv->parent_wake_irq < 0) {
	355	dev_warn(dev,
	356	"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
	357	} else {
3afa129a GF	358	int err;
	359
	360	/*
	361	* Set wakeup capability before requesting wakeup
	362	* interrupt, so we can process boot-time "wakeups"
	363	* (e.g., from S5 cold boot)
	364	*/
	365	device_set_wakeup_capable(dev, true);
	366	device_wakeup_enable(dev);
	367	err = devm_request_irq(dev, priv->parent_wake_irq,
19a7b694 GF	368	brcmstb_gpio_wake_irq_handler, 0,
	369	"brcmstb-gpio-wake", priv);
	370
	371	if (err < 0) {
	372	dev_err(dev, "Couldn't request wake IRQ");
	373	return err;
	374	}
	375
3afa129a GF	376	priv->reboot_notifier.notifier_call =
	377	brcmstb_gpio_reboot;
	378	register_reboot_notifier(&priv->reboot_notifier);
19a7b694 GF	379	priv->can_wake = true;
	380	}
	381	}
	382
	383	if (priv->can_wake)
	384	bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
	385
0f4630f3	386	gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
19a7b694	387	handle_simple_irq, IRQ_TYPE_NONE);
0f4630f3	388	gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
19a7b694 GF	389	priv->parent_irq, brcmstb_gpio_irq_handler);
	390
	391	return 0;
	392	}
	393
3b0213d5 GF	394	static int brcmstb_gpio_probe(struct platform_device *pdev)
	395	{
	396	struct device *dev = &pdev->dev;
	397	struct device_node *np = dev->of_node;
	398	void __iomem *reg_base;
	399	struct brcmstb_gpio_priv *priv;
	400	struct resource *res;
	401	struct property *prop;
	402	const __be32 *p;
	403	u32 bank_width;
19a7b694	404	int num_banks = 0;
3b0213d5 GF	405	int err;
3b0213d5 GF	406	static int gpio_base;
ce5a7e81	407	unsigned long flags = 0;
3b0213d5 GF	408
	409	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	410	if (!priv)
	411	return -ENOMEM;
2252607d GF	412	platform_set_drvdata(pdev, priv);
2252607d GF	413	INIT_LIST_HEAD(&priv->bank_list);
3b0213d5 GF	414
	415	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	416	reg_base = devm_ioremap_resource(dev, res);
	417	if (IS_ERR(reg_base))
	418	return PTR_ERR(reg_base);
	419
	420	priv->gpio_base = gpio_base;
	421	priv->reg_base = reg_base;
	422	priv->pdev = pdev;
	423
19a7b694 GF	424	if (of_property_read_bool(np, "interrupt-controller")) {
	425	priv->parent_irq = platform_get_irq(pdev, 0);
	426	if (priv->parent_irq <= 0) {
	427	dev_err(dev, "Couldn't get IRQ");
	428	return -ENOENT;
	429	}
	430	} else {
	431	priv->parent_irq = -ENOENT;
	432	}
	433
3b0213d5 GF	434	if (brcmstb_gpio_sanity_check_banks(dev, np, res))
	435	return -EINVAL;
	436
ce5a7e81 FF	437	/*
	438	* MIPS endianness is configured by boot strap, which also reverses all
	439	* bus endianness (i.e., big-endian CPU + big endian bus ==> native
	440	* endian I/O).
	441	*
	442	* Other architectures (e.g., ARM) either do not support big endian, or
	443	* else leave I/O in little endian mode.
	444	*/
	445	#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
	446	flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
	447	#endif
	448
3b0213d5 GF	449	of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
	450	bank_width) {
	451	struct brcmstb_gpio_bank *bank;
3b0213d5 GF	452	struct gpio_chip *gc;
	453
	454	bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
	455	if (!bank) {
	456	err = -ENOMEM;
	457	goto fail;
	458	}
	459
	460	bank->parent_priv = priv;
19a7b694	461	bank->id = num_banks;
3b0213d5 GF	462	if (bank_width <= 0 \|\| bank_width > MAX_GPIO_PER_BANK) {
3b0213d5 GF	463	dev_err(dev, "Invalid bank width %d\n", bank_width);
35b3fc88	464	err = -EINVAL;
3b0213d5 GF	465	goto fail;
	466	} else {
	467	bank->width = bank_width;
	468	}
	469
	470	/*
	471	* Regs are 4 bytes wide, have data reg, no set/clear regs,
	472	* and direction bits have 0 = output and 1 = input
	473	*/
0f4630f3 LW	474	gc = &bank->gc;
0f4630f3 LW	475	err = bgpio_init(gc, dev, 4,
3b0213d5 GF	476	reg_base + GIO_DATA(bank->id),
3b0213d5 GF	477	NULL, NULL, NULL,
ce5a7e81	478	reg_base + GIO_IODIR(bank->id), flags);
3b0213d5 GF	479	if (err) {
	480	dev_err(dev, "bgpio_init() failed\n");
	481	goto fail;
	482	}
	483
3b0213d5 GF	484	gc->of_node = np;
	485	gc->owner = THIS_MODULE;
	486	gc->label = np->full_name;
	487	gc->base = gpio_base;
	488	gc->of_gpio_n_cells = 2;
	489	gc->of_xlate = brcmstb_gpio_of_xlate;
	490	/* not all ngpio lines are valid, will use bank width later */
	491	gc->ngpio = MAX_GPIO_PER_BANK;
	492
3afa129a GF	493	/*
	494	* Mask all interrupts by default, since wakeup interrupts may
	495	* be retained from S5 cold boot
	496	*/
0f4630f3	497	gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
3afa129a	498
0f4630f3	499	err = gpiochip_add_data(gc, bank);
3b0213d5 GF	500	if (err) {
	501	dev_err(dev, "Could not add gpiochip for bank %d\n",
	502	bank->id);
	503	goto fail;
	504	}
	505	gpio_base += gc->ngpio;
19a7b694 GF	506
	507	if (priv->parent_irq > 0) {
	508	err = brcmstb_gpio_irq_setup(pdev, bank);
	509	if (err)
	510	goto fail;
	511	}
	512
3b0213d5 GF	513	dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
	514	gc->base, gc->ngpio, bank->width);
	515
	516	/* Everything looks good, so add bank to list */
	517	list_add(&bank->node, &priv->bank_list);
	518
19a7b694	519	num_banks++;
3b0213d5 GF	520	}
	521
	522	dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
19a7b694	523	num_banks, priv->gpio_base, gpio_base - 1);
3b0213d5	524
3b0213d5 GF	525	return 0;
	526
	527	fail:
	528	(void) brcmstb_gpio_remove(pdev);
	529	return err;
	530	}
	531
	532	static const struct of_device_id brcmstb_gpio_of_match[] = {
	533	{ .compatible = "brcm,brcmstb-gpio" },
	534	{},
	535	};
	536
	537	MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
	538
	539	static struct platform_driver brcmstb_gpio_driver = {
	540	.driver = {
	541	.name = "brcmstb-gpio",
	542	.of_match_table = brcmstb_gpio_of_match,
	543	},
	544	.probe = brcmstb_gpio_probe,
	545	.remove = brcmstb_gpio_remove,
	546	};
	547	module_platform_driver(brcmstb_gpio_driver);
	548
	549	MODULE_AUTHOR("Gregory Fong");
	550	MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
	551	MODULE_LICENSE("GPL v2");