[linux.git] / arch / arm / mm / cache-v4.S

/*
 *  linux/arch/arm/mm/cache-v4.S
 *
 *  Copyright (C) 1997-2002 Russell king
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/page.h>
#include "proc-macros.S"

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(v4_flush_icache_all)
	ret	lr
ENDPROC(v4_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 *
 *	- mm	- mm_struct describing address space
 */
ENTRY(v4_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(v4_flush_kern_cache_all)
#ifdef CONFIG_CPU_CP15
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
	ret	lr
#else
	/* FALLTHROUGH */
#endif

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start - start address (may not be aligned)
 *	- end	- end address (exclusive, may not be aligned)
 *	- flags	- vma_area_struct flags describing address space
 */
ENTRY(v4_flush_user_cache_range)
#ifdef CONFIG_CPU_CP15
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ flush ID cache
	ret	lr
#else
	/* FALLTHROUGH */
#endif

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_coherent_user_range)
	mov	r0, #0
	ret	lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(v4_flush_kern_dcache_area)
	/* FALLTHROUGH */

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_dma_flush_range)
#ifdef CONFIG_CPU_CP15
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
#endif
	ret	lr

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v4_dma_unmap_area)
	teq	r2, #DMA_TO_DEVICE
	bne	v4_dma_flush_range
	/* FALLTHROUGH */

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v4_dma_map_area)
	ret	lr
ENDPROC(v4_dma_unmap_area)
ENDPROC(v4_dma_map_area)

	.globl	v4_flush_kern_cache_louis
	.equ	v4_flush_kern_cache_louis, v4_flush_kern_cache_all

	__INITDATA

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions v4
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/cache-v4.S
	3	*
	4	* Copyright (C) 1997-2002 Russell king
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/linkage.h>
	11	#include <linux/init.h>
6ebbf2ce	12	#include <asm/assembler.h>
1da177e4 LT	13	#include <asm/page.h>
	14	#include "proc-macros.S"
	15
c8c90860 MW	16	/*
	17	* flush_icache_all()
	18	*
	19	* Unconditionally clean and invalidate the entire icache.
	20	*/
	21	ENTRY(v4_flush_icache_all)
6ebbf2ce	22	ret lr
c8c90860 MW	23	ENDPROC(v4_flush_icache_all)
c8c90860 MW	24
1da177e4 LT	25	/*
	26	* flush_user_cache_all()
	27	*
	28	* Invalidate all cache entries in a particular address
	29	* space.
	30	*
	31	* - mm - mm_struct describing address space
	32	*/
	33	ENTRY(v4_flush_user_cache_all)
	34	/* FALLTHROUGH */
	35	/*
	36	* flush_kern_cache_all()
	37	*
	38	* Clean and invalidate the entire cache.
	39	*/
	40	ENTRY(v4_flush_kern_cache_all)
e4d2a598	41	#ifdef CONFIG_CPU_CP15
1da177e4 LT	42	mov r0, #0
1da177e4 LT	43	mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
6ebbf2ce	44	ret lr
f12d0d7c HC	45	#else
	46	/* FALLTHROUGH */
	47	#endif
1da177e4 LT	48
	49	/*
	50	* flush_user_cache_range(start, end, flags)
	51	*
	52	* Invalidate a range of cache entries in the specified
	53	* address space.
	54	*
	55	* - start - start address (may not be aligned)
	56	* - end - end address (exclusive, may not be aligned)
	57	* - flags - vma_area_struct flags describing address space
	58	*/
	59	ENTRY(v4_flush_user_cache_range)
e4d2a598	60	#ifdef CONFIG_CPU_CP15
1da177e4	61	mov ip, #0
794fe85d	62	mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
6ebbf2ce	63	ret lr
f12d0d7c HC	64	#else
	65	/* FALLTHROUGH */
	66	#endif
1da177e4 LT	67
	68	/*
	69	* coherent_kern_range(start, end)
	70	*
	71	* Ensure coherency between the Icache and the Dcache in the
	72	* region described by start. If you have non-snooping
	73	* Harvard caches, you need to implement this function.
	74	*
	75	* - start - virtual start address
	76	* - end - virtual end address
	77	*/
	78	ENTRY(v4_coherent_kern_range)
	79	/* FALLTHROUGH */
	80
	81	/*
	82	* coherent_user_range(start, end)
	83	*
	84	* Ensure coherency between the Icache and the Dcache in the
	85	* region described by start. If you have non-snooping
	86	* Harvard caches, you need to implement this function.
	87	*
	88	* - start - virtual start address
	89	* - end - virtual end address
	90	*/
	91	ENTRY(v4_coherent_user_range)
c5102f59	92	mov r0, #0
6ebbf2ce	93	ret lr
1da177e4 LT	94
1da177e4 LT	95	/*
2c9b9c84	96	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	97	*
	98	* Ensure no D cache aliasing occurs, either with itself or
	99	* the I cache
	100	*
2c9b9c84 RK	101	* - addr - kernel address
2c9b9c84 RK	102	* - size - region size
1da177e4	103	*/
2c9b9c84	104	ENTRY(v4_flush_kern_dcache_area)
1da177e4 LT	105	/* FALLTHROUGH */
1da177e4 LT	106
1da177e4 LT	107	/*
	108	* dma_flush_range(start, end)
	109	*
	110	* Clean and invalidate the specified virtual address range.
	111	*
	112	* - start - virtual start address
	113	* - end - virtual end address
	114	*/
	115	ENTRY(v4_dma_flush_range)
e4d2a598	116	#ifdef CONFIG_CPU_CP15
1da177e4 LT	117	mov r0, #0
1da177e4 LT	118	mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
f12d0d7c	119	#endif
6ebbf2ce	120	ret lr
1da177e4	121
a9c9147e RK	122	/*
	123	* dma_unmap_area(start, size, dir)
	124	* - start - kernel virtual start address
	125	* - size - size of region
	126	* - dir - DMA direction
	127	*/
	128	ENTRY(v4_dma_unmap_area)
	129	teq r2, #DMA_TO_DEVICE
702b94bf	130	bne v4_dma_flush_range
a9c9147e RK	131	/* FALLTHROUGH */
	132
	133	/*
	134	* dma_map_area(start, size, dir)
	135	* - start - kernel virtual start address
	136	* - size - size of region
	137	* - dir - DMA direction
	138	*/
	139	ENTRY(v4_dma_map_area)
6ebbf2ce	140	ret lr
a9c9147e RK	141	ENDPROC(v4_dma_unmap_area)
	142	ENDPROC(v4_dma_map_area)
	143
031bd879 LP	144	.globl v4_flush_kern_cache_louis
	145	.equ v4_flush_kern_cache_louis, v4_flush_kern_cache_all
	146
1da177e4 LT	147	__INITDATA
1da177e4 LT	148
54d4e9eb DM	149	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
54d4e9eb DM	150	define_cache_functions v4