[linux.git] / drivers / media / dvb / frontends / zl10353.c

/*
 * Driver for Zarlink DVB-T ZL10353 demodulator
 *
 * Copyright (C) 2006, 2007 Christopher Pascoe <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <asm/div64.h>

#include "dvb_frontend.h"
#include "zl10353_priv.h"
#include "zl10353.h"

struct zl10353_state {
	struct i2c_adapter *i2c;
	struct dvb_frontend frontend;

	struct zl10353_config config;

	enum fe_bandwidth bandwidth;
       u32 ucblocks;
       u32 frequency;
};

static int debug;
#define dprintk(args...) \
	do { \
		if (debug) printk(KERN_DEBUG "zl10353: " args); \
	} while (0)

static int debug_regs;

static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 buf[2] = { reg, val };
	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
			       .buf = buf, .len = 2 };
	int err = i2c_transfer(state->i2c, &msg, 1);
	if (err != 1) {
		printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
		return err;
	}
	return 0;
}

static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
{
	int err, i;
	for (i = 0; i < ilen - 1; i++)
		if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
			return err;

	return 0;
}

static int zl10353_read_register(struct zl10353_state *state, u8 reg)
{
	int ret;
	u8 b0[1] = { reg };
	u8 b1[1] = { 0 };
	struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
				    .flags = 0,
				    .buf = b0, .len = 1 },
				  { .addr = state->config.demod_address,
				    .flags = I2C_M_RD,
				    .buf = b1, .len = 1 } };

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2) {
		printk("%s: readreg error (reg=%d, ret==%i)\n",
		       __func__, reg, ret);
		return ret;
	}

	return b1[0];
}

static void zl10353_dump_regs(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	int ret;
	u8 reg;

	/* Dump all registers. */
	for (reg = 0; ; reg++) {
		if (reg % 16 == 0) {
			if (reg)
				printk(KERN_CONT "\n");
			printk(KERN_DEBUG "%02x:", reg);
		}
		ret = zl10353_read_register(state, reg);
		if (ret >= 0)
			printk(KERN_CONT " %02x", (u8)ret);
		else
			printk(KERN_CONT " --");
		if (reg == 0xff)
			break;
	}
	printk(KERN_CONT "\n");
}

static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
				      enum fe_bandwidth bandwidth,
				      u16 *nominal_rate)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u32 adc_clock = 450560; /* 45.056 MHz */
	u64 value;
	u8 bw;

	if (state->config.adc_clock)
		adc_clock = state->config.adc_clock;

	switch (bandwidth) {
	case BANDWIDTH_6_MHZ:
		bw = 6;
		break;
	case BANDWIDTH_7_MHZ:
		bw = 7;
		break;
	case BANDWIDTH_8_MHZ:
	default:
		bw = 8;
		break;
	}

	value = (u64)10 * (1 << 23) / 7 * 125;
	value = (bw * value) + adc_clock / 2;
	do_div(value, adc_clock);
	*nominal_rate = value;

	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
		__func__, bw, adc_clock, *nominal_rate);
}

static void zl10353_calc_input_freq(struct dvb_frontend *fe,
				    u16 *input_freq)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u32 adc_clock = 450560;	/* 45.056  MHz */
	int if2 = 361667;	/* 36.1667 MHz */
	int ife;
	u64 value;

	if (state->config.adc_clock)
		adc_clock = state->config.adc_clock;
	if (state->config.if2)
		if2 = state->config.if2;

	if (adc_clock >= if2 * 2)
		ife = if2;
	else {
		ife = adc_clock - (if2 % adc_clock);
		if (ife > adc_clock / 2)
			ife = adc_clock - ife;
	}
	value = (u64)65536 * ife + adc_clock / 2;
	do_div(value, adc_clock);
	*input_freq = -value;

	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
		__func__, if2, ife, adc_clock, -(int)value, *input_freq);
}

static int zl10353_sleep(struct dvb_frontend *fe)
{
	static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };

	zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
	return 0;
}

static int zl10353_set_parameters(struct dvb_frontend *fe,
				  struct dvb_frontend_parameters *param)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u16 nominal_rate, input_freq;
	u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
	u16 tps = 0;
	struct dvb_ofdm_parameters *op = &param->u.ofdm;

       state->frequency = param->frequency;

	zl10353_single_write(fe, RESET, 0x80);
	udelay(200);
	zl10353_single_write(fe, 0xEA, 0x01);
	udelay(200);
	zl10353_single_write(fe, 0xEA, 0x00);

	zl10353_single_write(fe, AGC_TARGET, 0x28);

	if (op->transmission_mode != TRANSMISSION_MODE_AUTO)
		acq_ctl |= (1 << 0);
	if (op->guard_interval != GUARD_INTERVAL_AUTO)
		acq_ctl |= (1 << 1);
	zl10353_single_write(fe, ACQ_CTL, acq_ctl);

	switch (op->bandwidth) {
	case BANDWIDTH_6_MHZ:
		/* These are extrapolated from the 7 and 8MHz values */
		zl10353_single_write(fe, MCLK_RATIO, 0x97);
		zl10353_single_write(fe, 0x64, 0x34);
		zl10353_single_write(fe, 0xcc, 0xdd);
		break;
	case BANDWIDTH_7_MHZ:
		zl10353_single_write(fe, MCLK_RATIO, 0x86);
		zl10353_single_write(fe, 0x64, 0x35);
		zl10353_single_write(fe, 0xcc, 0x73);
		break;
	case BANDWIDTH_8_MHZ:
	default:
		zl10353_single_write(fe, MCLK_RATIO, 0x75);
		zl10353_single_write(fe, 0x64, 0x36);
		zl10353_single_write(fe, 0xcc, 0x73);
	}

	zl10353_calc_nominal_rate(fe, op->bandwidth, &nominal_rate);
	zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
	zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
	state->bandwidth = op->bandwidth;

	zl10353_calc_input_freq(fe, &input_freq);
	zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
	zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));

	/* Hint at TPS settings */
	switch (op->code_rate_HP) {
	case FEC_2_3:
		tps |= (1 << 7);
		break;
	case FEC_3_4:
		tps |= (2 << 7);
		break;
	case FEC_5_6:
		tps |= (3 << 7);
		break;
	case FEC_7_8:
		tps |= (4 << 7);
		break;
	case FEC_1_2:
	case FEC_AUTO:
		break;
	default:
		return -EINVAL;
	}

	switch (op->code_rate_LP) {
	case FEC_2_3:
		tps |= (1 << 4);
		break;
	case FEC_3_4:
		tps |= (2 << 4);
		break;
	case FEC_5_6:
		tps |= (3 << 4);
		break;
	case FEC_7_8:
		tps |= (4 << 4);
		break;
	case FEC_1_2:
	case FEC_AUTO:
		break;
	case FEC_NONE:
		if (op->hierarchy_information == HIERARCHY_AUTO ||
		    op->hierarchy_information == HIERARCHY_NONE)
			break;
	default:
		return -EINVAL;
	}

	switch (op->constellation) {
	case QPSK:
		break;
	case QAM_AUTO:
	case QAM_16:
		tps |= (1 << 13);
		break;
	case QAM_64:
		tps |= (2 << 13);
		break;
	default:
		return -EINVAL;
	}

	switch (op->transmission_mode) {
	case TRANSMISSION_MODE_2K:
	case TRANSMISSION_MODE_AUTO:
		break;
	case TRANSMISSION_MODE_8K:
		tps |= (1 << 0);
		break;
	default:
		return -EINVAL;
	}

	switch (op->guard_interval) {
	case GUARD_INTERVAL_1_32:
	case GUARD_INTERVAL_AUTO:
		break;
	case GUARD_INTERVAL_1_16:
		tps |= (1 << 2);
		break;
	case GUARD_INTERVAL_1_8:
		tps |= (2 << 2);
		break;
	case GUARD_INTERVAL_1_4:
		tps |= (3 << 2);
		break;
	default:
		return -EINVAL;
	}

	switch (op->hierarchy_information) {
	case HIERARCHY_AUTO:
	case HIERARCHY_NONE:
		break;
	case HIERARCHY_1:
		tps |= (1 << 10);
		break;
	case HIERARCHY_2:
		tps |= (2 << 10);
		break;
	case HIERARCHY_4:
		tps |= (3 << 10);
		break;
	default:
		return -EINVAL;
	}

	zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
	zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));

	if (fe->ops.i2c_gate_ctrl)
		fe->ops.i2c_gate_ctrl(fe, 0);

	/*
	 * If there is no tuner attached to the secondary I2C bus, we call
	 * set_params to program a potential tuner attached somewhere else.
	 * Otherwise, we update the PLL registers via calc_regs.
	 */
	if (state->config.no_tuner) {
		if (fe->ops.tuner_ops.set_params) {
			fe->ops.tuner_ops.set_params(fe);
			if (fe->ops.i2c_gate_ctrl)
				fe->ops.i2c_gate_ctrl(fe, 0);
		}
	} else if (fe->ops.tuner_ops.calc_regs) {
		fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
		pllbuf[1] <<= 1;
		zl10353_write(fe, pllbuf, sizeof(pllbuf));
	}

	zl10353_single_write(fe, 0x5F, 0x13);

	/* If no attached tuner or invalid PLL registers, just start the FSM. */
	if (state->config.no_tuner || fe->ops.tuner_ops.calc_regs == NULL)
		zl10353_single_write(fe, FSM_GO, 0x01);
	else
		zl10353_single_write(fe, TUNER_GO, 0x01);

	return 0;
}

static int zl10353_get_parameters(struct dvb_frontend *fe,
				  struct dvb_frontend_parameters *param)
{
	struct zl10353_state *state = fe->demodulator_priv;
	struct dvb_ofdm_parameters *op = &param->u.ofdm;
	int s6, s9;
	u16 tps;
	static const u8 tps_fec_to_api[8] = {
		FEC_1_2,
		FEC_2_3,
		FEC_3_4,
		FEC_5_6,
		FEC_7_8,
		FEC_AUTO,
		FEC_AUTO,
		FEC_AUTO
	};

	s6 = zl10353_read_register(state, STATUS_6);
	s9 = zl10353_read_register(state, STATUS_9);
	if (s6 < 0 || s9 < 0)
		return -EREMOTEIO;
	if ((s6 & (1 << 5)) == 0 || (s9 & (1 << 4)) == 0)
		return -EINVAL;	/* no FE or TPS lock */

	tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 |
	      zl10353_read_register(state, TPS_RECEIVED_0);

	op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
	op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];

	switch ((tps >> 13) & 3) {
	case 0:
		op->constellation = QPSK;
		break;
	case 1:
		op->constellation = QAM_16;
		break;
	case 2:
		op->constellation = QAM_64;
		break;
	default:
		op->constellation = QAM_AUTO;
		break;
	}

	op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
					       TRANSMISSION_MODE_2K;

	switch ((tps >> 2) & 3) {
	case 0:
		op->guard_interval = GUARD_INTERVAL_1_32;
		break;
	case 1:
		op->guard_interval = GUARD_INTERVAL_1_16;
		break;
	case 2:
		op->guard_interval = GUARD_INTERVAL_1_8;
		break;
	case 3:
		op->guard_interval = GUARD_INTERVAL_1_4;
		break;
	default:
		op->guard_interval = GUARD_INTERVAL_AUTO;
		break;
	}

	switch ((tps >> 10) & 7) {
	case 0:
		op->hierarchy_information = HIERARCHY_NONE;
		break;
	case 1:
		op->hierarchy_information = HIERARCHY_1;
		break;
	case 2:
		op->hierarchy_information = HIERARCHY_2;
		break;
	case 3:
		op->hierarchy_information = HIERARCHY_4;
		break;
	default:
		op->hierarchy_information = HIERARCHY_AUTO;
		break;
	}

       param->frequency = state->frequency;
	op->bandwidth = state->bandwidth;
	param->inversion = INVERSION_AUTO;

	return 0;
}

static int zl10353_read_status(struct dvb_frontend *fe, fe_status_t *status)
{
	struct zl10353_state *state = fe->demodulator_priv;
	int s6, s7, s8;

	if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
		return -EREMOTEIO;
	if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
		return -EREMOTEIO;
	if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
		return -EREMOTEIO;

	*status = 0;
	if (s6 & (1 << 2))
		*status |= FE_HAS_CARRIER;
	if (s6 & (1 << 1))
		*status |= FE_HAS_VITERBI;
	if (s6 & (1 << 5))
		*status |= FE_HAS_LOCK;
	if (s7 & (1 << 4))
		*status |= FE_HAS_SYNC;
	if (s8 & (1 << 6))
		*status |= FE_HAS_SIGNAL;

	if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
	    (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
		*status &= ~FE_HAS_LOCK;

	return 0;
}

static int zl10353_read_ber(struct dvb_frontend *fe, u32 *ber)
{
	struct zl10353_state *state = fe->demodulator_priv;

	*ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 |
	       zl10353_read_register(state, RS_ERR_CNT_1) << 8 |
	       zl10353_read_register(state, RS_ERR_CNT_0);

	return 0;
}

static int zl10353_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
	struct zl10353_state *state = fe->demodulator_priv;

	u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 |
		     zl10353_read_register(state, AGC_GAIN_0) << 2 | 3;

	*strength = ~signal;

	return 0;
}

static int zl10353_read_snr(struct dvb_frontend *fe, u16 *snr)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 _snr;

	if (debug_regs)
		zl10353_dump_regs(fe);

	_snr = zl10353_read_register(state, SNR);
	*snr = (_snr << 8) | _snr;

	return 0;
}

static int zl10353_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
	struct zl10353_state *state = fe->demodulator_priv;
       u32 ubl = 0;

       ubl = zl10353_read_register(state, RS_UBC_1) << 8 |
	     zl10353_read_register(state, RS_UBC_0);

       state->ucblocks += ubl;
       *ucblocks = state->ucblocks;

	return 0;
}

static int zl10353_get_tune_settings(struct dvb_frontend *fe,
				     struct dvb_frontend_tune_settings
					 *fe_tune_settings)
{
	fe_tune_settings->min_delay_ms = 1000;
	fe_tune_settings->step_size = 0;
	fe_tune_settings->max_drift = 0;

	return 0;
}

static int zl10353_init(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };
	int rc = 0;

	if (debug_regs)
		zl10353_dump_regs(fe);
	if (state->config.parallel_ts)
		zl10353_reset_attach[2] &= ~0x20;
	if (state->config.clock_ctl_1)
		zl10353_reset_attach[3] = state->config.clock_ctl_1;
	if (state->config.pll_0)
		zl10353_reset_attach[4] = state->config.pll_0;

	/* Do a "hard" reset if not already done */
	if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] ||
	    zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
		rc = zl10353_write(fe, zl10353_reset_attach,
				   sizeof(zl10353_reset_attach));
		if (debug_regs)
			zl10353_dump_regs(fe);
	}

	return 0;
}

static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
	struct zl10353_state *state = fe->demodulator_priv;
	u8 val = 0x0a;

	if (state->config.disable_i2c_gate_ctrl) {
		/* No tuner attached to the internal I2C bus */
		/* If set enable I2C bridge, the main I2C bus stopped hardly */
		return 0;
	}

	if (enable)
		val |= 0x10;

	return zl10353_single_write(fe, 0x62, val);
}

static void zl10353_release(struct dvb_frontend *fe)
{
	struct zl10353_state *state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops zl10353_ops;

struct dvb_frontend *zl10353_attach(const struct zl10353_config *config,
				    struct i2c_adapter *i2c)
{
	struct zl10353_state *state = NULL;
	int id;

	/* allocate memory for the internal state */
	state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
	if (state == NULL)
		goto error;

	/* setup the state */
	state->i2c = i2c;
	memcpy(&state->config, config, sizeof(struct zl10353_config));

	/* check if the demod is there */
	id = zl10353_read_register(state, CHIP_ID);
	if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
		goto error;

	/* create dvb_frontend */
	memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
	state->frontend.demodulator_priv = state;

	return &state->frontend;
error:
	kfree(state);
	return NULL;
}

static struct dvb_frontend_ops zl10353_ops = {

	.info = {
		.name			= "Zarlink ZL10353 DVB-T",
		.type			= FE_OFDM,
		.frequency_min		= 174000000,
		.frequency_max		= 862000000,
		.frequency_stepsize	= 166667,
		.frequency_tolerance	= 0,
		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
			FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
			FE_CAN_FEC_AUTO |
			FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
			FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
			FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
			FE_CAN_MUTE_TS
	},

	.release = zl10353_release,

	.init = zl10353_init,
	.sleep = zl10353_sleep,
	.i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
	.write = zl10353_write,

	.set_frontend_legacy = zl10353_set_parameters,
	.get_frontend = zl10353_get_parameters,
	.get_tune_settings = zl10353_get_tune_settings,

	.read_status = zl10353_read_status,
	.read_ber = zl10353_read_ber,
	.read_signal_strength = zl10353_read_signal_strength,
	.read_snr = zl10353_read_snr,
	.read_ucblocks = zl10353_read_ucblocks,
};

module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");

module_param(debug_regs, int, 0644);
MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");

MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
MODULE_AUTHOR("Chris Pascoe");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(zl10353_attach);
Commit	Line	Data
780dfef3 CP	1	/*
	2	* Driver for Zarlink DVB-T ZL10353 demodulator
	3	*
794604c3	4	* Copyright (C) 2006, 2007 Christopher Pascoe <[email protected]>
780dfef3 CP	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	*
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
794604c3	19	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
780dfef3 CP	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
780dfef3 CP	24	#include <linux/init.h>
	25	#include <linux/delay.h>
	26	#include <linux/string.h>
	27	#include <linux/slab.h>
794604c3	28	#include <asm/div64.h>
780dfef3 CP	29
	30	#include "dvb_frontend.h"
	31	#include "zl10353_priv.h"
	32	#include "zl10353.h"
	33
	34	struct zl10353_state {
	35	struct i2c_adapter *i2c;
	36	struct dvb_frontend frontend;
780dfef3 CP	37
780dfef3 CP	38	struct zl10353_config config;
bc514710 CP	39
bc514710 CP	40	enum fe_bandwidth bandwidth;
decee2e8 AP	41	u32 ucblocks;
decee2e8 AP	42	u32 frequency;
780dfef3 CP	43	};
780dfef3 CP	44
f7f57770 AP	45	static int debug;
	46	#define dprintk(args...) \
	47	do { \
	48	if (debug) printk(KERN_DEBUG "zl10353: " args); \
	49	} while (0)
	50
ff699e6b	51	static int debug_regs;
780dfef3 CP	52
	53	static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
	54	{
	55	struct zl10353_state *state = fe->demodulator_priv;
	56	u8 buf[2] = { reg, val };
	57	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
	58	.buf = buf, .len = 2 };
	59	int err = i2c_transfer(state->i2c, &msg, 1);
	60	if (err != 1) {
	61	printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err);
	62	return err;
	63	}
	64	return 0;
	65	}
	66
2e4e98e7	67	static int zl10353_write(struct dvb_frontend *fe, const u8 ibuf[], int ilen)
780dfef3 CP	68	{
	69	int err, i;
	70	for (i = 0; i < ilen - 1; i++)
	71	if ((err = zl10353_single_write(fe, ibuf[0] + i, ibuf[i + 1])))
	72	return err;
	73
	74	return 0;
	75	}
	76
	77	static int zl10353_read_register(struct zl10353_state *state, u8 reg)
	78	{
	79	int ret;
	80	u8 b0[1] = { reg };
	81	u8 b1[1] = { 0 };
	82	struct i2c_msg msg[2] = { { .addr = state->config.demod_address,
	83	.flags = 0,
	84	.buf = b0, .len = 1 },
	85	{ .addr = state->config.demod_address,
	86	.flags = I2C_M_RD,
	87	.buf = b1, .len = 1 } };
	88
	89	ret = i2c_transfer(state->i2c, msg, 2);
	90
	91	if (ret != 2) {
	92	printk("%s: readreg error (reg=%d, ret==%i)\n",
271ddbf7	93	__func__, reg, ret);
780dfef3 CP	94	return ret;
	95	}
	96
	97	return b1[0];
	98	}
	99
c04e89b1	100	static void zl10353_dump_regs(struct dvb_frontend *fe)
780dfef3 CP	101	{
780dfef3 CP	102	struct zl10353_state *state = fe->demodulator_priv;
780dfef3 CP	103	int ret;
	104	u8 reg;
	105
	106	/* Dump all registers. */
	107	for (reg = 0; ; reg++) {
	108	if (reg % 16 == 0) {
	109	if (reg)
458f9aa3 JN	110	printk(KERN_CONT "\n");
458f9aa3 JN	111	printk(KERN_DEBUG "%02x:", reg);
780dfef3 CP	112	}
	113	ret = zl10353_read_register(state, reg);
	114	if (ret >= 0)
458f9aa3	115	printk(KERN_CONT " %02x", (u8)ret);
780dfef3	116	else
458f9aa3	117	printk(KERN_CONT " --");
780dfef3 CP	118	if (reg == 0xff)
	119	break;
	120	}
458f9aa3	121	printk(KERN_CONT "\n");
780dfef3 CP	122	}
780dfef3 CP	123
f7f57770 AP	124	static void zl10353_calc_nominal_rate(struct dvb_frontend *fe,
	125	enum fe_bandwidth bandwidth,
	126	u16 *nominal_rate)
	127	{
f7f57770	128	struct zl10353_state *state = fe->demodulator_priv;
a1dcd9de CP	129	u32 adc_clock = 450560; /* 45.056 MHz */
	130	u64 value;
	131	u8 bw;
f7f57770 AP	132
	133	if (state->config.adc_clock)
	134	adc_clock = state->config.adc_clock;
	135
	136	switch (bandwidth) {
	137	case BANDWIDTH_6_MHZ:
	138	bw = 6;
	139	break;
	140	case BANDWIDTH_7_MHZ:
	141	bw = 7;
	142	break;
	143	case BANDWIDTH_8_MHZ:
	144	default:
	145	bw = 8;
	146	break;
	147	}
	148
18ff605a AM	149	value = (u64)10 * (1 << 23) / 7 * 125;
18ff605a AM	150	value = (bw * value) + adc_clock / 2;
a1dcd9de CP	151	do_div(value, adc_clock);
a1dcd9de CP	152	*nominal_rate = value;
f7f57770 AP	153
f7f57770 AP	154	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
271ddbf7	155	__func__, bw, adc_clock, *nominal_rate);
f7f57770 AP	156	}
f7f57770 AP	157
794604c3 CP	158	static void zl10353_calc_input_freq(struct dvb_frontend *fe,
	159	u16 *input_freq)
	160	{
	161	struct zl10353_state *state = fe->demodulator_priv;
a1dcd9de CP	162	u32 adc_clock = 450560; /* 45.056 MHz */
a1dcd9de CP	163	int if2 = 361667; /* 36.1667 MHz */
794604c3 CP	164	int ife;
	165	u64 value;
	166
	167	if (state->config.adc_clock)
	168	adc_clock = state->config.adc_clock;
	169	if (state->config.if2)
	170	if2 = state->config.if2;
	171
	172	if (adc_clock >= if2 * 2)
	173	ife = if2;
	174	else {
	175	ife = adc_clock - (if2 % adc_clock);
	176	if (ife > adc_clock / 2)
	177	ife = adc_clock - ife;
	178	}
a1dcd9de	179	value = (u64)65536 * ife + adc_clock / 2;
794604c3 CP	180	do_div(value, adc_clock);
	181	*input_freq = -value;
	182
	183	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
271ddbf7	184	__func__, if2, ife, adc_clock, -(int)value, *input_freq);
794604c3 CP	185	}
794604c3 CP	186
780dfef3 CP	187	static int zl10353_sleep(struct dvb_frontend *fe)
	188	{
	189	static u8 zl10353_softdown[] = { 0x50, 0x0C, 0x44 };
	190
	191	zl10353_write(fe, zl10353_softdown, sizeof(zl10353_softdown));
	192	return 0;
	193	}
	194
	195	static int zl10353_set_parameters(struct dvb_frontend *fe,
	196	struct dvb_frontend_parameters *param)
	197	{
8dec0732	198	struct zl10353_state *state = fe->demodulator_priv;
794604c3	199	u16 nominal_rate, input_freq;
bc514710 CP	200	u8 pllbuf[6] = { 0x67 }, acq_ctl = 0;
	201	u16 tps = 0;
	202	struct dvb_ofdm_parameters *op = &param->u.ofdm;
780dfef3	203
decee2e8 AP	204	state->frequency = param->frequency;
decee2e8 AP	205
bc514710	206	zl10353_single_write(fe, RESET, 0x80);
780dfef3 CP	207	udelay(200);
	208	zl10353_single_write(fe, 0xEA, 0x01);
	209	udelay(200);
	210	zl10353_single_write(fe, 0xEA, 0x00);
	211
bc514710 CP	212	zl10353_single_write(fe, AGC_TARGET, 0x28);
	213
	214	if (op->transmission_mode != TRANSMISSION_MODE_AUTO)
	215	acq_ctl \|= (1 << 0);
	216	if (op->guard_interval != GUARD_INTERVAL_AUTO)
	217	acq_ctl \|= (1 << 1);
	218	zl10353_single_write(fe, ACQ_CTL, acq_ctl);
f7f57770	219
bc514710 CP	220	switch (op->bandwidth) {
	221	case BANDWIDTH_6_MHZ:
	222	/* These are extrapolated from the 7 and 8MHz values */
	223	zl10353_single_write(fe, MCLK_RATIO, 0x97);
	224	zl10353_single_write(fe, 0x64, 0x34);
a9dbe5dc	225	zl10353_single_write(fe, 0xcc, 0xdd);
bc514710 CP	226	break;
	227	case BANDWIDTH_7_MHZ:
	228	zl10353_single_write(fe, MCLK_RATIO, 0x86);
	229	zl10353_single_write(fe, 0x64, 0x35);
a9dbe5dc	230	zl10353_single_write(fe, 0xcc, 0x73);
bc514710 CP	231	break;
	232	case BANDWIDTH_8_MHZ:
	233	default:
	234	zl10353_single_write(fe, MCLK_RATIO, 0x75);
	235	zl10353_single_write(fe, 0x64, 0x36);
a9dbe5dc	236	zl10353_single_write(fe, 0xcc, 0x73);
bc514710 CP	237	}
	238
	239	zl10353_calc_nominal_rate(fe, op->bandwidth, &nominal_rate);
f7f57770 AP	240	zl10353_single_write(fe, TRL_NOMINAL_RATE_1, msb(nominal_rate));
f7f57770 AP	241	zl10353_single_write(fe, TRL_NOMINAL_RATE_0, lsb(nominal_rate));
bc514710	242	state->bandwidth = op->bandwidth;
f7f57770	243
794604c3 CP	244	zl10353_calc_input_freq(fe, &input_freq);
	245	zl10353_single_write(fe, INPUT_FREQ_1, msb(input_freq));
	246	zl10353_single_write(fe, INPUT_FREQ_0, lsb(input_freq));
	247
bc514710 CP	248	/* Hint at TPS settings */
	249	switch (op->code_rate_HP) {
	250	case FEC_2_3:
	251	tps \|= (1 << 7);
	252	break;
	253	case FEC_3_4:
	254	tps \|= (2 << 7);
	255	break;
	256	case FEC_5_6:
	257	tps \|= (3 << 7);
	258	break;
	259	case FEC_7_8:
	260	tps \|= (4 << 7);
	261	break;
	262	case FEC_1_2:
	263	case FEC_AUTO:
	264	break;
	265	default:
	266	return -EINVAL;
	267	}
	268
	269	switch (op->code_rate_LP) {
	270	case FEC_2_3:
	271	tps \|= (1 << 4);
	272	break;
	273	case FEC_3_4:
	274	tps \|= (2 << 4);
	275	break;
	276	case FEC_5_6:
	277	tps \|= (3 << 4);
	278	break;
	279	case FEC_7_8:
	280	tps \|= (4 << 4);
	281	break;
	282	case FEC_1_2:
	283	case FEC_AUTO:
	284	break;
	285	case FEC_NONE:
	286	if (op->hierarchy_information == HIERARCHY_AUTO \|\|
	287	op->hierarchy_information == HIERARCHY_NONE)
	288	break;
	289	default:
	290	return -EINVAL;
	291	}
	292
	293	switch (op->constellation) {
	294	case QPSK:
	295	break;
	296	case QAM_AUTO:
	297	case QAM_16:
	298	tps \|= (1 << 13);
	299	break;
	300	case QAM_64:
	301	tps \|= (2 << 13);
	302	break;
	303	default:
	304	return -EINVAL;
	305	}
	306
	307	switch (op->transmission_mode) {
	308	case TRANSMISSION_MODE_2K:
	309	case TRANSMISSION_MODE_AUTO:
	310	break;
	311	case TRANSMISSION_MODE_8K:
312	tps \|= (1 << 0);
313	break;
314	default:
315	return -EINVAL;
316	}
317
318	switch (op->guard_interval) {
319	case GUARD_INTERVAL_1_32:
320	case GUARD_INTERVAL_AUTO:
321	break;
322	case GUARD_INTERVAL_1_16:
323	tps \|= (1 << 2);
324	break;
325	case GUARD_INTERVAL_1_8:
326	tps \|= (2 << 2);
327	break;
328	case GUARD_INTERVAL_1_4:
329	tps \|= (3 << 2);
330	break;
331	default:
332	return -EINVAL;
333	}
334
335	switch (op->hierarchy_information) {
336	case HIERARCHY_AUTO:
337	case HIERARCHY_NONE:
338	break;
339	case HIERARCHY_1:
340	tps \|= (1 << 10);
341	break;
342	case HIERARCHY_2:
343	tps \|= (2 << 10);
344	break;
345	case HIERARCHY_4:
346	tps \|= (3 << 10);
347	break;
348	default:
349	return -EINVAL;
350	}
351
352	zl10353_single_write(fe, TPS_GIVEN_1, msb(tps));
353	zl10353_single_write(fe, TPS_GIVEN_0, lsb(tps));
354
0a11bb86 AP	355	if (fe->ops.i2c_gate_ctrl)
0a11bb86 AP	356	fe->ops.i2c_gate_ctrl(fe, 0);
780dfef3	357
58d834ea CP	358	/*
	359	* If there is no tuner attached to the secondary I2C bus, we call
	360	* set_params to program a potential tuner attached somewhere else.
	361	* Otherwise, we update the PLL registers via calc_regs.
	362	*/
8dec0732	363	if (state->config.no_tuner) {
dea74869	364	if (fe->ops.tuner_ops.set_params) {
14d24d14	365	fe->ops.tuner_ops.set_params(fe);
0a11bb86 AP	366	if (fe->ops.i2c_gate_ctrl)
0a11bb86 AP	367	fe->ops.i2c_gate_ctrl(fe, 0);
8dec0732	368	}
58d834ea	369	} else if (fe->ops.tuner_ops.calc_regs) {
249fa0b0	370	fe->ops.tuner_ops.calc_regs(fe, pllbuf + 1, 5);
e994b8d9	371	pllbuf[1] <<= 1;
58d834ea	372	zl10353_write(fe, pllbuf, sizeof(pllbuf));
e994b8d9	373	}
780dfef3	374
fc3398d8	375	zl10353_single_write(fe, 0x5F, 0x13);
58d834ea CP	376
	377	/* If no attached tuner or invalid PLL registers, just start the FSM. */
	378	if (state->config.no_tuner \|\| fe->ops.tuner_ops.calc_regs == NULL)
	379	zl10353_single_write(fe, FSM_GO, 0x01);
	380	else
	381	zl10353_single_write(fe, TUNER_GO, 0x01);
	382
bc514710 CP	383	return 0;
	384	}
	385
	386	static int zl10353_get_parameters(struct dvb_frontend *fe,
	387	struct dvb_frontend_parameters *param)
	388	{
	389	struct zl10353_state *state = fe->demodulator_priv;
	390	struct dvb_ofdm_parameters *op = &param->u.ofdm;
	391	int s6, s9;
	392	u16 tps;
	393	static const u8 tps_fec_to_api[8] = {
	394	FEC_1_2,
	395	FEC_2_3,
	396	FEC_3_4,
	397	FEC_5_6,
	398	FEC_7_8,
	399	FEC_AUTO,
	400	FEC_AUTO,
	401	FEC_AUTO
	402	};
	403
	404	s6 = zl10353_read_register(state, STATUS_6);
	405	s9 = zl10353_read_register(state, STATUS_9);
	406	if (s6 < 0 \|\| s9 < 0)
	407	return -EREMOTEIO;
	408	if ((s6 & (1 << 5)) == 0 \|\| (s9 & (1 << 4)) == 0)
	409	return -EINVAL; /* no FE or TPS lock */
	410
	411	tps = zl10353_read_register(state, TPS_RECEIVED_1) << 8 \|
	412	zl10353_read_register(state, TPS_RECEIVED_0);
	413
	414	op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
	415	op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
	416
	417	switch ((tps >> 13) & 3) {
	418	case 0:
	419	op->constellation = QPSK;
	420	break;
	421	case 1:
	422	op->constellation = QAM_16;
	423	break;
	424	case 2:
	425	op->constellation = QAM_64;
	426	break;
	427	default:
	428	op->constellation = QAM_AUTO;
	429	break;
	430	}
	431
	432	op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K :
	433	TRANSMISSION_MODE_2K;
	434
	435	switch ((tps >> 2) & 3) {
	436	case 0:
	437	op->guard_interval = GUARD_INTERVAL_1_32;
	438	break;
	439	case 1:
	440	op->guard_interval = GUARD_INTERVAL_1_16;
	441	break;
	442	case 2:
	443	op->guard_interval = GUARD_INTERVAL_1_8;
	444	break;
	445	case 3:
	446	op->guard_interval = GUARD_INTERVAL_1_4;
447	break;
448	default:
449	op->guard_interval = GUARD_INTERVAL_AUTO;
450	break;
451	}
452
453	switch ((tps >> 10) & 7) {
454	case 0:
455	op->hierarchy_information = HIERARCHY_NONE;
456	break;
457	case 1:
458	op->hierarchy_information = HIERARCHY_1;
459	break;
460	case 2:
461	op->hierarchy_information = HIERARCHY_2;
462	break;
463	case 3:
464	op->hierarchy_information = HIERARCHY_4;
465	break;
466	default:
467	op->hierarchy_information = HIERARCHY_AUTO;
468	break;
469	}
470
decee2e8	471	param->frequency = state->frequency;
bc514710 CP	472	op->bandwidth = state->bandwidth;
bc514710 CP	473	param->inversion = INVERSION_AUTO;
780dfef3 CP	474
	475	return 0;
	476	}
	477
	478	static int zl10353_read_status(struct dvb_frontend fe, fe_status_t status)
	479	{
	480	struct zl10353_state *state = fe->demodulator_priv;
	481	int s6, s7, s8;
	482
	483	if ((s6 = zl10353_read_register(state, STATUS_6)) < 0)
	484	return -EREMOTEIO;
	485	if ((s7 = zl10353_read_register(state, STATUS_7)) < 0)
	486	return -EREMOTEIO;
	487	if ((s8 = zl10353_read_register(state, STATUS_8)) < 0)
	488	return -EREMOTEIO;
	489
	490	*status = 0;
	491	if (s6 & (1 << 2))
	492	*status \|= FE_HAS_CARRIER;
	493	if (s6 & (1 << 1))
	494	*status \|= FE_HAS_VITERBI;
	495	if (s6 & (1 << 5))
	496	*status \|= FE_HAS_LOCK;
	497	if (s7 & (1 << 4))
	498	*status \|= FE_HAS_SYNC;
	499	if (s8 & (1 << 6))
	500	*status \|= FE_HAS_SIGNAL;
	501
	502	if ((*status & (FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_SYNC)) !=
	503	(FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_SYNC))
	504	*status &= ~FE_HAS_LOCK;
	505
	506	return 0;
	507	}
	508
67b60aad CP	509	static int zl10353_read_ber(struct dvb_frontend fe, u32 ber)
	510	{
	511	struct zl10353_state *state = fe->demodulator_priv;
	512
6345f0f6 CP	513	*ber = zl10353_read_register(state, RS_ERR_CNT_2) << 16 \|
	514	zl10353_read_register(state, RS_ERR_CNT_1) << 8 \|
	515	zl10353_read_register(state, RS_ERR_CNT_0);
67b60aad CP	516
	517	return 0;
	518	}
	519
	520	static int zl10353_read_signal_strength(struct dvb_frontend fe, u16 strength)
	521	{
	522	struct zl10353_state *state = fe->demodulator_priv;
	523
6345f0f6 CP	524	u16 signal = zl10353_read_register(state, AGC_GAIN_1) << 10 \|
6345f0f6 CP	525	zl10353_read_register(state, AGC_GAIN_0) << 2 \| 3;
67b60aad CP	526
	527	*strength = ~signal;
	528
	529	return 0;
	530	}
	531
780dfef3 CP	532	static int zl10353_read_snr(struct dvb_frontend fe, u16 snr)
	533	{
	534	struct zl10353_state *state = fe->demodulator_priv;
	535	u8 _snr;
	536
	537	if (debug_regs)
	538	zl10353_dump_regs(fe);
	539
	540	_snr = zl10353_read_register(state, SNR);
	541	*snr = (_snr << 8) \| _snr;
	542
	543	return 0;
	544	}
	545
67b60aad CP	546	static int zl10353_read_ucblocks(struct dvb_frontend fe, u32 ucblocks)
	547	{
	548	struct zl10353_state *state = fe->demodulator_priv;
decee2e8 AP	549	u32 ubl = 0;
	550
	551	ubl = zl10353_read_register(state, RS_UBC_1) << 8 \|
	552	zl10353_read_register(state, RS_UBC_0);
67b60aad	553
decee2e8 AP	554	state->ucblocks += ubl;
decee2e8 AP	555	*ucblocks = state->ucblocks;
67b60aad CP	556
	557	return 0;
	558	}
	559
780dfef3 CP	560	static int zl10353_get_tune_settings(struct dvb_frontend *fe,
	561	struct dvb_frontend_tune_settings
	562	*fe_tune_settings)
	563	{
	564	fe_tune_settings->min_delay_ms = 1000;
	565	fe_tune_settings->step_size = 0;
	566	fe_tune_settings->max_drift = 0;
	567
	568	return 0;
	569	}
	570
	571	static int zl10353_init(struct dvb_frontend *fe)
	572	{
	573	struct zl10353_state *state = fe->demodulator_priv;
	574	u8 zl10353_reset_attach[6] = { 0x50, 0x03, 0x64, 0x46, 0x15, 0x0F };
	575	int rc = 0;
	576
	577	if (debug_regs)
	578	zl10353_dump_regs(fe);
8fb95784 CP	579	if (state->config.parallel_ts)
8fb95784 CP	580	zl10353_reset_attach[2] &= ~0x20;
378a2793 AP	581	if (state->config.clock_ctl_1)
	582	zl10353_reset_attach[3] = state->config.clock_ctl_1;
	583	if (state->config.pll_0)
	584	zl10353_reset_attach[4] = state->config.pll_0;
780dfef3 CP	585
780dfef3 CP	586	/* Do a "hard" reset if not already done */
8fb95784 CP	587	if (zl10353_read_register(state, 0x50) != zl10353_reset_attach[1] \|\|
8fb95784 CP	588	zl10353_read_register(state, 0x51) != zl10353_reset_attach[2]) {
780dfef3 CP	589	rc = zl10353_write(fe, zl10353_reset_attach,
	590	sizeof(zl10353_reset_attach));
	591	if (debug_regs)
	592	zl10353_dump_regs(fe);
	593	}
	594
	595	return 0;
	596	}
	597
0a11bb86 AP	598	static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
0a11bb86 AP	599	{
899a6f67	600	struct zl10353_state *state = fe->demodulator_priv;
0a11bb86 AP	601	u8 val = 0x0a;
0a11bb86 AP	602
5f77af93	603	if (state->config.disable_i2c_gate_ctrl) {
899a6f67 DB	604	/* No tuner attached to the internal I2C bus */
	605	/* If set enable I2C bridge, the main I2C bus stopped hardly */
	606	return 0;
	607	}
	608
0a11bb86 AP	609	if (enable)
	610	val \|= 0x10;
	611
	612	return zl10353_single_write(fe, 0x62, val);
	613	}
	614
780dfef3 CP	615	static void zl10353_release(struct dvb_frontend *fe)
	616	{
	617	struct zl10353_state *state = fe->demodulator_priv;
780dfef3 CP	618	kfree(state);
	619	}
	620
	621	static struct dvb_frontend_ops zl10353_ops;
	622
	623	struct dvb_frontend zl10353_attach(const struct zl10353_config config,
	624	struct i2c_adapter *i2c)
	625	{
	626	struct zl10353_state *state = NULL;
378a2793	627	int id;
780dfef3 CP	628
	629	/* allocate memory for the internal state */
	630	state = kzalloc(sizeof(struct zl10353_state), GFP_KERNEL);
	631	if (state == NULL)
	632	goto error;
	633
	634	/* setup the state */
	635	state->i2c = i2c;
	636	memcpy(&state->config, config, sizeof(struct zl10353_config));
780dfef3 CP	637
780dfef3 CP	638	/* check if the demod is there */
378a2793 AP	639	id = zl10353_read_register(state, CHIP_ID);
378a2793 AP	640	if ((id != ID_ZL10353) && (id != ID_CE6230) && (id != ID_CE6231))
780dfef3 CP	641	goto error;
	642
	643	/* create dvb_frontend */
dea74869	644	memcpy(&state->frontend.ops, &zl10353_ops, sizeof(struct dvb_frontend_ops));
780dfef3 CP	645	state->frontend.demodulator_priv = state;
	646
	647	return &state->frontend;
	648	error:
	649	kfree(state);
	650	return NULL;
	651	}
	652
	653	static struct dvb_frontend_ops zl10353_ops = {
	654
	655	.info = {
	656	.name = "Zarlink ZL10353 DVB-T",
	657	.type = FE_OFDM,
	658	.frequency_min = 174000000,
	659	.frequency_max = 862000000,
	660	.frequency_stepsize = 166667,
	661	.frequency_tolerance = 0,
	662	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \|
	663	FE_CAN_FEC_3_4 \| FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \|
	664	FE_CAN_FEC_AUTO \|
	665	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|
	666	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|
	667	FE_CAN_HIERARCHY_AUTO \| FE_CAN_RECOVER \|
	668	FE_CAN_MUTE_TS
	669	},
	670
	671	.release = zl10353_release,
	672
	673	.init = zl10353_init,
	674	.sleep = zl10353_sleep,
0a11bb86	675	.i2c_gate_ctrl = zl10353_i2c_gate_ctrl,
c10d14d6	676	.write = zl10353_write,
780dfef3	677
bc9cd273	678	.set_frontend_legacy = zl10353_set_parameters,
bc514710	679	.get_frontend = zl10353_get_parameters,
780dfef3 CP	680	.get_tune_settings = zl10353_get_tune_settings,
	681
	682	.read_status = zl10353_read_status,
67b60aad CP	683	.read_ber = zl10353_read_ber,
67b60aad CP	684	.read_signal_strength = zl10353_read_signal_strength,
780dfef3	685	.read_snr = zl10353_read_snr,
67b60aad	686	.read_ucblocks = zl10353_read_ucblocks,
780dfef3 CP	687	};
780dfef3 CP	688
f7f57770 AP	689	module_param(debug, int, 0644);
	690	MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
	691
780dfef3 CP	692	module_param(debug_regs, int, 0644);
	693	MODULE_PARM_DESC(debug_regs, "Turn on/off frontend register dumps (default:off).");
	694
	695	MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver");
	696	MODULE_AUTHOR("Chris Pascoe");
	697	MODULE_LICENSE("GPL");
	698
	699	EXPORT_SYMBOL(zl10353_attach);