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KVM: SVM: Do not allow instruction emulation under SEV-ES
[linux.git] / arch / x86 / kvm / svm / svm.c
CommitLineData
44a95dae
SS		 1#define pr_fmt(fmt) "SVM: " fmt
2
edf88417
AK		 3#include <linux/kvm_host.h>
4
85f455f7 5#include "irq.h"
1d737c8a 6#include "mmu.h"
5fdbf976 7#include "kvm_cache_regs.h"
fe4c7b19 8#include "x86.h"
66f7b72e 9#include "cpuid.h"
25462f7f 10#include "pmu.h"
e495606d 11
6aa8b732 12#include <linux/module.h>
ae759544 13#include <linux/mod_devicetable.h>
9d8f549d 14#include <linux/kernel.h>
6aa8b732
AK		 15#include <linux/vmalloc.h>
16#include <linux/highmem.h>
ef0f6496 17#include <linux/amd-iommu.h>
e8edc6e0 18#include <linux/sched.h>
af658dca 19#include <linux/trace_events.h>
5a0e3ad6 20#include <linux/slab.h>
5881f737 21#include <linux/hashtable.h>
00089c04 22#include <linux/objtool.h>
e9df0942 23#include <linux/psp-sev.h>
1654efcb 24#include <linux/file.h>
89c50580
BS		 25#include <linux/pagemap.h>
26#include <linux/swap.h>
33af3a7e 27#include <linux/rwsem.h>
6aa8b732 28
8221c137 29#include <asm/apic.h>
1018faa6 30#include <asm/perf_event.h>
67ec6607 31#include <asm/tlbflush.h>
e495606d 32#include <asm/desc.h>
facb0139 33#include <asm/debugreg.h>
631bc487 34#include <asm/kvm_para.h>
411b44ba 35#include <asm/irq_remapping.h>
28a27752 36#include <asm/spec-ctrl.h>
ba5bade4 37#include <asm/cpu_device_id.h>
f1c6366e 38#include <asm/traps.h>
6aa8b732 39
63d1142f 40#include <asm/virtext.h>
229456fc 41#include "trace.h"
63d1142f 42
883b0a91
JR		 43#include "svm.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
575b255c 50#ifdef MODULE
ae759544 51static const struct x86_cpu_id svm_cpu_id[] = {
320debe5 52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
ae759544
JT		 53 {}
54};
55MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
575b255c 56#endif
ae759544 57
6aa8b732
AK		 58#define IOPM_ALLOC_ORDER 2
59#define MSRPM_ALLOC_ORDER 1
60
6aa8b732
AK		 61#define SEG_TYPE_LDT 2
62#define SEG_TYPE_BUSY_TSS16 3
63
6bc31bdc
AP		 64#define SVM_FEATURE_LBRV (1 << 1)
65#define SVM_FEATURE_SVML (1 << 2)
ddce97aa
AP		 66#define SVM_FEATURE_TSC_RATE (1 << 4)
67#define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68#define SVM_FEATURE_FLUSH_ASID (1 << 6)
69#define SVM_FEATURE_DECODE_ASSIST (1 << 7)
6bc31bdc 70#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 71
24e09cbf
JR		 72#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
73
fbc0db76 74#define TSC_RATIO_RSVD 0xffffff0000000000ULL
92a1f12d
JR		 75#define TSC_RATIO_MIN 0x0000000000000001ULL
76#define TSC_RATIO_MAX 0x000000ffffffffffULL
fbc0db76 77
67ec6607
JR		 78static bool erratum_383_found __read_mostly;
79
883b0a91 80u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
323c3d80 81
2b036c6b
BO		 82/*
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
85 */
86static uint64_t osvw_len = 4, osvw_status;
87
fbc0db76
JR		 88static DEFINE_PER_CPU(u64, current_tsc_ratio);
89#define TSC_RATIO_DEFAULT 0x0100000000ULL
90
09941fbb 91static const struct svm_direct_access_msrs {
ac72a9b7
JR		 92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
fd6fa73d 94} direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
8c06585d 95 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
97#ifdef CONFIG_X86_64
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
104#endif
b2ac58f9 105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
15d45071 106 { .index = MSR_IA32_PRED_CMD, .always = false },
ac72a9b7
JR		 107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
883b0a91 116bool npt_enabled = true;
709ddebf 117#else
883b0a91 118bool npt_enabled;
709ddebf 119#endif
6c7dac72 120
8566ac8b
BM		 121/*
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
131 *
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
148 * count only mode.
149 */
150
151static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152module_param(pause_filter_thresh, ushort, 0444);
153
154static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155module_param(pause_filter_count, ushort, 0444);
156
157/* Default doubles per-vcpu window every exit. */
158static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159module_param(pause_filter_count_grow, ushort, 0444);
160
161/* Default resets per-vcpu window every exit to pause_filter_count. */
162static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163module_param(pause_filter_count_shrink, ushort, 0444);
164
165/* Default is to compute the maximum so we can never overflow. */
166static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167module_param(pause_filter_count_max, ushort, 0444);
168
e2358851
DB		 169/* allow nested paging (virtualized MMU) for all guests */
170static int npt = true;
6c7dac72 171module_param(npt, int, S_IRUGO);
e3da3acd 172
e2358851
DB		 173/* allow nested virtualization in KVM/SVM */
174static int nested = true;
236de055
AG		 175module_param(nested, int, S_IRUGO);
176
d647eb63
PB		 177/* enable/disable Next RIP Save */
178static int nrips = true;
179module_param(nrips, int, 0444);
180
89c8a498
JN		 181/* enable/disable Virtual VMLOAD VMSAVE */
182static int vls = true;
183module_param(vls, int, 0444);
184
640bd6e5
JN		 185/* enable/disable Virtual GIF */
186static int vgif = true;
187module_param(vgif, int, 0444);
5ea11f2b 188
e9df0942 189/* enable/disable SEV support */
916391a2 190int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
e9df0942
BS		 191module_param(sev, int, 0444);
192
916391a2
TL		 193/* enable/disable SEV-ES support */
194int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
195module_param(sev_es, int, 0444);
196
6f2f8453
PB		 197static bool __read_mostly dump_invalid_vmcb = 0;
198module_param(dump_invalid_vmcb, bool, 0644);
199
7607b717
BS		 200static u8 rsm_ins_bytes[] = "\x0f\xaa";
201
a5c3832d 202static void svm_complete_interrupts(struct vcpu_svm *svm);
44a95dae 203
4866d5e3 204static unsigned long iopm_base;
6aa8b732
AK		 205
206struct kvm_ldttss_desc {
207 u16 limit0;
208 u16 base0;
e0231715
JR		 209 unsigned base1:8, type:5, dpl:2, p:1;
210 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 211 u32 base3;
212 u32 zero1;
213} __attribute__((packed));
214
eaf78265 215DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
6aa8b732 216
09941fbb 217static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
6aa8b732 218
9d8f549d 219#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 220#define MSRS_RANGE_SIZE 2048
221#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
222
883b0a91 223u32 svm_msrpm_offset(u32 msr)
455716fa
JR		 224{
225 u32 offset;
226 int i;
227
228 for (i = 0; i < NUM_MSR_MAPS; i++) {
229 if (msr < msrpm_ranges[i] ||
230 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
231 continue;
232
233 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
234 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
235
236 /* Now we have the u8 offset - but need the u32 offset */
237 return offset / 4;
238 }
239
240 /* MSR not in any range */
241 return MSR_INVALID;
242}
243
6aa8b732
AK		 244#define MAX_INST_SIZE 15
245
6aa8b732
AK		 246static inline void clgi(void)
247{
ac5ffda2 248 asm volatile (__ex("clgi"));
6aa8b732
AK		 249}
250
251static inline void stgi(void)
252{
ac5ffda2 253 asm volatile (__ex("stgi"));
6aa8b732
AK		 254}
255
256static inline void invlpga(unsigned long addr, u32 asid)
257{
ac5ffda2 258 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
6aa8b732
AK		 259}
260
d468d94b 261static int get_max_npt_level(void)
4b16184c
JR		 262{
263#ifdef CONFIG_X86_64
2a7266a8 264 return PT64_ROOT_4LEVEL;
4b16184c
JR		 265#else
266 return PT32E_ROOT_LEVEL;
267#endif
268}
269
72f211ec 270int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
6aa8b732 271{
c513f484 272 struct vcpu_svm *svm = to_svm(vcpu);
2fcf4876 273 u64 old_efer = vcpu->arch.efer;
6dc696d4 274 vcpu->arch.efer = efer;
9167ab79
PB		 275
276 if (!npt_enabled) {
277 /* Shadow paging assumes NX to be available. */
278 efer |= EFER_NX;
279
280 if (!(efer & EFER_LMA))
281 efer &= ~EFER_LME;
282 }
6aa8b732 283
2fcf4876
ML		 284 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
285 if (!(efer & EFER_SVME)) {
286 svm_leave_nested(svm);
287 svm_set_gif(svm, true);
288
289 /*
290 * Free the nested guest state, unless we are in SMM.
291 * In this case we will return to the nested guest
292 * as soon as we leave SMM.
293 */
294 if (!is_smm(&svm->vcpu))
295 svm_free_nested(svm);
296
297 } else {
298 int ret = svm_allocate_nested(svm);
299
300 if (ret) {
301 vcpu->arch.efer = old_efer;
302 return ret;
303 }
304 }
c513f484
PB		 305 }
306
307 svm->vmcb->save.efer = efer | EFER_SVME;
06e7852c 308 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
72f211ec 309 return 0;
6aa8b732
AK		 310}
311
6aa8b732
AK		 312static int is_external_interrupt(u32 info)
313{
314 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
315 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
316}
317
37ccdcbe 318static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 319{
320 struct vcpu_svm *svm = to_svm(vcpu);
321 u32 ret = 0;
322
323 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
37ccdcbe
PB		 324 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
325 return ret;
2809f5d2
GC		 326}
327
328static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
329{
330 struct vcpu_svm *svm = to_svm(vcpu);
331
332 if (mask == 0)
333 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
334 else
335 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
336
337}
338
f8ea7c60 339static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
6aa8b732 340{
a2fa3e9f
GH		 341 struct vcpu_svm *svm = to_svm(vcpu);
342
f1c6366e
TL		 343 /*
344 * SEV-ES does not expose the next RIP. The RIP update is controlled by
345 * the type of exit and the #VC handler in the guest.
346 */
347 if (sev_es_guest(vcpu->kvm))
348 goto done;
349
d647eb63 350 if (nrips && svm->vmcb->control.next_rip != 0) {
d2922422 351 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
6bc31bdc 352 svm->next_rip = svm->vmcb->control.next_rip;
f104765b 353 }
6bc31bdc 354
1957aa63
SC		 355 if (!svm->next_rip) {
356 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
357 return 0;
358 } else {
1957aa63
SC		 359 kvm_rip_write(vcpu, svm->next_rip);
360 }
f1c6366e
TL		 361
362done:
2809f5d2 363 svm_set_interrupt_shadow(vcpu, 0);
f8ea7c60 364
60fc3d02 365 return 1;
6aa8b732
AK		 366}
367
cfcd20e5 368static void svm_queue_exception(struct kvm_vcpu *vcpu)
116a4752
JK		 369{
370 struct vcpu_svm *svm = to_svm(vcpu);
cfcd20e5
WL		 371 unsigned nr = vcpu->arch.exception.nr;
372 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 373 u32 error_code = vcpu->arch.exception.error_code;
116a4752 374
da998b46
JM		 375 kvm_deliver_exception_payload(&svm->vcpu);
376
d647eb63 377 if (nr == BP_VECTOR && !nrips) {
66b7138f
JK		 378 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
379
380 /*
381 * For guest debugging where we have to reinject #BP if some
382 * INT3 is guest-owned:
383 * Emulate nRIP by moving RIP forward. Will fail if injection
384 * raises a fault that is not intercepted. Still better than
385 * failing in all cases.
386 */
f8ea7c60 387 (void)skip_emulated_instruction(&svm->vcpu);
66b7138f
JK		 388 rip = kvm_rip_read(&svm->vcpu);
389 svm->int3_rip = rip + svm->vmcb->save.cs.base;
390 svm->int3_injected = rip - old_rip;
391 }
392
116a4752
JK		 393 svm->vmcb->control.event_inj = nr
394 | SVM_EVTINJ_VALID
395 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
396 | SVM_EVTINJ_TYPE_EXEPT;
397 svm->vmcb->control.event_inj_err = error_code;
398}
399
67ec6607
JR		 400static void svm_init_erratum_383(void)
401{
402 u32 low, high;
403 int err;
404 u64 val;
405
e6ee94d5 406 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
67ec6607
JR		 407 return;
408
409 /* Use _safe variants to not break nested virtualization */
410 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
411 if (err)
412 return;
413
414 val |= (1ULL << 47);
415
416 low = lower_32_bits(val);
417 high = upper_32_bits(val);
418
419 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
420
421 erratum_383_found = true;
422}
423
2b036c6b
BO		 424static void svm_init_osvw(struct kvm_vcpu *vcpu)
425{
426 /*
427 * Guests should see errata 400 and 415 as fixed (assuming that
428 * HLT and IO instructions are intercepted).
429 */
430 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
431 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
432
433 /*
434 * By increasing VCPU's osvw.length to 3 we are telling the guest that
435 * all osvw.status bits inside that length, including bit 0 (which is
436 * reserved for erratum 298), are valid. However, if host processor's
437 * osvw_len is 0 then osvw_status[0] carries no information. We need to
438 * be conservative here and therefore we tell the guest that erratum 298
439 * is present (because we really don't know).
440 */
441 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
442 vcpu->arch.osvw.status |= 1;
443}
444
6aa8b732
AK		 445static int has_svm(void)
446{
63d1142f 447 const char *msg;
6aa8b732 448
63d1142f 449 if (!cpu_has_svm(&msg)) {
ff81ff10 450 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 451 return 0;
452 }
453
6aa8b732
AK		 454 return 1;
455}
456
13a34e06 457static void svm_hardware_disable(void)
6aa8b732 458{
fbc0db76
JR		 459 /* Make sure we clean up behind us */
460 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
461 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
462
2c8dceeb 463 cpu_svm_disable();
1018faa6
JR		 464
465 amd_pmu_disable_virt();
6aa8b732
AK		 466}
467
13a34e06 468static int svm_hardware_enable(void)
6aa8b732
AK		 469{
470
0fe1e009 471 struct svm_cpu_data *sd;
6aa8b732 472 uint64_t efer;
6aa8b732
AK		 473 struct desc_struct *gdt;
474 int me = raw_smp_processor_id();
475
10474ae8
AG		 476 rdmsrl(MSR_EFER, efer);
477 if (efer & EFER_SVME)
478 return -EBUSY;
479
6aa8b732 480 if (!has_svm()) {
1f5b77f5 481 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
10474ae8 482 return -EINVAL;
6aa8b732 483 }
0fe1e009 484 sd = per_cpu(svm_data, me);
0fe1e009 485 if (!sd) {
1f5b77f5 486 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
10474ae8 487 return -EINVAL;
6aa8b732
AK		 488 }
489
0fe1e009
TH		 490 sd->asid_generation = 1;
491 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
492 sd->next_asid = sd->max_asid + 1;
ed3cd233 493 sd->min_asid = max_sev_asid + 1;
6aa8b732 494
45fc8757 495 gdt = get_current_gdt_rw();
0fe1e009 496 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 497
9962d032 498 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 499
d0316554 500 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 501
fbc0db76
JR		 502 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
503 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
89cbc767 504 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
fbc0db76
JR		 505 }
506
2b036c6b
BO		 507
508 /*
509 * Get OSVW bits.
510 *
511 * Note that it is possible to have a system with mixed processor
512 * revisions and therefore different OSVW bits. If bits are not the same
513 * on different processors then choose the worst case (i.e. if erratum
514 * is present on one processor and not on another then assume that the
515 * erratum is present everywhere).
516 */
517 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
518 uint64_t len, status = 0;
519 int err;
520
521 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
522 if (!err)
523 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
524 &err);
525
526 if (err)
527 osvw_status = osvw_len = 0;
528 else {
529 if (len < osvw_len)
530 osvw_len = len;
531 osvw_status |= status;
532 osvw_status &= (1ULL << osvw_len) - 1;
533 }
534 } else
535 osvw_status = osvw_len = 0;
536
67ec6607
JR		 537 svm_init_erratum_383();
538
1018faa6
JR		 539 amd_pmu_enable_virt();
540
10474ae8 541 return 0;
6aa8b732
AK		 542}
543
0da1db75
JR		 544static void svm_cpu_uninit(int cpu)
545{
0fe1e009 546 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 547
0fe1e009 548 if (!sd)
0da1db75
JR		 549 return;
550
551 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
70cd94e6 552 kfree(sd->sev_vmcbs);
0fe1e009
TH		 553 __free_page(sd->save_area);
554 kfree(sd);
0da1db75
JR		 555}
556
6aa8b732
AK		 557static int svm_cpu_init(int cpu)
558{
0fe1e009 559 struct svm_cpu_data *sd;
6aa8b732 560
0fe1e009
TH		 561 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
562 if (!sd)
6aa8b732 563 return -ENOMEM;
0fe1e009 564 sd->cpu = cpu;
70cd94e6 565 sd->save_area = alloc_page(GFP_KERNEL);
0fe1e009 566 if (!sd->save_area)
d80b64ff 567 goto free_cpu_data;
6aa8b732 568
70cd94e6 569 if (svm_sev_enabled()) {
6da2ec56
KC		 570 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
571 sizeof(void *),
572 GFP_KERNEL);
70cd94e6 573 if (!sd->sev_vmcbs)
d80b64ff 574 goto free_save_area;
70cd94e6
BS		 575 }
576
0fe1e009 577 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 578
579 return 0;
580
d80b64ff
ML		 581free_save_area:
582 __free_page(sd->save_area);
583free_cpu_data:
0fe1e009 584 kfree(sd);
d80b64ff 585 return -ENOMEM;
6aa8b732
AK		 586
587}
588
fd6fa73d 589static int direct_access_msr_slot(u32 msr)
ac72a9b7 590{
fd6fa73d 591 u32 i;
ac72a9b7
JR		 592
593 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
fd6fa73d
AG		 594 if (direct_access_msrs[i].index == msr)
595 return i;
ac72a9b7 596
fd6fa73d
AG		 597 return -ENOENT;
598}
599
600static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
601 int write)
602{
603 struct vcpu_svm *svm = to_svm(vcpu);
604 int slot = direct_access_msr_slot(msr);
605
606 if (slot == -ENOENT)
607 return;
608
609 /* Set the shadow bitmaps to the desired intercept states */
610 if (read)
611 set_bit(slot, svm->shadow_msr_intercept.read);
612 else
613 clear_bit(slot, svm->shadow_msr_intercept.read);
614
615 if (write)
616 set_bit(slot, svm->shadow_msr_intercept.write);
617 else
618 clear_bit(slot, svm->shadow_msr_intercept.write);
ac72a9b7
JR		 619}
620
fd6fa73d
AG		 621static bool valid_msr_intercept(u32 index)
622{
623 return direct_access_msr_slot(index) != -ENOENT;
ac72a9b7
JR		 624}
625
476c9bd8 626static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
b2ac58f9
KA		 627{
628 u8 bit_write;
629 unsigned long tmp;
630 u32 offset;
631 u32 *msrpm;
632
633 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
634 to_svm(vcpu)->msrpm;
635
636 offset = svm_msrpm_offset(msr);
637 bit_write = 2 * (msr & 0x0f) + 1;
638 tmp = msrpm[offset];
639
640 BUG_ON(offset == MSR_INVALID);
641
642 return !!test_bit(bit_write, &tmp);
643}
644
fd6fa73d
AG		 645static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
646 u32 msr, int read, int write)
6aa8b732 647{
455716fa
JR		 648 u8 bit_read, bit_write;
649 unsigned long tmp;
650 u32 offset;
6aa8b732 651
ac72a9b7
JR		 652 /*
653 * If this warning triggers extend the direct_access_msrs list at the
654 * beginning of the file
655 */
656 WARN_ON(!valid_msr_intercept(msr));
657
fd6fa73d
AG		 658 /* Enforce non allowed MSRs to trap */
659 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
660 read = 0;
661
662 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
663 write = 0;
664
455716fa
JR		 665 offset = svm_msrpm_offset(msr);
666 bit_read = 2 * (msr & 0x0f);
667 bit_write = 2 * (msr & 0x0f) + 1;
668 tmp = msrpm[offset];
669
670 BUG_ON(offset == MSR_INVALID);
671
672 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
673 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
674
675 msrpm[offset] = tmp;
6aa8b732
AK		 676}
677
fd6fa73d
AG		 678static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
679 int read, int write)
6aa8b732 680{
fd6fa73d
AG		 681 set_shadow_msr_intercept(vcpu, msr, read, write);
682 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
683}
684
2fcf4876 685u32 *svm_vcpu_alloc_msrpm(void)
6aa8b732 686{
f4c847a9 687 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
476c9bd8 688 u32 *msrpm;
f4c847a9
ML		 689
690 if (!pages)
691 return NULL;
6aa8b732 692
f4c847a9 693 msrpm = page_address(pages);
f65c229c
JR		 694 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
695
476c9bd8
AL		 696 return msrpm;
697}
698
2fcf4876 699void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
476c9bd8
AL		 700{
701 int i;
702
ac72a9b7
JR		 703 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
704 if (!direct_access_msrs[i].always)
705 continue;
476c9bd8 706 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
ac72a9b7 707 }
f4c847a9 708}
ac72a9b7 709
2fcf4876
ML		 710
711void svm_vcpu_free_msrpm(u32 *msrpm)
f4c847a9
ML		 712{
713 __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
f65c229c
JR		 714}
715
fd6fa73d
AG		 716static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
717{
718 struct vcpu_svm *svm = to_svm(vcpu);
719 u32 i;
720
721 /*
722 * Set intercept permissions for all direct access MSRs again. They
723 * will automatically get filtered through the MSR filter, so we are
724 * back in sync after this.
725 */
726 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
727 u32 msr = direct_access_msrs[i].index;
728 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
729 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
730
731 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
ac72a9b7 732 }
f65c229c
JR		 733}
734
323c3d80
JR		 735static void add_msr_offset(u32 offset)
736{
737 int i;
738
739 for (i = 0; i < MSRPM_OFFSETS; ++i) {
740
741 /* Offset already in list? */
742 if (msrpm_offsets[i] == offset)
bfc733a7 743 return;
323c3d80
JR		 744
745 /* Slot used by another offset? */
746 if (msrpm_offsets[i] != MSR_INVALID)
747 continue;
748
749 /* Add offset to list */
750 msrpm_offsets[i] = offset;
751
752 return;
6aa8b732 753 }
323c3d80
JR		 754
755 /*
756 * If this BUG triggers the msrpm_offsets table has an overflow. Just
757 * increase MSRPM_OFFSETS in this case.
758 */
bfc733a7 759 BUG();
6aa8b732
AK		 760}
761
323c3d80 762static void init_msrpm_offsets(void)
f65c229c 763{
323c3d80 764 int i;
f65c229c 765
323c3d80
JR		 766 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
767
768 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
769 u32 offset;
770
771 offset = svm_msrpm_offset(direct_access_msrs[i].index);
772 BUG_ON(offset == MSR_INVALID);
773
774 add_msr_offset(offset);
775 }
f65c229c
JR		 776}
777
476c9bd8 778static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
24e09cbf 779{
476c9bd8 780 struct vcpu_svm *svm = to_svm(vcpu);
24e09cbf 781
0dc92119 782 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
476c9bd8
AL		 783 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
784 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
785 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
786 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
24e09cbf
JR		 787}
788
476c9bd8 789static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
24e09cbf 790{
476c9bd8 791 struct vcpu_svm *svm = to_svm(vcpu);
24e09cbf 792
0dc92119 793 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
476c9bd8
AL		 794 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
795 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
796 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
797 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
24e09cbf
JR		 798}
799
883b0a91 800void disable_nmi_singlestep(struct vcpu_svm *svm)
4aebd0e9
LP		 801{
802 svm->nmi_singlestep = false;
640bd6e5 803
ab2f4d73
LP		 804 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
805 /* Clear our flags if they were not set by the guest */
806 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
807 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
808 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
809 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
810 }
4aebd0e9
LP		 811}
812
8566ac8b
BM		 813static void grow_ple_window(struct kvm_vcpu *vcpu)
814{
815 struct vcpu_svm *svm = to_svm(vcpu);
816 struct vmcb_control_area *control = &svm->vmcb->control;
817 int old = control->pause_filter_count;
818
819 control->pause_filter_count = __grow_ple_window(old,
820 pause_filter_count,
821 pause_filter_count_grow,
822 pause_filter_count_max);
823
4f75bcc3 824 if (control->pause_filter_count != old) {
06e7852c 825 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 826 trace_kvm_ple_window_update(vcpu->vcpu_id,
827 control->pause_filter_count, old);
828 }
8566ac8b
BM		 829}
830
831static void shrink_ple_window(struct kvm_vcpu *vcpu)
832{
833 struct vcpu_svm *svm = to_svm(vcpu);
834 struct vmcb_control_area *control = &svm->vmcb->control;
835 int old = control->pause_filter_count;
836
837 control->pause_filter_count =
838 __shrink_ple_window(old,
839 pause_filter_count,
840 pause_filter_count_shrink,
841 pause_filter_count);
4f75bcc3 842 if (control->pause_filter_count != old) {
06e7852c 843 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
4f75bcc3
PX		 844 trace_kvm_ple_window_update(vcpu->vcpu_id,
845 control->pause_filter_count, old);
846 }
8566ac8b
BM		 847}
848
52918ed5
TL		 849/*
850 * The default MMIO mask is a single bit (excluding the present bit),
851 * which could conflict with the memory encryption bit. Check for
852 * memory encryption support and override the default MMIO mask if
853 * memory encryption is enabled.
854 */
855static __init void svm_adjust_mmio_mask(void)
856{
857 unsigned int enc_bit, mask_bit;
858 u64 msr, mask;
859
860 /* If there is no memory encryption support, use existing mask */
861 if (cpuid_eax(0x80000000) < 0x8000001f)
862 return;
863
864 /* If memory encryption is not enabled, use existing mask */
865 rdmsrl(MSR_K8_SYSCFG, msr);
866 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
867 return;
868
869 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
870 mask_bit = boot_cpu_data.x86_phys_bits;
871
872 /* Increment the mask bit if it is the same as the encryption bit */
873 if (enc_bit == mask_bit)
874 mask_bit++;
875
876 /*
877 * If the mask bit location is below 52, then some bits above the
878 * physical addressing limit will always be reserved, so use the
879 * rsvd_bits() function to generate the mask. This mask, along with
880 * the present bit, will be used to generate a page fault with
881 * PFER.RSV = 1.
882 *
883 * If the mask bit location is 52 (or above), then clear the mask.
884 */
885 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
886
e7581cac 887 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
52918ed5
TL		 888}
889
dd58f3c9
LR		 890static void svm_hardware_teardown(void)
891{
892 int cpu;
893
eaf78265
JR		 894 if (svm_sev_enabled())
895 sev_hardware_teardown();
dd58f3c9
LR		 896
897 for_each_possible_cpu(cpu)
898 svm_cpu_uninit(cpu);
899
900 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
901 iopm_base = 0;
902}
903
9b58b985
SC		 904static __init void svm_set_cpu_caps(void)
905{
906 kvm_set_cpu_caps();
907
408e9a31
PB		 908 supported_xss = 0;
909
a50718cc
SC		 910 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
911 if (nested) {
9b58b985
SC		 912 kvm_cpu_cap_set(X86_FEATURE_SVM);
913
4eb87460 914 if (nrips)
a50718cc
SC		 915 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
916
917 if (npt_enabled)
918 kvm_cpu_cap_set(X86_FEATURE_NPT);
919 }
920
93c380e7
SC		 921 /* CPUID 0x80000008 */
922 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
923 boot_cpu_has(X86_FEATURE_AMD_SSBD))
924 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
4407a797
BM		 925
926 /* Enable INVPCID feature */
927 kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
9b58b985
SC		 928}
929
6aa8b732
AK		 930static __init int svm_hardware_setup(void)
931{
932 int cpu;
933 struct page *iopm_pages;
f65c229c 934 void *iopm_va;
6aa8b732
AK		 935 int r;
936
6aa8b732
AK		 937 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
938
939 if (!iopm_pages)
940 return -ENOMEM;
c8681339
AL		 941
942 iopm_va = page_address(iopm_pages);
943 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 944 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
945
323c3d80
JR		 946 init_msrpm_offsets();
947
cfc48181
SC		 948 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
949
50a37eb4
JR		 950 if (boot_cpu_has(X86_FEATURE_NX))
951 kvm_enable_efer_bits(EFER_NX);
952
1b2fd70c
AG		 953 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
954 kvm_enable_efer_bits(EFER_FFXSR);
955
92a1f12d 956 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
92a1f12d 957 kvm_has_tsc_control = true;
bc9b961b
HZ		 958 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
959 kvm_tsc_scaling_ratio_frac_bits = 32;
92a1f12d
JR		 960 }
961
8566ac8b
BM		 962 /* Check for pause filtering support */
963 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
964 pause_filter_count = 0;
965 pause_filter_thresh = 0;
966 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
967 pause_filter_thresh = 0;
968 }
969
236de055
AG		 970 if (nested) {
971 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 972 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 973 }
974
916391a2
TL		 975 if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
976 sev_hardware_setup();
977 } else {
978 sev = false;
979 sev_es = false;
e9df0942
BS		 980 }
981
52918ed5
TL		 982 svm_adjust_mmio_mask();
983
3230bb47 984 for_each_possible_cpu(cpu) {
6aa8b732
AK		 985 r = svm_cpu_init(cpu);
986 if (r)
f65c229c 987 goto err;
6aa8b732 988 }
33bd6a0b 989
2a6b20b8 990 if (!boot_cpu_has(X86_FEATURE_NPT))
e3da3acd
JR		 991 npt_enabled = false;
992
213e0e1f 993 if (npt_enabled && !npt)
6c7dac72 994 npt_enabled = false;
6c7dac72 995
83013059 996 kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
213e0e1f 997 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
e3da3acd 998
d647eb63
PB		 999 if (nrips) {
1000 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1001 nrips = false;
1002 }
1003
5b8abf1f
SS		 1004 if (avic) {
1005 if (!npt_enabled ||
1006 !boot_cpu_has(X86_FEATURE_AVIC) ||
5881f737 1007 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
5b8abf1f 1008 avic = false;
5881f737 1009 } else {
5b8abf1f 1010 pr_info("AVIC enabled\n");
5881f737 1011
5881f737
SS		 1012 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1013 }
5b8abf1f 1014 }
44a95dae 1015
89c8a498
JN		 1016 if (vls) {
1017 if (!npt_enabled ||
5442c269 1018 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
89c8a498
JN		 1019 !IS_ENABLED(CONFIG_X86_64)) {
1020 vls = false;
1021 } else {
1022 pr_info("Virtual VMLOAD VMSAVE supported\n");
1023 }
1024 }
1025
640bd6e5
JN		 1026 if (vgif) {
1027 if (!boot_cpu_has(X86_FEATURE_VGIF))
1028 vgif = false;
1029 else
1030 pr_info("Virtual GIF supported\n");
1031 }
1032
9b58b985 1033 svm_set_cpu_caps();
66a6950f 1034
3edd6839
MG		 1035 /*
1036 * It seems that on AMD processors PTE's accessed bit is
1037 * being set by the CPU hardware before the NPF vmexit.
1038 * This is not expected behaviour and our tests fail because
1039 * of it.
1040 * A workaround here is to disable support for
1041 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1042 * In this case userspace can know if there is support using
1043 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1044 * it
1045 * If future AMD CPU models change the behaviour described above,
1046 * this variable can be changed accordingly
1047 */
1048 allow_smaller_maxphyaddr = !npt_enabled;
1049
6aa8b732
AK		 1050 return 0;
1051
f65c229c 1052err:
dd58f3c9 1053 svm_hardware_teardown();
6aa8b732
AK		 1054 return r;
1055}
1056
6aa8b732
AK		 1057static void init_seg(struct vmcb_seg *seg)
1058{
1059 seg->selector = 0;
1060 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 1061 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 1062 seg->limit = 0xffff;
1063 seg->base = 0;
1064}
1065
1066static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1067{
1068 seg->selector = 0;
1069 seg->attrib = SVM_SELECTOR_P_MASK | type;
1070 seg->limit = 0xffff;
1071 seg->base = 0;
1072}
1073
326e7425 1074static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
f4e1b3c8
ZA		 1075{
1076 struct vcpu_svm *svm = to_svm(vcpu);
1077 u64 g_tsc_offset = 0;
1078
2030753d 1079 if (is_guest_mode(vcpu)) {
e79f245d 1080 /* Write L1's TSC offset. */
f4e1b3c8
ZA		 1081 g_tsc_offset = svm->vmcb->control.tsc_offset -
1082 svm->nested.hsave->control.tsc_offset;
1083 svm->nested.hsave->control.tsc_offset = offset;
45c3af97
PB		 1084 }
1085
1086 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1087 svm->vmcb->control.tsc_offset - g_tsc_offset,
1088 offset);
f4e1b3c8
ZA		 1089
1090 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
116a0a23 1091
06e7852c 1092 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
326e7425 1093 return svm->vmcb->control.tsc_offset;
f4e1b3c8
ZA		 1094}
1095
4407a797
BM		 1096static void svm_check_invpcid(struct vcpu_svm *svm)
1097{
1098 /*
1099 * Intercept INVPCID instruction only if shadow page table is
1100 * enabled. Interception is not required with nested page table
1101 * enabled.
1102 */
1103 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1104 if (!npt_enabled)
1105 svm_set_intercept(svm, INTERCEPT_INVPCID);
1106 else
1107 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1108 }
1109}
1110
5690891b 1111static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 1112{
e6101a96
JR		 1113 struct vmcb_control_area *control = &svm->vmcb->control;
1114 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 1115
4ee546b4 1116 svm->vcpu.arch.hflags = 0;
bff78274 1117
830bd71f
BM		 1118 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1119 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1120 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1121 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1122 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1123 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
3bbf3565 1124 if (!kvm_vcpu_apicv_active(&svm->vcpu))
830bd71f 1125 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
6aa8b732 1126
5315c716 1127 set_dr_intercepts(svm);
6aa8b732 1128
18c918c5
JR		 1129 set_exception_intercept(svm, PF_VECTOR);
1130 set_exception_intercept(svm, UD_VECTOR);
1131 set_exception_intercept(svm, MC_VECTOR);
54a20552 1132 set_exception_intercept(svm, AC_VECTOR);
cbdb967a 1133 set_exception_intercept(svm, DB_VECTOR);
9718420e
LA		 1134 /*
1135 * Guest access to VMware backdoor ports could legitimately
1136 * trigger #GP because of TSS I/O permission bitmap.
1137 * We intercept those #GP and allow access to them anyway
1138 * as VMware does.
1139 */
1140 if (enable_vmware_backdoor)
1141 set_exception_intercept(svm, GP_VECTOR);
6aa8b732 1142
a284ba56
JR		 1143 svm_set_intercept(svm, INTERCEPT_INTR);
1144 svm_set_intercept(svm, INTERCEPT_NMI);
1145 svm_set_intercept(svm, INTERCEPT_SMI);
1146 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1147 svm_set_intercept(svm, INTERCEPT_RDPMC);
1148 svm_set_intercept(svm, INTERCEPT_CPUID);
1149 svm_set_intercept(svm, INTERCEPT_INVD);
1150 svm_set_intercept(svm, INTERCEPT_INVLPG);
1151 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1152 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1153 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1154 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1155 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1156 svm_set_intercept(svm, INTERCEPT_VMRUN);
1157 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1158 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1159 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1160 svm_set_intercept(svm, INTERCEPT_STGI);
1161 svm_set_intercept(svm, INTERCEPT_CLGI);
1162 svm_set_intercept(svm, INTERCEPT_SKINIT);
1163 svm_set_intercept(svm, INTERCEPT_WBINVD);
1164 svm_set_intercept(svm, INTERCEPT_XSETBV);
1165 svm_set_intercept(svm, INTERCEPT_RDPRU);
1166 svm_set_intercept(svm, INTERCEPT_RSM);
6aa8b732 1167
4d5422ce 1168 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
a284ba56
JR		 1169 svm_set_intercept(svm, INTERCEPT_MONITOR);
1170 svm_set_intercept(svm, INTERCEPT_MWAIT);
668fffa3
MT		 1171 }
1172
caa057a2 1173 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
a284ba56 1174 svm_set_intercept(svm, INTERCEPT_HLT);
caa057a2 1175
d0ec49d4
TL		 1176 control->iopm_base_pa = __sme_set(iopm_base);
1177 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
6aa8b732
AK		 1178 control->int_ctl = V_INTR_MASKING_MASK;
1179
1180 init_seg(&save->es);
1181 init_seg(&save->ss);
1182 init_seg(&save->ds);
1183 init_seg(&save->fs);
1184 init_seg(&save->gs);
1185
1186 save->cs.selector = 0xf000;
04b66839 1187 save->cs.base = 0xffff0000;
6aa8b732
AK		 1188 /* Executable/Readable Code Segment */
1189 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1190 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1191 save->cs.limit = 0xffff;
6aa8b732
AK		 1192
1193 save->gdtr.limit = 0xffff;
1194 save->idtr.limit = 0xffff;
1195
1196 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1197 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1198
5690891b 1199 svm_set_efer(&svm->vcpu, 0);
d77c26fc 1200 save->dr6 = 0xffff0ff0;
f6e78475 1201 kvm_set_rflags(&svm->vcpu, 2);
6aa8b732 1202 save->rip = 0x0000fff0;
5fdbf976 1203 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 1204
e0231715 1205 /*
18fa000a 1206 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
d28bc9dd 1207 * It also updates the guest-visible cr0 value.
6aa8b732 1208 */
79a8059d 1209 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
ebae871a 1210 kvm_mmu_reset_context(&svm->vcpu);
18fa000a 1211
66aee91a 1212 save->cr4 = X86_CR4_PAE;
6aa8b732 1213 /* rdx = ?? */
709ddebf
JR		 1214
1215 if (npt_enabled) {
1216 /* Setup VMCB for Nested Paging */
cea3a19b 1217 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
a284ba56 1218 svm_clr_intercept(svm, INTERCEPT_INVLPG);
18c918c5 1219 clr_exception_intercept(svm, PF_VECTOR);
830bd71f
BM		 1220 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1221 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
74545705 1222 save->g_pat = svm->vcpu.arch.pat;
709ddebf
JR		 1223 save->cr3 = 0;
1224 save->cr4 = 0;
1225 }
f40f6a45 1226 svm->asid_generation = 0;
7e8e6eed 1227 svm->asid = 0;
1371d904 1228
0dd16b5b 1229 svm->nested.vmcb12_gpa = 0;
2af9194d
JR		 1230 svm->vcpu.arch.hflags = 0;
1231
830f01b0 1232 if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
8566ac8b
BM		 1233 control->pause_filter_count = pause_filter_count;
1234 if (pause_filter_thresh)
1235 control->pause_filter_thresh = pause_filter_thresh;
a284ba56 1236 svm_set_intercept(svm, INTERCEPT_PAUSE);
8566ac8b 1237 } else {
a284ba56 1238 svm_clr_intercept(svm, INTERCEPT_PAUSE);
565d0998
ML		 1239 }
1240
4407a797
BM		 1241 svm_check_invpcid(svm);
1242
67034bb9 1243 if (kvm_vcpu_apicv_active(&svm->vcpu))
44a95dae
SS		 1244 avic_init_vmcb(svm);
1245
89c8a498
JN		 1246 /*
1247 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1248 * in VMCB and clear intercepts to avoid #VMEXIT.
1249 */
1250 if (vls) {
a284ba56
JR		 1251 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1252 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
89c8a498
JN		 1253 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1254 }
1255
640bd6e5 1256 if (vgif) {
a284ba56
JR		 1257 svm_clr_intercept(svm, INTERCEPT_STGI);
1258 svm_clr_intercept(svm, INTERCEPT_CLGI);
640bd6e5
JN		 1259 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1260 }
1261
35c6f649 1262 if (sev_guest(svm->vcpu.kvm)) {
1654efcb 1263 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
35c6f649
BS		 1264 clr_exception_intercept(svm, UD_VECTOR);
1265 }
1654efcb 1266
06e7852c 1267 vmcb_mark_all_dirty(svm->vmcb);
8d28fec4 1268
2af9194d 1269 enable_gif(svm);
44a95dae
SS		 1270
1271}
1272
d28bc9dd 1273static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
04d2cc77
AK		 1274{
1275 struct vcpu_svm *svm = to_svm(vcpu);
66f7b72e
JS		 1276 u32 dummy;
1277 u32 eax = 1;
04d2cc77 1278
b2ac58f9 1279 svm->spec_ctrl = 0;
ccbcd267 1280 svm->virt_spec_ctrl = 0;
b2ac58f9 1281
d28bc9dd
NA		 1282 if (!init_event) {
1283 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1284 MSR_IA32_APICBASE_ENABLE;
1285 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1286 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1287 }
5690891b 1288 init_vmcb(svm);
70433389 1289
f91af517 1290 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
de3cd117 1291 kvm_rdx_write(vcpu, eax);
44a95dae
SS		 1292
1293 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1294 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
04d2cc77
AK		 1295}
1296
987b2594 1297static int svm_create_vcpu(struct kvm_vcpu *vcpu)
6aa8b732 1298{
a2fa3e9f 1299 struct vcpu_svm *svm;
1feaba14 1300 struct page *vmcb_page;
add5e2f0 1301 struct page *vmsa_page = NULL;
fb3f0f51 1302 int err;
6aa8b732 1303
a9dd6f09
SC		 1304 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1305 svm = to_svm(vcpu);
fb3f0f51 1306
b7af4043 1307 err = -ENOMEM;
0681de1b 1308 vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1feaba14 1309 if (!vmcb_page)
987b2594 1310 goto out;
6aa8b732 1311
add5e2f0
TL		 1312 if (sev_es_guest(svm->vcpu.kvm)) {
1313 /*
1314 * SEV-ES guests require a separate VMSA page used to contain
1315 * the encrypted register state of the guest.
1316 */
1317 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1318 if (!vmsa_page)
1319 goto error_free_vmcb_page;
1320 }
1321
dfa20099
SS		 1322 err = avic_init_vcpu(svm);
1323 if (err)
add5e2f0 1324 goto error_free_vmsa_page;
44a95dae 1325
8221c137
SS		 1326 /* We initialize this flag to true to make sure that the is_running
1327 * bit would be set the first time the vcpu is loaded.
1328 */
6c3e4422
SS		 1329 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1330 svm->avic_is_running = true;
8221c137 1331
476c9bd8 1332 svm->msrpm = svm_vcpu_alloc_msrpm();
f4c847a9 1333 if (!svm->msrpm)
add5e2f0 1334 goto error_free_vmsa_page;
b7af4043 1335
476c9bd8 1336 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
3d6368ef 1337
1feaba14 1338 svm->vmcb = page_address(vmcb_page);
1feaba14 1339 svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
add5e2f0
TL		 1340
1341 if (vmsa_page)
1342 svm->vmsa = page_address(vmsa_page);
1343
a2fa3e9f 1344 svm->asid_generation = 0;
5690891b 1345 init_vmcb(svm);
6aa8b732 1346
7f27179a 1347 svm_init_osvw(vcpu);
bab0c318 1348 vcpu->arch.microcode_version = 0x01000065;
2b036c6b 1349
a9dd6f09 1350 return 0;
36241b8c 1351
add5e2f0
TL		 1352error_free_vmsa_page:
1353 if (vmsa_page)
1354 __free_page(vmsa_page);
8d22b90e 1355error_free_vmcb_page:
1feaba14 1356 __free_page(vmcb_page);
987b2594 1357out:
a9dd6f09 1358 return err;
6aa8b732
AK		 1359}
1360
fd65d314
JM		 1361static void svm_clear_current_vmcb(struct vmcb *vmcb)
1362{
1363 int i;
1364
1365 for_each_online_cpu(i)
1366 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1367}
1368
6aa8b732
AK		 1369static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1370{
a2fa3e9f
GH		 1371 struct vcpu_svm *svm = to_svm(vcpu);
1372
fd65d314
JM		 1373 /*
1374 * The vmcb page can be recycled, causing a false negative in
1375 * svm_vcpu_load(). So, ensure that no logical CPU has this
1376 * vmcb page recorded as its current vmcb.
1377 */
1378 svm_clear_current_vmcb(svm->vmcb);
1379
2fcf4876
ML		 1380 svm_free_nested(svm);
1381
add5e2f0
TL		 1382 sev_free_vcpu(vcpu);
1383
d0ec49d4 1384 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
f65c229c 1385 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
6aa8b732
AK		 1386}
1387
15ad7146 1388static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1389{
a2fa3e9f 1390 struct vcpu_svm *svm = to_svm(vcpu);
15d45071 1391 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
15ad7146 1392 int i;
0cc5064d 1393
0cc5064d 1394 if (unlikely(cpu != vcpu->cpu)) {
4b656b12 1395 svm->asid_generation = 0;
06e7852c 1396 vmcb_mark_all_dirty(svm->vmcb);
0cc5064d 1397 }
94dfbdb3 1398
82ca2d10
AK		 1399#ifdef CONFIG_X86_64
1400 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1401#endif
dacccfdd
AK		 1402 savesegment(fs, svm->host.fs);
1403 savesegment(gs, svm->host.gs);
1404 svm->host.ldt = kvm_read_ldt();
1405
94dfbdb3 1406 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1407 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
fbc0db76 1408
ad721883
HZ		 1409 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1410 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1411 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1412 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1413 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1414 }
fbc0db76 1415 }
46896c73
PB		 1416 /* This assumes that the kernel never uses MSR_TSC_AUX */
1417 if (static_cpu_has(X86_FEATURE_RDTSCP))
1418 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
8221c137 1419
15d45071
AR		 1420 if (sd->current_vmcb != svm->vmcb) {
1421 sd->current_vmcb = svm->vmcb;
1422 indirect_branch_prediction_barrier();
1423 }
8221c137 1424 avic_vcpu_load(vcpu, cpu);
6aa8b732
AK		 1425}
1426
1427static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1428{
a2fa3e9f 1429 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 1430 int i;
1431
8221c137
SS		 1432 avic_vcpu_put(vcpu);
1433
e1beb1d3 1434 ++vcpu->stat.host_state_reload;
dacccfdd
AK		 1435 kvm_load_ldt(svm->host.ldt);
1436#ifdef CONFIG_X86_64
1437 loadsegment(fs, svm->host.fs);
296f781a 1438 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
893a5ab6 1439 load_gs_index(svm->host.gs);
dacccfdd 1440#else
831ca609 1441#ifdef CONFIG_X86_32_LAZY_GS
dacccfdd 1442 loadsegment(gs, svm->host.gs);
831ca609 1443#endif
dacccfdd 1444#endif
94dfbdb3 1445 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 1446 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 1447}
1448
6aa8b732
AK		 1449static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1450{
9b611747
LP		 1451 struct vcpu_svm *svm = to_svm(vcpu);
1452 unsigned long rflags = svm->vmcb->save.rflags;
1453
1454 if (svm->nmi_singlestep) {
1455 /* Hide our flags if they were not set by the guest */
1456 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1457 rflags &= ~X86_EFLAGS_TF;
1458 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1459 rflags &= ~X86_EFLAGS_RF;
1460 }
1461 return rflags;
6aa8b732
AK		 1462}
1463
1464static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1465{
9b611747
LP		 1466 if (to_svm(vcpu)->nmi_singlestep)
1467 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1468
ae9fedc7 1469 /*
bb3541f1 1470 * Any change of EFLAGS.VM is accompanied by a reload of SS
ae9fedc7
PB		 1471 * (caused by either a task switch or an inter-privilege IRET),
1472 * so we do not need to update the CPL here.
1473 */
a2fa3e9f 1474 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 1475}
1476
6de4f3ad
AK		 1477static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1478{
1479 switch (reg) {
1480 case VCPU_EXREG_PDPTR:
1481 BUG_ON(!npt_enabled);
9f8fe504 1482 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6de4f3ad
AK		 1483 break;
1484 default:
34059c25 1485 WARN_ON_ONCE(1);
6de4f3ad
AK		 1486 }
1487}
1488
e14b7786 1489static void svm_set_vintr(struct vcpu_svm *svm)
64b5bd27
PB		 1490{
1491 struct vmcb_control_area *control;
1492
1493 /* The following fields are ignored when AVIC is enabled */
1494 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
a284ba56 1495 svm_set_intercept(svm, INTERCEPT_VINTR);
64b5bd27
PB		 1496
1497 /*
1498 * This is just a dummy VINTR to actually cause a vmexit to happen.
1499 * Actual injection of virtual interrupts happens through EVENTINJ.
1500 */
1501 control = &svm->vmcb->control;
1502 control->int_vector = 0x0;
1503 control->int_ctl &= ~V_INTR_PRIO_MASK;
1504 control->int_ctl |= V_IRQ_MASK |
1505 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
06e7852c 1506 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
64b5bd27
PB		 1507}
1508
f0b85051
AG		 1509static void svm_clear_vintr(struct vcpu_svm *svm)
1510{
d8e4e58f 1511 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
a284ba56 1512 svm_clr_intercept(svm, INTERCEPT_VINTR);
64b5bd27 1513
d8e4e58f
PB		 1514 /* Drop int_ctl fields related to VINTR injection. */
1515 svm->vmcb->control.int_ctl &= mask;
1516 if (is_guest_mode(&svm->vcpu)) {
fb7333df
PB		 1517 svm->nested.hsave->control.int_ctl &= mask;
1518
d8e4e58f
PB		 1519 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1520 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1521 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1522 }
1523
06e7852c 1524 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
f0b85051
AG		 1525}
1526
6aa8b732
AK		 1527static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1528{
a2fa3e9f 1529 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1530
1531 switch (seg) {
1532 case VCPU_SREG_CS: return &save->cs;
1533 case VCPU_SREG_DS: return &save->ds;
1534 case VCPU_SREG_ES: return &save->es;
1535 case VCPU_SREG_FS: return &save->fs;
1536 case VCPU_SREG_GS: return &save->gs;
1537 case VCPU_SREG_SS: return &save->ss;
1538 case VCPU_SREG_TR: return &save->tr;
1539 case VCPU_SREG_LDTR: return &save->ldtr;
1540 }
1541 BUG();
8b6d44c7 1542 return NULL;
6aa8b732
AK		 1543}
1544
1545static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1546{
1547 struct vmcb_seg *s = svm_seg(vcpu, seg);
1548
1549 return s->base;
1550}
1551
1552static void svm_get_segment(struct kvm_vcpu *vcpu,
1553 struct kvm_segment *var, int seg)
1554{
1555 struct vmcb_seg *s = svm_seg(vcpu, seg);
1556
1557 var->base = s->base;
1558 var->limit = s->limit;
1559 var->selector = s->selector;
1560 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1561 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1562 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1563 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1564 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1565 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1566 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
80112c89
JM		 1567
1568 /*
1569 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1570 * However, the SVM spec states that the G bit is not observed by the
1571 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1572 * So let's synthesize a legal G bit for all segments, this helps
1573 * running KVM nested. It also helps cross-vendor migration, because
1574 * Intel's vmentry has a check on the 'G' bit.
1575 */
1576 var->g = s->limit > 0xfffff;
25022acc 1577
e0231715
JR		 1578 /*
1579 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1580 * for cross vendor migration purposes by "not present"
1581 */
8eae9570 1582 var->unusable = !var->present;
19bca6ab 1583
1fbdc7a5 1584 switch (seg) {
1fbdc7a5
AP		 1585 case VCPU_SREG_TR:
1586 /*
1587 * Work around a bug where the busy flag in the tr selector
1588 * isn't exposed
1589 */
c0d09828 1590 var->type |= 0x2;
1fbdc7a5
AP		 1591 break;
1592 case VCPU_SREG_DS:
1593 case VCPU_SREG_ES:
1594 case VCPU_SREG_FS:
1595 case VCPU_SREG_GS:
1596 /*
1597 * The accessed bit must always be set in the segment
1598 * descriptor cache, although it can be cleared in the
1599 * descriptor, the cached bit always remains at 1. Since
1600 * Intel has a check on this, set it here to support
1601 * cross-vendor migration.
1602 */
1603 if (!var->unusable)
1604 var->type |= 0x1;
1605 break;
b586eb02 1606 case VCPU_SREG_SS:
e0231715
JR		 1607 /*
1608 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1609 * descriptor is left as 1, although the whole segment has
1610 * been made unusable. Clear it here to pass an Intel VMX
1611 * entry check when cross vendor migrating.
1612 */
1613 if (var->unusable)
1614 var->db = 0;
d9c1b543 1615 /* This is symmetric with svm_set_segment() */
33b458d2 1616 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
b586eb02 1617 break;
1fbdc7a5 1618 }
6aa8b732
AK		 1619}
1620
2e4d2653
IE		 1621static int svm_get_cpl(struct kvm_vcpu *vcpu)
1622{
1623 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1624
1625 return save->cpl;
1626}
1627
89a27f4d 1628static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1629{
a2fa3e9f
GH		 1630 struct vcpu_svm *svm = to_svm(vcpu);
1631
89a27f4d
GN		 1632 dt->size = svm->vmcb->save.idtr.limit;
1633 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1634}
1635
89a27f4d 1636static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1637{
a2fa3e9f
GH		 1638 struct vcpu_svm *svm = to_svm(vcpu);
1639
89a27f4d
GN		 1640 svm->vmcb->save.idtr.limit = dt->size;
1641 svm->vmcb->save.idtr.base = dt->address ;
06e7852c 1642 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1643}
1644
89a27f4d 1645static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1646{
a2fa3e9f
GH		 1647 struct vcpu_svm *svm = to_svm(vcpu);
1648
89a27f4d
GN		 1649 dt->size = svm->vmcb->save.gdtr.limit;
1650 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1651}
1652
89a27f4d 1653static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1654{
a2fa3e9f
GH		 1655 struct vcpu_svm *svm = to_svm(vcpu);
1656
89a27f4d
GN		 1657 svm->vmcb->save.gdtr.limit = dt->size;
1658 svm->vmcb->save.gdtr.base = dt->address ;
06e7852c 1659 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
6aa8b732
AK		 1660}
1661
d225157b
AK		 1662static void update_cr0_intercept(struct vcpu_svm *svm)
1663{
f1c6366e
TL		 1664 ulong gcr0;
1665 u64 *hcr0;
1666
1667 /*
1668 * SEV-ES guests must always keep the CR intercepts cleared. CR
1669 * tracking is done using the CR write traps.
1670 */
1671 if (sev_es_guest(svm->vcpu.kvm))
1672 return;
d225157b 1673
f1c6366e
TL		 1674 gcr0 = svm->vcpu.arch.cr0;
1675 hcr0 = &svm->vmcb->save.cr0;
bd7e5b08
PB		 1676 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1677 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
d225157b 1678
06e7852c 1679 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1680
bd7e5b08 1681 if (gcr0 == *hcr0) {
830bd71f
BM		 1682 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1683 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b 1684 } else {
830bd71f
BM		 1685 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1686 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
d225157b
AK		 1687 }
1688}
1689
883b0a91 1690void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 1691{
a2fa3e9f
GH		 1692 struct vcpu_svm *svm = to_svm(vcpu);
1693
05b3e0c2 1694#ifdef CONFIG_X86_64
f1c6366e 1695 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
707d92fa 1696 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1697 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1698 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1699 }
1700
d77c26fc 1701 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1702 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1703 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1704 }
1705 }
1706#endif
ad312c7c 1707 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1708
1709 if (!npt_enabled)
1710 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21 1711
bcf166a9
PB		 1712 /*
1713 * re-enable caching here because the QEMU bios
1714 * does not do it - this results in some delay at
1715 * reboot
1716 */
1717 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1718 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1719 svm->vmcb->save.cr0 = cr0;
06e7852c 1720 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
d225157b 1721 update_cr0_intercept(svm);
6aa8b732
AK		 1722}
1723
c2fe3cd4
SC		 1724static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1725{
1726 return true;
1727}
1728
1729void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 1730{
1e02ce4c 1731 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
dc924b06 1732 unsigned long old_cr4 = vcpu->arch.cr4;
e5eab0ce
JR		 1733
1734 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
f55ac304 1735 svm_flush_tlb(vcpu);
6394b649 1736
ec077263
JR		 1737 vcpu->arch.cr4 = cr4;
1738 if (!npt_enabled)
1739 cr4 |= X86_CR4_PAE;
6394b649 1740 cr4 |= host_cr4_mce;
ec077263 1741 to_svm(vcpu)->vmcb->save.cr4 = cr4;
06e7852c 1742 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2259c17f
JM		 1743
1744 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1745 kvm_update_cpuid_runtime(vcpu);
6aa8b732
AK		 1746}
1747
1748static void svm_set_segment(struct kvm_vcpu *vcpu,
1749 struct kvm_segment *var, int seg)
1750{
a2fa3e9f 1751 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1752 struct vmcb_seg *s = svm_seg(vcpu, seg);
1753
1754 s->base = var->base;
1755 s->limit = var->limit;
1756 s->selector = var->selector;
d9c1b543
RP		 1757 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1758 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1759 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1760 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1761 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1762 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1763 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1764 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
ae9fedc7
PB		 1765
1766 /*
1767 * This is always accurate, except if SYSRET returned to a segment
1768 * with SS.DPL != 3. Intel does not have this quirk, and always
1769 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1770 * would entail passing the CPL to userspace and back.
1771 */
1772 if (seg == VCPU_SREG_SS)
d9c1b543
RP		 1773 /* This is symmetric with svm_get_segment() */
1774 svm->vmcb->save.cpl = (var->dpl & 3);
6aa8b732 1775
06e7852c 1776 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
6aa8b732
AK		 1777}
1778
6986982f 1779static void update_exception_bitmap(struct kvm_vcpu *vcpu)
6aa8b732 1780{
d0bfb940
JK		 1781 struct vcpu_svm *svm = to_svm(vcpu);
1782
18c918c5 1783 clr_exception_intercept(svm, BP_VECTOR);
44c11430 1784
d0bfb940 1785 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940 1786 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
18c918c5 1787 set_exception_intercept(svm, BP_VECTOR);
6986982f 1788 }
44c11430
GN		 1789}
1790
0fe1e009 1791static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1792{
0fe1e009
TH		 1793 if (sd->next_asid > sd->max_asid) {
1794 ++sd->asid_generation;
4faefff3 1795 sd->next_asid = sd->min_asid;
a2fa3e9f 1796 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
7e8e6eed 1797 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
6aa8b732
AK		 1798 }
1799
0fe1e009 1800 svm->asid_generation = sd->asid_generation;
7e8e6eed 1801 svm->asid = sd->next_asid++;
6aa8b732
AK		 1802}
1803
d67668e9 1804static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
73aaf249 1805{
d67668e9 1806 struct vmcb *vmcb = svm->vmcb;
73aaf249 1807
8d4846b9
TL		 1808 if (svm->vcpu.arch.guest_state_protected)
1809 return;
1810
d67668e9
PB		 1811 if (unlikely(value != vmcb->save.dr6)) {
1812 vmcb->save.dr6 = value;
06e7852c 1813 vmcb_mark_dirty(vmcb, VMCB_DR);
d67668e9 1814 }
73aaf249
JK		 1815}
1816
facb0139
PB		 1817static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1818{
1819 struct vcpu_svm *svm = to_svm(vcpu);
1820
8d4846b9
TL		 1821 if (vcpu->arch.guest_state_protected)
1822 return;
1823
facb0139
PB		 1824 get_debugreg(vcpu->arch.db[0], 0);
1825 get_debugreg(vcpu->arch.db[1], 1);
1826 get_debugreg(vcpu->arch.db[2], 2);
1827 get_debugreg(vcpu->arch.db[3], 3);
d67668e9
PB		 1828 /*
1829 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1830 * because db_interception might need it. We can do it before vmentry.
1831 */
5679b803 1832 vcpu->arch.dr6 = svm->vmcb->save.dr6;
facb0139 1833 vcpu->arch.dr7 = svm->vmcb->save.dr7;
facb0139
PB		 1834 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1835 set_dr_intercepts(svm);
1836}
1837
020df079 1838static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1839{
42dbaa5a 1840 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1841
8d4846b9
TL		 1842 if (vcpu->arch.guest_state_protected)
1843 return;
1844
020df079 1845 svm->vmcb->save.dr7 = value;
06e7852c 1846 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
6aa8b732
AK		 1847}
1848
851ba692 1849static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1850{
0ede79e1 1851 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1261bfa3 1852 u64 error_code = svm->vmcb->control.exit_info_1;
6aa8b732 1853
1261bfa3 1854 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
00b10fe1
BS		 1855 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1856 svm->vmcb->control.insn_bytes : NULL,
d0006530
PB		 1857 svm->vmcb->control.insn_len);
1858}
1859
1860static int npf_interception(struct vcpu_svm *svm)
1861{
0ede79e1 1862 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
d0006530
PB		 1863 u64 error_code = svm->vmcb->control.exit_info_1;
1864
1865 trace_kvm_page_fault(fault_address, error_code);
1866 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
00b10fe1
BS		 1867 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1868 svm->vmcb->control.insn_bytes : NULL,
d0006530 1869 svm->vmcb->control.insn_len);
6aa8b732
AK		 1870}
1871
851ba692 1872static int db_interception(struct vcpu_svm *svm)
d0bfb940 1873{
851ba692 1874 struct kvm_run *kvm_run = svm->vcpu.run;
99c22179 1875 struct kvm_vcpu *vcpu = &svm->vcpu;
851ba692 1876
d0bfb940 1877 if (!(svm->vcpu.guest_debug &
44c11430 1878 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1879 !svm->nmi_singlestep) {
d67668e9
PB		 1880 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1881 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
d0bfb940
JK		 1882 return 1;
1883 }
44c11430 1884
6be7d306 1885 if (svm->nmi_singlestep) {
4aebd0e9 1886 disable_nmi_singlestep(svm);
99c22179
VK		 1887 /* Make sure we check for pending NMIs upon entry */
1888 kvm_make_request(KVM_REQ_EVENT, vcpu);
44c11430
GN		 1889 }
1890
1891 if (svm->vcpu.guest_debug &
e0231715 1892 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430 1893 kvm_run->exit_reason = KVM_EXIT_DEBUG;
dee919d1
PB		 1894 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1895 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
44c11430
GN		 1896 kvm_run->debug.arch.pc =
1897 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1898 kvm_run->debug.arch.exception = DB_VECTOR;
1899 return 0;
1900 }
1901
1902 return 1;
d0bfb940
JK		 1903}
1904
851ba692 1905static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1906{
851ba692
AK		 1907 struct kvm_run *kvm_run = svm->vcpu.run;
1908
d0bfb940
JK		 1909 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1910 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1911 kvm_run->debug.arch.exception = BP_VECTOR;
1912 return 0;
1913}
1914
851ba692 1915static int ud_interception(struct vcpu_svm *svm)
7aa81cc0 1916{
082d06ed 1917 return handle_ud(&svm->vcpu);
7aa81cc0
AL		 1918}
1919
54a20552
EN		 1920static int ac_interception(struct vcpu_svm *svm)
1921{
1922 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1923 return 1;
1924}
1925
9718420e
LA		 1926static int gp_interception(struct vcpu_svm *svm)
1927{
1928 struct kvm_vcpu *vcpu = &svm->vcpu;
1929 u32 error_code = svm->vmcb->control.exit_info_1;
9718420e
LA		 1930
1931 WARN_ON_ONCE(!enable_vmware_backdoor);
1932
a6c6ed1e
SC		 1933 /*
1934 * VMware backdoor emulation on #GP interception only handles IN{S},
1935 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1936 */
1937 if (error_code) {
1938 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1939 return 1;
1940 }
60fc3d02 1941 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
9718420e
LA		 1942}
1943
67ec6607
JR		 1944static bool is_erratum_383(void)
1945{
1946 int err, i;
1947 u64 value;
1948
1949 if (!erratum_383_found)
1950 return false;
1951
1952 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1953 if (err)
1954 return false;
1955
1956 /* Bit 62 may or may not be set for this mce */
1957 value &= ~(1ULL << 62);
1958
1959 if (value != 0xb600000000010015ULL)
1960 return false;
1961
1962 /* Clear MCi_STATUS registers */
1963 for (i = 0; i < 6; ++i)
1964 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1965
1966 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1967 if (!err) {
1968 u32 low, high;
1969
1970 value &= ~(1ULL << 2);
1971 low = lower_32_bits(value);
1972 high = upper_32_bits(value);
1973
1974 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1975 }
1976
1977 /* Flush tlb to evict multi-match entries */
1978 __flush_tlb_all();
1979
1980 return true;
1981}
1982
fe5913e4 1983static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1984{
67ec6607
JR		 1985 if (is_erratum_383()) {
1986 /*
1987 * Erratum 383 triggered. Guest state is corrupt so kill the
1988 * guest.
1989 */
1990 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1991
a8eeb04a 1992 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1993
1994 return;
1995 }
1996
53371b50
JR		 1997 /*
1998 * On an #MC intercept the MCE handler is not called automatically in
1999 * the host. So do it by hand here.
2000 */
1c164cb3 2001 kvm_machine_check();
fe5913e4
JR		 2002}
2003
2004static int mc_interception(struct vcpu_svm *svm)
2005{
53371b50
JR		 2006 return 1;
2007}
2008
851ba692 2009static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 2010{
851ba692
AK		 2011 struct kvm_run *kvm_run = svm->vcpu.run;
2012
46fe4ddd
JR		 2013 /*
2014 * VMCB is undefined after a SHUTDOWN intercept
2015 * so reinitialize it.
2016 */
a2fa3e9f 2017 clear_page(svm->vmcb);
5690891b 2018 init_vmcb(svm);
46fe4ddd
JR		 2019
2020 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2021 return 0;
2022}
2023
851ba692 2024static int io_interception(struct vcpu_svm *svm)
6aa8b732 2025{
cf8f70bf 2026 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 2027 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
dca7f128 2028 int size, in, string;
039576c0 2029 unsigned port;
6aa8b732 2030
e756fc62 2031 ++svm->vcpu.stat.io_exits;
e70669ab 2032 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 2033 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
8370c3d0 2034 if (string)
60fc3d02 2035 return kvm_emulate_instruction(vcpu, 0);
cf8f70bf 2036
039576c0
AK		 2037 port = io_info >> 16;
2038 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 2039 svm->next_rip = svm->vmcb->control.exit_info_2;
cf8f70bf 2040
dca7f128 2041 return kvm_fast_pio(&svm->vcpu, size, port, in);
6aa8b732
AK		 2042}
2043
851ba692 2044static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 2045{
2046 return 1;
2047}
2048
851ba692 2049static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 2050{
2051 ++svm->vcpu.stat.irq_exits;
2052 return 1;
2053}
2054
851ba692 2055static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 2056{
2057 return 1;
2058}
2059
851ba692 2060static int halt_interception(struct vcpu_svm *svm)
6aa8b732 2061{
e756fc62 2062 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 2063}
2064
851ba692 2065static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 2066{
0d9c055e 2067 return kvm_emulate_hypercall(&svm->vcpu);
02e235bc
AK		 2068}
2069
851ba692 2070static int vmload_interception(struct vcpu_svm *svm)
5542675b 2071{
9966bf68 2072 struct vmcb *nested_vmcb;
8c5fbf1a 2073 struct kvm_host_map map;
b742c1e6 2074 int ret;
9966bf68 2075
5542675b
AG		 2076 if (nested_svm_check_permissions(svm))
2077 return 1;
2078
8c5fbf1a
KA		 2079 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2080 if (ret) {
2081 if (ret == -EINVAL)
2082 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 2083 return 1;
8c5fbf1a
KA		 2084 }
2085
2086 nested_vmcb = map.hva;
9966bf68 2087
b742c1e6 2088 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 2089
9966bf68 2090 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
8c5fbf1a 2091 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 2092
b742c1e6 2093 return ret;
5542675b
AG		 2094}
2095
851ba692 2096static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2097{
9966bf68 2098 struct vmcb *nested_vmcb;
8c5fbf1a 2099 struct kvm_host_map map;
b742c1e6 2100 int ret;
9966bf68 2101
5542675b
AG		 2102 if (nested_svm_check_permissions(svm))
2103 return 1;
2104
8c5fbf1a
KA		 2105 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2106 if (ret) {
2107 if (ret == -EINVAL)
2108 kvm_inject_gp(&svm->vcpu, 0);
9966bf68 2109 return 1;
8c5fbf1a
KA		 2110 }
2111
2112 nested_vmcb = map.hva;
9966bf68 2113
b742c1e6 2114 ret = kvm_skip_emulated_instruction(&svm->vcpu);
e3e9ed3d 2115
9966bf68 2116 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
8c5fbf1a 2117 kvm_vcpu_unmap(&svm->vcpu, &map, true);
5542675b 2118
b742c1e6 2119 return ret;
5542675b
AG		 2120}
2121
851ba692 2122static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2123{
3d6368ef
AG		 2124 if (nested_svm_check_permissions(svm))
2125 return 1;
2126
e7134c1b 2127 return nested_svm_vmrun(svm);
3d6368ef
AG		 2128}
2129
ffdf7f9e
PB		 2130void svm_set_gif(struct vcpu_svm *svm, bool value)
2131{
2132 if (value) {
2133 /*
2134 * If VGIF is enabled, the STGI intercept is only added to
2135 * detect the opening of the SMI/NMI window; remove it now.
2136 * Likewise, clear the VINTR intercept, we will set it
2137 * again while processing KVM_REQ_EVENT if needed.
2138 */
2139 if (vgif_enabled(svm))
a284ba56
JR		 2140 svm_clr_intercept(svm, INTERCEPT_STGI);
2141 if (svm_is_intercept(svm, INTERCEPT_VINTR))
ffdf7f9e
PB		 2142 svm_clear_vintr(svm);
2143
2144 enable_gif(svm);
2145 if (svm->vcpu.arch.smi_pending ||
2146 svm->vcpu.arch.nmi_pending ||
2147 kvm_cpu_has_injectable_intr(&svm->vcpu))
2148 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2149 } else {
2150 disable_gif(svm);
2151
2152 /*
2153 * After a CLGI no interrupts should come. But if vGIF is
2154 * in use, we still rely on the VINTR intercept (rather than
2155 * STGI) to detect an open interrupt window.
2156 */
2157 if (!vgif_enabled(svm))
2158 svm_clear_vintr(svm);
2159 }
2160}
2161
851ba692 2162static int stgi_interception(struct vcpu_svm *svm)
1371d904 2163{
b742c1e6
LP		 2164 int ret;
2165
1371d904
AG		 2166 if (nested_svm_check_permissions(svm))
2167 return 1;
2168
b742c1e6 2169 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2170 svm_set_gif(svm, true);
b742c1e6 2171 return ret;
1371d904
AG		 2172}
2173
851ba692 2174static int clgi_interception(struct vcpu_svm *svm)
1371d904 2175{
b742c1e6
LP		 2176 int ret;
2177
1371d904
AG		 2178 if (nested_svm_check_permissions(svm))
2179 return 1;
2180
b742c1e6 2181 ret = kvm_skip_emulated_instruction(&svm->vcpu);
ffdf7f9e 2182 svm_set_gif(svm, false);
b742c1e6 2183 return ret;
1371d904
AG		 2184}
2185
851ba692 2186static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2187{
2188 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2189
de3cd117
SC		 2190 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2191 kvm_rax_read(&svm->vcpu));
ec1ff790 2192
ff092385 2193 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
de3cd117 2194 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
ff092385 2195
b742c1e6 2196 return kvm_skip_emulated_instruction(&svm->vcpu);
ff092385
AG		 2197}
2198
532a46b9
JR		 2199static int skinit_interception(struct vcpu_svm *svm)
2200{
de3cd117 2201 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
532a46b9
JR		 2202
2203 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2204 return 1;
2205}
2206
dab429a7
DK		 2207static int wbinvd_interception(struct vcpu_svm *svm)
2208{
6affcbed 2209 return kvm_emulate_wbinvd(&svm->vcpu);
dab429a7
DK		 2210}
2211
81dd35d4
JR		 2212static int xsetbv_interception(struct vcpu_svm *svm)
2213{
2214 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
de3cd117 2215 u32 index = kvm_rcx_read(&svm->vcpu);
81dd35d4
JR		 2216
2217 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
b742c1e6 2218 return kvm_skip_emulated_instruction(&svm->vcpu);
81dd35d4
JR		 2219 }
2220
2221 return 1;
2222}
2223
0cb8410b
JM		 2224static int rdpru_interception(struct vcpu_svm *svm)
2225{
2226 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2227 return 1;
2228}
2229
851ba692 2230static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2231{
37817f29 2232 u16 tss_selector;
64a7ec06
GN		 2233 int reason;
2234 int int_type = svm->vmcb->control.exit_int_info &
2235 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2236 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2237 uint32_t type =
2238 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2239 uint32_t idt_v =
2240 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2241 bool has_error_code = false;
2242 u32 error_code = 0;
37817f29
IE		 2243
2244 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2245
37817f29
IE		 2246 if (svm->vmcb->control.exit_info_2 &
2247 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2248 reason = TASK_SWITCH_IRET;
2249 else if (svm->vmcb->control.exit_info_2 &
2250 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2251 reason = TASK_SWITCH_JMP;
fe8e7f83 2252 else if (idt_v)
64a7ec06
GN		 2253 reason = TASK_SWITCH_GATE;
2254 else
2255 reason = TASK_SWITCH_CALL;
2256
fe8e7f83
GN		 2257 if (reason == TASK_SWITCH_GATE) {
2258 switch (type) {
2259 case SVM_EXITINTINFO_TYPE_NMI:
2260 svm->vcpu.arch.nmi_injected = false;
2261 break;
2262 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2263 if (svm->vmcb->control.exit_info_2 &
2264 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2265 has_error_code = true;
2266 error_code =
2267 (u32)svm->vmcb->control.exit_info_2;
2268 }
fe8e7f83
GN		 2269 kvm_clear_exception_queue(&svm->vcpu);
2270 break;
2271 case SVM_EXITINTINFO_TYPE_INTR:
2272 kvm_clear_interrupt_queue(&svm->vcpu);
2273 break;
2274 default:
2275 break;
2276 }
2277 }
64a7ec06 2278
8317c298
GN		 2279 if (reason != TASK_SWITCH_GATE ||
2280 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2281 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f8ea7c60 2282 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
60fc3d02 2283 if (!skip_emulated_instruction(&svm->vcpu))
738fece4 2284 return 0;
f8ea7c60 2285 }
64a7ec06 2286
7f3d35fd
KW		 2287 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2288 int_vec = -1;
2289
1051778f 2290 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
60fc3d02 2291 has_error_code, error_code);
6aa8b732
AK		 2292}
2293
851ba692 2294static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2295{
6a908b62 2296 return kvm_emulate_cpuid(&svm->vcpu);
6aa8b732
AK		 2297}
2298
851ba692 2299static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2300{
2301 ++svm->vcpu.stat.nmi_window_exits;
a284ba56 2302 svm_clr_intercept(svm, INTERCEPT_IRET);
44c11430 2303 svm->vcpu.arch.hflags |= HF_IRET_MASK;
bd3d1ec3 2304 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
f303b4ce 2305 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
95ba8273
GN		 2306 return 1;
2307}
2308
4bb05f30
TL		 2309static int invd_interception(struct vcpu_svm *svm)
2310{
2311 /* Treat an INVD instruction as a NOP and just skip it. */
2312 return kvm_skip_emulated_instruction(&svm->vcpu);
2313}
2314
851ba692 2315static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2316{
df4f3108 2317 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
60fc3d02 2318 return kvm_emulate_instruction(&svm->vcpu, 0);
df4f3108
AP		 2319
2320 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
b742c1e6 2321 return kvm_skip_emulated_instruction(&svm->vcpu);
a7052897
MT		 2322}
2323
851ba692 2324static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2325{
60fc3d02 2326 return kvm_emulate_instruction(&svm->vcpu, 0);
6aa8b732
AK		 2327}
2328
7607b717
BS		 2329static int rsm_interception(struct vcpu_svm *svm)
2330{
60fc3d02 2331 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
7607b717
BS		 2332}
2333
332b56e4
AK		 2334static int rdpmc_interception(struct vcpu_svm *svm)
2335{
2336 int err;
2337
d647eb63 2338 if (!nrips)
332b56e4
AK		 2339 return emulate_on_interception(svm);
2340
2341 err = kvm_rdpmc(&svm->vcpu);
6affcbed 2342 return kvm_complete_insn_gp(&svm->vcpu, err);
332b56e4
AK		 2343}
2344
52eb5a6d
XL		 2345static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2346 unsigned long val)
628afd2a
JR		 2347{
2348 unsigned long cr0 = svm->vcpu.arch.cr0;
2349 bool ret = false;
628afd2a
JR		 2350
2351 if (!is_guest_mode(&svm->vcpu) ||
c62e2e94 2352 (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
628afd2a
JR		 2353 return false;
2354
2355 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2356 val &= ~SVM_CR0_SELECTIVE_MASK;
2357
2358 if (cr0 ^ val) {
2359 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2360 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2361 }
2362
2363 return ret;
2364}
2365
7ff76d58
AP		 2366#define CR_VALID (1ULL << 63)
2367
2368static int cr_interception(struct vcpu_svm *svm)
2369{
2370 int reg, cr;
2371 unsigned long val;
2372 int err;
2373
2374 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2375 return emulate_on_interception(svm);
2376
2377 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2378 return emulate_on_interception(svm);
2379
2380 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
5e57518d
DK		 2381 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2382 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2383 else
2384 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
7ff76d58
AP		 2385
2386 err = 0;
2387 if (cr >= 16) { /* mov to cr */
2388 cr -= 16;
2389 val = kvm_register_read(&svm->vcpu, reg);
95b28ac9 2390 trace_kvm_cr_write(cr, val);
7ff76d58
AP		 2391 switch (cr) {
2392 case 0:
628afd2a
JR		 2393 if (!check_selective_cr0_intercepted(svm, val))
2394 err = kvm_set_cr0(&svm->vcpu, val);
977b2d03
JR		 2395 else
2396 return 1;
2397
7ff76d58
AP		 2398 break;
2399 case 3:
2400 err = kvm_set_cr3(&svm->vcpu, val);
2401 break;
2402 case 4:
2403 err = kvm_set_cr4(&svm->vcpu, val);
2404 break;
2405 case 8:
2406 err = kvm_set_cr8(&svm->vcpu, val);
2407 break;
2408 default:
2409 WARN(1, "unhandled write to CR%d", cr);
2410 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2411 return 1;
2412 }
2413 } else { /* mov from cr */
2414 switch (cr) {
2415 case 0:
2416 val = kvm_read_cr0(&svm->vcpu);
2417 break;
2418 case 2:
2419 val = svm->vcpu.arch.cr2;
2420 break;
2421 case 3:
9f8fe504 2422 val = kvm_read_cr3(&svm->vcpu);
7ff76d58
AP		 2423 break;
2424 case 4:
2425 val = kvm_read_cr4(&svm->vcpu);
2426 break;
2427 case 8:
2428 val = kvm_get_cr8(&svm->vcpu);
2429 break;
2430 default:
2431 WARN(1, "unhandled read from CR%d", cr);
2432 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2433 return 1;
2434 }
2435 kvm_register_write(&svm->vcpu, reg, val);
95b28ac9 2436 trace_kvm_cr_read(cr, val);
7ff76d58 2437 }
6affcbed 2438 return kvm_complete_insn_gp(&svm->vcpu, err);
7ff76d58
AP		 2439}
2440
cae3797a
AP		 2441static int dr_interception(struct vcpu_svm *svm)
2442{
2443 int reg, dr;
2444 unsigned long val;
cae3797a 2445
facb0139
PB		 2446 if (svm->vcpu.guest_debug == 0) {
2447 /*
2448 * No more DR vmexits; force a reload of the debug registers
2449 * and reenter on this instruction. The next vmexit will
2450 * retrieve the full state of the debug registers.
2451 */
2452 clr_dr_intercepts(svm);
2453 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2454 return 1;
2455 }
2456
cae3797a
AP		 2457 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2458 return emulate_on_interception(svm);
2459
2460 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2461 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2462
2463 if (dr >= 16) { /* mov to DRn */
16f8a6f9
NA		 2464 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2465 return 1;
cae3797a
AP		 2466 val = kvm_register_read(&svm->vcpu, reg);
2467 kvm_set_dr(&svm->vcpu, dr - 16, val);
2468 } else {
16f8a6f9
NA		 2469 if (!kvm_require_dr(&svm->vcpu, dr))
2470 return 1;
2471 kvm_get_dr(&svm->vcpu, dr, &val);
2472 kvm_register_write(&svm->vcpu, reg, val);
cae3797a
AP		 2473 }
2474
b742c1e6 2475 return kvm_skip_emulated_instruction(&svm->vcpu);
cae3797a
AP		 2476}
2477
851ba692 2478static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2479{
851ba692 2480 struct kvm_run *kvm_run = svm->vcpu.run;
eea1cff9 2481 int r;
851ba692 2482
0a5fff19
GN		 2483 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2484 /* instruction emulation calls kvm_set_cr8() */
7ff76d58 2485 r = cr_interception(svm);
35754c98 2486 if (lapic_in_kernel(&svm->vcpu))
7ff76d58 2487 return r;
0a5fff19 2488 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
7ff76d58 2489 return r;
1d075434
JR		 2490 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2491 return 0;
2492}
2493
801e459a
TL		 2494static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2495{
d1d93fa9
TL		 2496 msr->data = 0;
2497
2498 switch (msr->index) {
2499 case MSR_F10H_DECFG:
2500 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2501 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2502 break;
d574c539
VK		 2503 case MSR_IA32_PERF_CAPABILITIES:
2504 return 0;
d1d93fa9 2505 default:
12bc2132 2506 return KVM_MSR_RET_INVALID;
d1d93fa9
TL		 2507 }
2508
2509 return 0;
801e459a
TL		 2510}
2511
609e36d3 2512static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2513{
a2fa3e9f
GH		 2514 struct vcpu_svm *svm = to_svm(vcpu);
2515
609e36d3 2516 switch (msr_info->index) {
8c06585d 2517 case MSR_STAR:
609e36d3 2518 msr_info->data = svm->vmcb->save.star;
6aa8b732 2519 break;
0e859cac 2520#ifdef CONFIG_X86_64
6aa8b732 2521 case MSR_LSTAR:
609e36d3 2522 msr_info->data = svm->vmcb->save.lstar;
6aa8b732
AK		 2523 break;
2524 case MSR_CSTAR:
609e36d3 2525 msr_info->data = svm->vmcb->save.cstar;
6aa8b732
AK		 2526 break;
2527 case MSR_KERNEL_GS_BASE:
609e36d3 2528 msr_info->data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2529 break;
2530 case MSR_SYSCALL_MASK:
609e36d3 2531 msr_info->data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2532 break;
2533#endif
2534 case MSR_IA32_SYSENTER_CS:
609e36d3 2535 msr_info->data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2536 break;
2537 case MSR_IA32_SYSENTER_EIP:
609e36d3 2538 msr_info->data = svm->sysenter_eip;
6aa8b732
AK		 2539 break;
2540 case MSR_IA32_SYSENTER_ESP:
609e36d3 2541 msr_info->data = svm->sysenter_esp;
6aa8b732 2542 break;
46896c73
PB		 2543 case MSR_TSC_AUX:
2544 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2545 return 1;
2546 msr_info->data = svm->tsc_aux;
2547 break;
e0231715
JR		 2548 /*
2549 * Nobody will change the following 5 values in the VMCB so we can
2550 * safely return them on rdmsr. They will always be 0 until LBRV is
2551 * implemented.
2552 */
a2938c80 2553 case MSR_IA32_DEBUGCTLMSR:
609e36d3 2554 msr_info->data = svm->vmcb->save.dbgctl;
a2938c80
JR		 2555 break;
2556 case MSR_IA32_LASTBRANCHFROMIP:
609e36d3 2557 msr_info->data = svm->vmcb->save.br_from;
a2938c80
JR		 2558 break;
2559 case MSR_IA32_LASTBRANCHTOIP:
609e36d3 2560 msr_info->data = svm->vmcb->save.br_to;
a2938c80
JR		 2561 break;
2562 case MSR_IA32_LASTINTFROMIP:
609e36d3 2563 msr_info->data = svm->vmcb->save.last_excp_from;
a2938c80
JR		 2564 break;
2565 case MSR_IA32_LASTINTTOIP:
609e36d3 2566 msr_info->data = svm->vmcb->save.last_excp_to;
a2938c80 2567 break;
b286d5d8 2568 case MSR_VM_HSAVE_PA:
609e36d3 2569 msr_info->data = svm->nested.hsave_msr;
b286d5d8 2570 break;
eb6f302e 2571 case MSR_VM_CR:
609e36d3 2572 msr_info->data = svm->nested.vm_cr_msr;
eb6f302e 2573 break;
b2ac58f9
KA		 2574 case MSR_IA32_SPEC_CTRL:
2575 if (!msr_info->host_initiated &&
39485ed9 2576 !guest_has_spec_ctrl_msr(vcpu))
b2ac58f9
KA		 2577 return 1;
2578
2579 msr_info->data = svm->spec_ctrl;
2580 break;
bc226f07
TL		 2581 case MSR_AMD64_VIRT_SPEC_CTRL:
2582 if (!msr_info->host_initiated &&
2583 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2584 return 1;
2585
2586 msr_info->data = svm->virt_spec_ctrl;
2587 break;
ae8b7875
BP		 2588 case MSR_F15H_IC_CFG: {
2589
2590 int family, model;
2591
2592 family = guest_cpuid_family(vcpu);
2593 model = guest_cpuid_model(vcpu);
2594
2595 if (family < 0 || model < 0)
2596 return kvm_get_msr_common(vcpu, msr_info);
2597
2598 msr_info->data = 0;
2599
2600 if (family == 0x15 &&
2601 (model >= 0x2 && model < 0x20))
2602 msr_info->data = 0x1E;
2603 }
2604 break;
d1d93fa9
TL		 2605 case MSR_F10H_DECFG:
2606 msr_info->data = svm->msr_decfg;
2607 break;
6aa8b732 2608 default:
609e36d3 2609 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 2610 }
2611 return 0;
2612}
2613
f1c6366e
TL		 2614static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2615{
2616 struct vcpu_svm *svm = to_svm(vcpu);
2617 if (!sev_es_guest(svm->vcpu.kvm) || !err)
2618 return kvm_complete_insn_gp(&svm->vcpu, err);
2619
2620 ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2621 ghcb_set_sw_exit_info_2(svm->ghcb,
2622 X86_TRAP_GP |
2623 SVM_EVTINJ_TYPE_EXEPT |
2624 SVM_EVTINJ_VALID);
2625 return 1;
2626}
2627
851ba692 2628static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2629{
1edce0a9 2630 return kvm_emulate_rdmsr(&svm->vcpu);
6aa8b732
AK		 2631}
2632
4a810181
JR		 2633static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2634{
2635 struct vcpu_svm *svm = to_svm(vcpu);
2636 int svm_dis, chg_mask;
2637
2638 if (data & ~SVM_VM_CR_VALID_MASK)
2639 return 1;
2640
2641 chg_mask = SVM_VM_CR_VALID_MASK;
2642
2643 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2644 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2645
2646 svm->nested.vm_cr_msr &= ~chg_mask;
2647 svm->nested.vm_cr_msr |= (data & chg_mask);
2648
2649 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2650
2651 /* check for svm_disable while efer.svme is set */
2652 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2653 return 1;
2654
2655 return 0;
2656}
2657
8fe8ab46 2658static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
6aa8b732 2659{
a2fa3e9f
GH		 2660 struct vcpu_svm *svm = to_svm(vcpu);
2661
8fe8ab46
WA		 2662 u32 ecx = msr->index;
2663 u64 data = msr->data;
6aa8b732 2664 switch (ecx) {
15038e14
PB		 2665 case MSR_IA32_CR_PAT:
2666 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2667 return 1;
2668 vcpu->arch.pat = data;
2669 svm->vmcb->save.g_pat = data;
06e7852c 2670 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
15038e14 2671 break;
b2ac58f9
KA		 2672 case MSR_IA32_SPEC_CTRL:
2673 if (!msr->host_initiated &&
39485ed9 2674 !guest_has_spec_ctrl_msr(vcpu))
b2ac58f9
KA		 2675 return 1;
2676
841c2be0 2677 if (kvm_spec_ctrl_test_value(data))
b2ac58f9
KA		 2678 return 1;
2679
2680 svm->spec_ctrl = data;
b2ac58f9
KA		 2681 if (!data)
2682 break;
2683
2684 /*
2685 * For non-nested:
2686 * When it's written (to non-zero) for the first time, pass
2687 * it through.
2688 *
2689 * For nested:
2690 * The handling of the MSR bitmap for L2 guests is done in
2691 * nested_svm_vmrun_msrpm.
2692 * We update the L1 MSR bit as well since it will end up
2693 * touching the MSR anyway now.
2694 */
476c9bd8 2695 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
b2ac58f9 2696 break;
15d45071
AR		 2697 case MSR_IA32_PRED_CMD:
2698 if (!msr->host_initiated &&
39485ed9 2699 !guest_has_pred_cmd_msr(vcpu))
15d45071
AR		 2700 return 1;
2701
2702 if (data & ~PRED_CMD_IBPB)
2703 return 1;
39485ed9 2704 if (!boot_cpu_has(X86_FEATURE_IBPB))
6441fa61 2705 return 1;
15d45071
AR		 2706 if (!data)
2707 break;
2708
2709 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
476c9bd8 2710 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
15d45071 2711 break;
bc226f07
TL		 2712 case MSR_AMD64_VIRT_SPEC_CTRL:
2713 if (!msr->host_initiated &&
2714 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2715 return 1;
2716
2717 if (data & ~SPEC_CTRL_SSBD)
2718 return 1;
2719
2720 svm->virt_spec_ctrl = data;
2721 break;
8c06585d 2722 case MSR_STAR:
a2fa3e9f 2723 svm->vmcb->save.star = data;
6aa8b732 2724 break;
49b14f24 2725#ifdef CONFIG_X86_64
6aa8b732 2726 case MSR_LSTAR:
a2fa3e9f 2727 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2728 break;
2729 case MSR_CSTAR:
a2fa3e9f 2730 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2731 break;
2732 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2733 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2734 break;
2735 case MSR_SYSCALL_MASK:
a2fa3e9f 2736 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2737 break;
2738#endif
2739 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2740 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2741 break;
2742 case MSR_IA32_SYSENTER_EIP:
017cb99e 2743 svm->sysenter_eip = data;
a2fa3e9f 2744 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2745 break;
2746 case MSR_IA32_SYSENTER_ESP:
017cb99e 2747 svm->sysenter_esp = data;
a2fa3e9f 2748 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2749 break;
46896c73
PB		 2750 case MSR_TSC_AUX:
2751 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2752 return 1;
2753
2754 /*
2755 * This is rare, so we update the MSR here instead of using
2756 * direct_access_msrs. Doing that would require a rdmsr in
2757 * svm_vcpu_put.
2758 */
2759 svm->tsc_aux = data;
2760 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2761 break;
a2938c80 2762 case MSR_IA32_DEBUGCTLMSR:
2a6b20b8 2763 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
a737f256
CD		 2764 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2765 __func__, data);
24e09cbf
JR		 2766 break;
2767 }
2768 if (data & DEBUGCTL_RESERVED_BITS)
2769 return 1;
2770
2771 svm->vmcb->save.dbgctl = data;
06e7852c 2772 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
24e09cbf 2773 if (data & (1ULL<<0))
476c9bd8 2774 svm_enable_lbrv(vcpu);
24e09cbf 2775 else
476c9bd8 2776 svm_disable_lbrv(vcpu);
a2938c80 2777 break;
b286d5d8 2778 case MSR_VM_HSAVE_PA:
e6aa9abd 2779 svm->nested.hsave_msr = data;
62b9abaa 2780 break;
3c5d0a44 2781 case MSR_VM_CR:
4a810181 2782 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2783 case MSR_VM_IGNNE:
a737f256 2784 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3c5d0a44 2785 break;
d1d93fa9
TL		 2786 case MSR_F10H_DECFG: {
2787 struct kvm_msr_entry msr_entry;
2788
2789 msr_entry.index = msr->index;
2790 if (svm_get_msr_feature(&msr_entry))
2791 return 1;
2792
2793 /* Check the supported bits */
2794 if (data & ~msr_entry.data)
2795 return 1;
2796
2797 /* Don't allow the guest to change a bit, #GP */
2798 if (!msr->host_initiated && (data ^ msr_entry.data))
2799 return 1;
2800
2801 svm->msr_decfg = data;
2802 break;
2803 }
44a95dae
SS		 2804 case MSR_IA32_APICBASE:
2805 if (kvm_vcpu_apicv_active(vcpu))
2806 avic_update_vapic_bar(to_svm(vcpu), data);
df561f66 2807 fallthrough;
6aa8b732 2808 default:
8fe8ab46 2809 return kvm_set_msr_common(vcpu, msr);
6aa8b732
AK		 2810 }
2811 return 0;
2812}
2813
851ba692 2814static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2815{
1edce0a9 2816 return kvm_emulate_wrmsr(&svm->vcpu);
6aa8b732
AK		 2817}
2818
851ba692 2819static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2820{
e756fc62 2821 if (svm->vmcb->control.exit_info_1)
851ba692 2822 return wrmsr_interception(svm);
6aa8b732 2823 else
851ba692 2824 return rdmsr_interception(svm);
6aa8b732
AK		 2825}
2826
851ba692 2827static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2828{
3842d135 2829 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
f0b85051 2830 svm_clear_vintr(svm);
f3515dc3
SS		 2831
2832 /*
2833 * For AVIC, the only reason to end up here is ExtINTs.
2834 * In this case AVIC was temporarily disabled for
2835 * requesting the IRQ window and we have to re-enable it.
2836 */
2837 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2838
675acb75 2839 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2840 return 1;
2841}
2842
565d0998
ML		 2843static int pause_interception(struct vcpu_svm *svm)
2844{
de63ad4c 2845 struct kvm_vcpu *vcpu = &svm->vcpu;
f1c6366e
TL		 2846 bool in_kernel;
2847
2848 /*
2849 * CPL is not made available for an SEV-ES guest, therefore
2850 * vcpu->arch.preempted_in_kernel can never be true. Just
2851 * set in_kernel to false as well.
2852 */
2853 in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
de63ad4c 2854
830f01b0 2855 if (!kvm_pause_in_guest(vcpu->kvm))
8566ac8b
BM		 2856 grow_ple_window(vcpu);
2857
de63ad4c 2858 kvm_vcpu_on_spin(vcpu, in_kernel);
565d0998
ML		 2859 return 1;
2860}
2861
87c00572
GS		 2862static int nop_interception(struct vcpu_svm *svm)
2863{
b742c1e6 2864 return kvm_skip_emulated_instruction(&(svm->vcpu));
87c00572
GS		 2865}
2866
2867static int monitor_interception(struct vcpu_svm *svm)
2868{
2869 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2870 return nop_interception(svm);
2871}
2872
2873static int mwait_interception(struct vcpu_svm *svm)
2874{
2875 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2876 return nop_interception(svm);
2877}
2878
4407a797
BM		 2879static int invpcid_interception(struct vcpu_svm *svm)
2880{
2881 struct kvm_vcpu *vcpu = &svm->vcpu;
2882 unsigned long type;
2883 gva_t gva;
2884
2885 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2886 kvm_queue_exception(vcpu, UD_VECTOR);
2887 return 1;
2888 }
2889
2890 /*
2891 * For an INVPCID intercept:
2892 * EXITINFO1 provides the linear address of the memory operand.
2893 * EXITINFO2 provides the contents of the register operand.
2894 */
2895 type = svm->vmcb->control.exit_info_2;
2896 gva = svm->vmcb->control.exit_info_1;
2897
2898 if (type > 3) {
2899 kvm_inject_gp(vcpu, 0);
2900 return 1;
2901 }
2902
2903 return kvm_handle_invpcid(vcpu, type, gva);
2904}
2905
09941fbb 2906static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
7ff76d58
AP		 2907 [SVM_EXIT_READ_CR0] = cr_interception,
2908 [SVM_EXIT_READ_CR3] = cr_interception,
2909 [SVM_EXIT_READ_CR4] = cr_interception,
2910 [SVM_EXIT_READ_CR8] = cr_interception,
5e57518d 2911 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
628afd2a 2912 [SVM_EXIT_WRITE_CR0] = cr_interception,
7ff76d58
AP		 2913 [SVM_EXIT_WRITE_CR3] = cr_interception,
2914 [SVM_EXIT_WRITE_CR4] = cr_interception,
e0231715 2915 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
cae3797a
AP		 2916 [SVM_EXIT_READ_DR0] = dr_interception,
2917 [SVM_EXIT_READ_DR1] = dr_interception,
2918 [SVM_EXIT_READ_DR2] = dr_interception,
2919 [SVM_EXIT_READ_DR3] = dr_interception,
2920 [SVM_EXIT_READ_DR4] = dr_interception,
2921 [SVM_EXIT_READ_DR5] = dr_interception,
2922 [SVM_EXIT_READ_DR6] = dr_interception,
2923 [SVM_EXIT_READ_DR7] = dr_interception,
2924 [SVM_EXIT_WRITE_DR0] = dr_interception,
2925 [SVM_EXIT_WRITE_DR1] = dr_interception,
2926 [SVM_EXIT_WRITE_DR2] = dr_interception,
2927 [SVM_EXIT_WRITE_DR3] = dr_interception,
2928 [SVM_EXIT_WRITE_DR4] = dr_interception,
2929 [SVM_EXIT_WRITE_DR5] = dr_interception,
2930 [SVM_EXIT_WRITE_DR6] = dr_interception,
2931 [SVM_EXIT_WRITE_DR7] = dr_interception,
d0bfb940
JK		 2932 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2933 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2934 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715 2935 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
e0231715 2936 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
54a20552 2937 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
9718420e 2938 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
e0231715 2939 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2940 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2941 [SVM_EXIT_SMI] = nop_on_interception,
2942 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2943 [SVM_EXIT_VINTR] = interrupt_window_interception,
332b56e4 2944 [SVM_EXIT_RDPMC] = rdpmc_interception,
6aa8b732 2945 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2946 [SVM_EXIT_IRET] = iret_interception,
4bb05f30 2947 [SVM_EXIT_INVD] = invd_interception,
565d0998 2948 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2949 [SVM_EXIT_HLT] = halt_interception,
a7052897 2950 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2951 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2952 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2953 [SVM_EXIT_MSR] = msr_interception,
2954 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2955 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2956 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2957 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2958 [SVM_EXIT_VMLOAD] = vmload_interception,
2959 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2960 [SVM_EXIT_STGI] = stgi_interception,
2961 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2962 [SVM_EXIT_SKINIT] = skinit_interception,
dab429a7 2963 [SVM_EXIT_WBINVD] = wbinvd_interception,
87c00572
GS		 2964 [SVM_EXIT_MONITOR] = monitor_interception,
2965 [SVM_EXIT_MWAIT] = mwait_interception,
81dd35d4 2966 [SVM_EXIT_XSETBV] = xsetbv_interception,
0cb8410b 2967 [SVM_EXIT_RDPRU] = rdpru_interception,
4407a797 2968 [SVM_EXIT_INVPCID] = invpcid_interception,
d0006530 2969 [SVM_EXIT_NPF] = npf_interception,
7607b717 2970 [SVM_EXIT_RSM] = rsm_interception,
18f40c53
SS		 2971 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2972 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
6aa8b732
AK		 2973};
2974
ae8cc059 2975static void dump_vmcb(struct kvm_vcpu *vcpu)
3f10c846
JR		 2976{
2977 struct vcpu_svm *svm = to_svm(vcpu);
2978 struct vmcb_control_area *control = &svm->vmcb->control;
2979 struct vmcb_save_area *save = &svm->vmcb->save;
2980
6f2f8453
PB		 2981 if (!dump_invalid_vmcb) {
2982 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2983 return;
2984 }
2985
3f10c846 2986 pr_err("VMCB Control Area:\n");
03bfeeb9
BM		 2987 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
2988 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
30abaa88
BM		 2989 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
2990 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
9780d51d 2991 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
c62e2e94
BM		 2992 pr_err("%-20s%08x %08x\n", "intercepts:",
2993 control->intercepts[INTERCEPT_WORD3],
2994 control->intercepts[INTERCEPT_WORD4]);
ae8cc059 2995 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
1d8fb44a
BM		 2996 pr_err("%-20s%d\n", "pause filter threshold:",
2997 control->pause_filter_thresh);
ae8cc059
JP		 2998 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2999 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3000 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3001 pr_err("%-20s%d\n", "asid:", control->asid);
3002 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3003 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3004 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3005 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3006 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3007 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3008 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3009 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3010 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3011 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3012 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
44a95dae 3013 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
ae8cc059
JP		 3014 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3015 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
0dc92119 3016 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
ae8cc059 3017 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
44a95dae
SS		 3018 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3019 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3020 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3f10c846 3021 pr_err("VMCB State Save Area:\n");
ae8cc059
JP		 3022 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3023 "es:",
3024 save->es.selector, save->es.attrib,
3025 save->es.limit, save->es.base);
3026 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3027 "cs:",
3028 save->cs.selector, save->cs.attrib,
3029 save->cs.limit, save->cs.base);
3030 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3031 "ss:",
3032 save->ss.selector, save->ss.attrib,
3033 save->ss.limit, save->ss.base);
3034 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3035 "ds:",
3036 save->ds.selector, save->ds.attrib,
3037 save->ds.limit, save->ds.base);
3038 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3039 "fs:",
3040 save->fs.selector, save->fs.attrib,
3041 save->fs.limit, save->fs.base);
3042 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3043 "gs:",
3044 save->gs.selector, save->gs.attrib,
3045 save->gs.limit, save->gs.base);
3046 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3047 "gdtr:",
3048 save->gdtr.selector, save->gdtr.attrib,
3049 save->gdtr.limit, save->gdtr.base);
3050 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3051 "ldtr:",
3052 save->ldtr.selector, save->ldtr.attrib,
3053 save->ldtr.limit, save->ldtr.base);
3054 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3055 "idtr:",
3056 save->idtr.selector, save->idtr.attrib,
3057 save->idtr.limit, save->idtr.base);
3058 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3059 "tr:",
3060 save->tr.selector, save->tr.attrib,
3061 save->tr.limit, save->tr.base);
3f10c846
JR		 3062 pr_err("cpl: %d efer: %016llx\n",
3063 save->cpl, save->efer);
ae8cc059
JP		 3064 pr_err("%-15s %016llx %-13s %016llx\n",
3065 "cr0:", save->cr0, "cr2:", save->cr2);
3066 pr_err("%-15s %016llx %-13s %016llx\n",
3067 "cr3:", save->cr3, "cr4:", save->cr4);
3068 pr_err("%-15s %016llx %-13s %016llx\n",
3069 "dr6:", save->dr6, "dr7:", save->dr7);
3070 pr_err("%-15s %016llx %-13s %016llx\n",
3071 "rip:", save->rip, "rflags:", save->rflags);
3072 pr_err("%-15s %016llx %-13s %016llx\n",
3073 "rsp:", save->rsp, "rax:", save->rax);
3074 pr_err("%-15s %016llx %-13s %016llx\n",
3075 "star:", save->star, "lstar:", save->lstar);
3076 pr_err("%-15s %016llx %-13s %016llx\n",
3077 "cstar:", save->cstar, "sfmask:", save->sfmask);
3078 pr_err("%-15s %016llx %-13s %016llx\n",
3079 "kernel_gs_base:", save->kernel_gs_base,
3080 "sysenter_cs:", save->sysenter_cs);
3081 pr_err("%-15s %016llx %-13s %016llx\n",
3082 "sysenter_esp:", save->sysenter_esp,
3083 "sysenter_eip:", save->sysenter_eip);
3084 pr_err("%-15s %016llx %-13s %016llx\n",
3085 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3086 pr_err("%-15s %016llx %-13s %016llx\n",
3087 "br_from:", save->br_from, "br_to:", save->br_to);
3088 pr_err("%-15s %016llx %-13s %016llx\n",
3089 "excp_from:", save->last_excp_from,
3090 "excp_to:", save->last_excp_to);
3f10c846
JR		 3091}
3092
235ba74f
SC		 3093static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3094 u32 *intr_info, u32 *error_code)
586f9607
AK		 3095{
3096 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3097
3098 *info1 = control->exit_info_1;
3099 *info2 = control->exit_info_2;
235ba74f
SC		 3100 *intr_info = control->exit_int_info;
3101 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3102 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3103 *error_code = control->exit_int_info_err;
3104 else
3105 *error_code = 0;
586f9607
AK		 3106}
3107
404d5d7b 3108static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
6aa8b732 3109{
04d2cc77 3110 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 3111 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 3112 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 3113
8b89fe1f
PB		 3114 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3115
f1c6366e
TL		 3116 /* SEV-ES guests must use the CR write traps to track CR registers. */
3117 if (!sev_es_guest(vcpu->kvm)) {
3118 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3119 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3120 if (npt_enabled)
3121 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3122 }
af9ca2d7 3123
2030753d 3124 if (is_guest_mode(vcpu)) {
410e4d57
JR		 3125 int vmexit;
3126
cc167bd7 3127 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
d8cabddf 3128
410e4d57
JR		 3129 vmexit = nested_svm_exit_special(svm);
3130
3131 if (vmexit == NESTED_EXIT_CONTINUE)
3132 vmexit = nested_svm_exit_handled(svm);
3133
3134 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 3135 return 1;
cf74a78b
AG		 3136 }
3137
04d2cc77
AK		 3138 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3139 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3140 kvm_run->fail_entry.hardware_entry_failure_reason
3141 = svm->vmcb->control.exit_code;
8a14fe4f 3142 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3f10c846 3143 dump_vmcb(vcpu);
04d2cc77
AK		 3144 return 0;
3145 }
3146
a2fa3e9f 3147 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 3148 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
55c5e464
JR		 3149 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3150 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
6614c7d0 3151 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
6aa8b732 3152 "exit_code 0x%x\n",
b8688d51 3153 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 3154 exit_code);
3155
404d5d7b 3156 if (exit_fastpath != EXIT_FASTPATH_NONE)
1e9e2622 3157 return 1;
404d5d7b
WL		 3158
3159 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 3160 || !svm_exit_handlers[exit_code]) {
7396d337
LA		 3161 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
3162 dump_vmcb(vcpu);
3163 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3164 vcpu->run->internal.suberror =
3165 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
1aa561b1 3166 vcpu->run->internal.ndata = 2;
7396d337 3167 vcpu->run->internal.data[0] = exit_code;
8a14fe4f 3168 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
7396d337 3169 return 0;
6aa8b732
AK		 3170 }
3171
3dcb2a3f
AA		 3172#ifdef CONFIG_RETPOLINE
3173 if (exit_code == SVM_EXIT_MSR)
3174 return msr_interception(svm);
3175 else if (exit_code == SVM_EXIT_VINTR)
3176 return interrupt_window_interception(svm);
3177 else if (exit_code == SVM_EXIT_INTR)
3178 return intr_interception(svm);
3179 else if (exit_code == SVM_EXIT_HLT)
3180 return halt_interception(svm);
3181 else if (exit_code == SVM_EXIT_NPF)
3182 return npf_interception(svm);
3183#endif
851ba692 3184 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 3185}
3186
3187static void reload_tss(struct kvm_vcpu *vcpu)
3188{
73cd6e5f 3189 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
6aa8b732 3190
0fe1e009 3191 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 3192 load_TR_desc();
3193}
3194
e756fc62 3195static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732 3196{
73cd6e5f 3197 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
6aa8b732 3198
70cd94e6 3199 if (sev_guest(svm->vcpu.kvm))
73cd6e5f 3200 return pre_sev_run(svm, svm->vcpu.cpu);
70cd94e6 3201
4b656b12 3202 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 3203 if (svm->asid_generation != sd->asid_generation)
3204 new_asid(svm, sd);
6aa8b732
AK		 3205}
3206
95ba8273
GN		 3207static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3208{
3209 struct vcpu_svm *svm = to_svm(vcpu);
3210
3211 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3212 vcpu->arch.hflags |= HF_NMI_MASK;
a284ba56 3213 svm_set_intercept(svm, INTERCEPT_IRET);
95ba8273
GN		 3214 ++vcpu->stat.nmi_injections;
3215}
6aa8b732 3216
66fd3f7f 3217static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 3218{
3219 struct vcpu_svm *svm = to_svm(vcpu);
3220
2af9194d 3221 BUG_ON(!(gif_set(svm)));
cf74a78b 3222
9fb2d2b4
GN		 3223 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3224 ++vcpu->stat.irq_injections;
3225
219b65dc
AG		 3226 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3227 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 3228}
3229
95ba8273 3230static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 3231{
3232 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 3233
f1c6366e
TL		 3234 /*
3235 * SEV-ES guests must always keep the CR intercepts cleared. CR
3236 * tracking is done using the CR write traps.
3237 */
3238 if (sev_es_guest(vcpu->kvm))
3239 return;
3240
01c3b2b5 3241 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3242 return;
3243
830bd71f 3244 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
596f3142 3245
95ba8273 3246 if (irr == -1)
aaacfc9a
JR		 3247 return;
3248
95ba8273 3249 if (tpr >= irr)
830bd71f 3250 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
95ba8273 3251}
aaacfc9a 3252
cae96af1 3253bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
95ba8273
GN		 3254{
3255 struct vcpu_svm *svm = to_svm(vcpu);
3256 struct vmcb *vmcb = svm->vmcb;
88c604b6 3257 bool ret;
9c3d370a 3258
cae96af1 3259 if (!gif_set(svm))
bbdad0b5
PB		 3260 return true;
3261
cae96af1
PB		 3262 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3263 return false;
3264
3265 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3266 (svm->vcpu.arch.hflags & HF_NMI_MASK);
924584cc
JR		 3267
3268 return ret;
aaacfc9a
JR		 3269}
3270
c9d40913 3271static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3272{
3273 struct vcpu_svm *svm = to_svm(vcpu);
3274 if (svm->nested.nested_run_pending)
c9d40913 3275 return -EBUSY;
cae96af1 3276
c300ab9f
PB		 3277 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3278 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
c9d40913 3279 return -EBUSY;
c300ab9f
PB		 3280
3281 return !svm_nmi_blocked(vcpu);
cae96af1
PB		 3282}
3283
3cfc3092
JK		 3284static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3285{
3286 struct vcpu_svm *svm = to_svm(vcpu);
3287
3288 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3289}
3290
3291static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3292{
3293 struct vcpu_svm *svm = to_svm(vcpu);
3294
3295 if (masked) {
3296 svm->vcpu.arch.hflags |= HF_NMI_MASK;
a284ba56 3297 svm_set_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3298 } else {
3299 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
a284ba56 3300 svm_clr_intercept(svm, INTERCEPT_IRET);
3cfc3092
JK		 3301 }
3302}
3303
cae96af1 3304bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
78646121
GN		 3305{
3306 struct vcpu_svm *svm = to_svm(vcpu);
3307 struct vmcb *vmcb = svm->vmcb;
7fcdb510 3308
fc6f7c03 3309 if (!gif_set(svm))
cae96af1 3310 return true;
7fcdb510 3311
f1c6366e
TL		 3312 if (sev_es_guest(svm->vcpu.kvm)) {
3313 /*
3314 * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3315 * bit to determine the state of the IF flag.
3316 */
3317 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3318 return true;
3319 } else if (is_guest_mode(vcpu)) {
fc6f7c03 3320 /* As long as interrupts are being delivered... */
e9fd761a 3321 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
08245e6d 3322 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
fc6f7c03
PB		 3323 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3324 return true;
3325
3326 /* ... vmexits aren't blocked by the interrupt shadow */
3327 if (nested_exit_on_intr(svm))
3328 return false;
3329 } else {
3330 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3331 return true;
3332 }
3333
3334 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
cae96af1
PB		 3335}
3336
c9d40913 3337static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 3338{
3339 struct vcpu_svm *svm = to_svm(vcpu);
3340 if (svm->nested.nested_run_pending)
c9d40913 3341 return -EBUSY;
cae96af1 3342
c300ab9f
PB		 3343 /*
3344 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3345 * e.g. if the IRQ arrived asynchronously after checking nested events.
3346 */
3347 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
c9d40913 3348 return -EBUSY;
c300ab9f
PB		 3349
3350 return !svm_interrupt_blocked(vcpu);
78646121
GN		 3351}
3352
c9a7953f 3353static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3354{
219b65dc 3355 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3356
e0231715
JR		 3357 /*
3358 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3359 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3360 * get that intercept, this function will be called again though and
640bd6e5
JN		 3361 * we'll get the vintr intercept. However, if the vGIF feature is
3362 * enabled, the STGI interception will not occur. Enable the irq
3363 * window under the assumption that the hardware will set the GIF.
e0231715 3364 */
b518ba9f 3365 if (vgif_enabled(svm) || gif_set(svm)) {
f3515dc3
SS		 3366 /*
3367 * IRQ window is not needed when AVIC is enabled,
3368 * unless we have pending ExtINT since it cannot be injected
3369 * via AVIC. In such case, we need to temporarily disable AVIC,
3370 * and fallback to injecting IRQ via V_IRQ.
3371 */
3372 svm_toggle_avic_for_irq_window(vcpu, false);
219b65dc 3373 svm_set_vintr(svm);
219b65dc 3374 }
85f455f7
ED		 3375}
3376
c9a7953f 3377static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3378{
04d2cc77 3379 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3380
44c11430
GN		 3381 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3382 == HF_NMI_MASK)
c9a7953f 3383 return; /* IRET will cause a vm exit */
44c11430 3384
640bd6e5
JN		 3385 if (!gif_set(svm)) {
3386 if (vgif_enabled(svm))
a284ba56 3387 svm_set_intercept(svm, INTERCEPT_STGI);
1a5e1852 3388 return; /* STGI will cause a vm exit */
640bd6e5 3389 }
1a5e1852 3390
e0231715
JR		 3391 /*
3392 * Something prevents NMI from been injected. Single step over possible
3393 * problem (IRET or exception injection or interrupt shadow)
3394 */
ab2f4d73 3395 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
6be7d306 3396 svm->nmi_singlestep = true;
44c11430 3397 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
c1150d8c
DL		 3398}
3399
cbc94022
IE		 3400static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3401{
3402 return 0;
3403}
3404
2ac52ab8
SC		 3405static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3406{
3407 return 0;
3408}
3409
f55ac304 3410void svm_flush_tlb(struct kvm_vcpu *vcpu)
d9e368d6 3411{
38e5e92f
JR		 3412 struct vcpu_svm *svm = to_svm(vcpu);
3413
4a41e43c
SC		 3414 /*
3415 * Flush only the current ASID even if the TLB flush was invoked via
3416 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3417 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3418 * unconditionally does a TLB flush on both nested VM-Enter and nested
3419 * VM-Exit (via kvm_mmu_reset_context()).
3420 */
38e5e92f
JR		 3421 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3422 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3423 else
3424 svm->asid_generation--;
d9e368d6
AK		 3425}
3426
faff8758
JS		 3427static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3428{
3429 struct vcpu_svm *svm = to_svm(vcpu);
3430
3431 invlpga(gva, svm->vmcb->control.asid);
3432}
3433
04d2cc77
AK		 3434static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3435{
3436}
3437
d7bf8221
JR		 3438static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3439{
3440 struct vcpu_svm *svm = to_svm(vcpu);
3441
01c3b2b5 3442 if (nested_svm_virtualize_tpr(vcpu))
88ab24ad
JR		 3443 return;
3444
830bd71f 3445 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
d7bf8221 3446 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3447 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3448 }
3449}
3450
649d6864
JR		 3451static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3452{
3453 struct vcpu_svm *svm = to_svm(vcpu);
3454 u64 cr8;
3455
01c3b2b5 3456 if (nested_svm_virtualize_tpr(vcpu) ||
3bbf3565 3457 kvm_vcpu_apicv_active(vcpu))
88ab24ad
JR		 3458 return;
3459
649d6864
JR		 3460 cr8 = kvm_get_cr8(vcpu);
3461 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3462 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3463}
3464
9222be18
GN		 3465static void svm_complete_interrupts(struct vcpu_svm *svm)
3466{
3467 u8 vector;
3468 int type;
3469 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3470 unsigned int3_injected = svm->int3_injected;
3471
3472 svm->int3_injected = 0;
9222be18 3473
bd3d1ec3
AK		 3474 /*
3475 * If we've made progress since setting HF_IRET_MASK, we've
3476 * executed an IRET and can allow NMI injection.
3477 */
3478 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3479 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
44c11430 3480 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3842d135
AK		 3481 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3482 }
44c11430 3483
9222be18
GN		 3484 svm->vcpu.arch.nmi_injected = false;
3485 kvm_clear_exception_queue(&svm->vcpu);
3486 kvm_clear_interrupt_queue(&svm->vcpu);
3487
3488 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3489 return;
3490
3842d135
AK		 3491 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3492
9222be18
GN		 3493 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3494 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3495
3496 switch (type) {
3497 case SVM_EXITINTINFO_TYPE_NMI:
3498 svm->vcpu.arch.nmi_injected = true;
3499 break;
3500 case SVM_EXITINTINFO_TYPE_EXEPT:
f1c6366e
TL		 3501 /*
3502 * Never re-inject a #VC exception.
3503 */
3504 if (vector == X86_TRAP_VC)
3505 break;
3506
66b7138f
JK		 3507 /*
3508 * In case of software exceptions, do not reinject the vector,
3509 * but re-execute the instruction instead. Rewind RIP first
3510 * if we emulated INT3 before.
3511 */
3512 if (kvm_exception_is_soft(vector)) {
3513 if (vector == BP_VECTOR && int3_injected &&
3514 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3515 kvm_rip_write(&svm->vcpu,
3516 kvm_rip_read(&svm->vcpu) -
3517 int3_injected);
9222be18 3518 break;
66b7138f 3519 }
9222be18
GN		 3520 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3521 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3522 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3523
3524 } else
ce7ddec4 3525 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3526 break;
3527 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3528 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3529 break;
3530 default:
3531 break;
3532 }
3533}
3534
b463a6f7
AK		 3535static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3536{
3537 struct vcpu_svm *svm = to_svm(vcpu);
3538 struct vmcb_control_area *control = &svm->vmcb->control;
3539
3540 control->exit_int_info = control->event_inj;
3541 control->exit_int_info_err = control->event_inj_err;
3542 control->event_inj = 0;
3543 svm_complete_interrupts(svm);
3544}
3545
404d5d7b 3546static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
a9ab13ff 3547{
4e810adb 3548 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
a9ab13ff
WL		 3549 to_svm(vcpu)->vmcb->control.exit_info_1)
3550 return handle_fastpath_set_msr_irqoff(vcpu);
3551
3552 return EXIT_FASTPATH_NONE;
3553}
3554
56a87e5d 3555void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
199cd1d7 3556
135961e0
TG		 3557static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3558 struct vcpu_svm *svm)
3559{
3560 /*
3561 * VMENTER enables interrupts (host state), but the kernel state is
3562 * interrupts disabled when this is invoked. Also tell RCU about
3563 * it. This is the same logic as for exit_to_user_mode().
3564 *
3565 * This ensures that e.g. latency analysis on the host observes
3566 * guest mode as interrupt enabled.
3567 *
3568 * guest_enter_irqoff() informs context tracking about the
3569 * transition to guest mode and if enabled adjusts RCU state
3570 * accordingly.
3571 */
3572 instrumentation_begin();
3573 trace_hardirqs_on_prepare();
3574 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3575 instrumentation_end();
3576
3577 guest_enter_irqoff();
3578 lockdep_hardirqs_on(CALLER_ADDR0);
3579
3580 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3581
3582#ifdef CONFIG_X86_64
c3f08ed1 3583 native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
135961e0
TG		 3584#else
3585 loadsegment(fs, svm->host.fs);
3586#ifndef CONFIG_X86_32_LAZY_GS
3587 loadsegment(gs, svm->host.gs);
3588#endif
3589#endif
3590
3591 /*
3592 * VMEXIT disables interrupts (host state), but tracing and lockdep
3593 * have them in state 'on' as recorded before entering guest mode.
3594 * Same as enter_from_user_mode().
3595 *
3596 * guest_exit_irqoff() restores host context and reinstates RCU if
3597 * enabled and required.
3598 *
3599 * This needs to be done before the below as native_read_msr()
3600 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3601 * into world and some more.
3602 */
3603 lockdep_hardirqs_off(CALLER_ADDR0);
3604 guest_exit_irqoff();
3605
3606 instrumentation_begin();
3607 trace_hardirqs_off_finish();
3608 instrumentation_end();
3609}
3610
b95273f1 3611static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3612{
a2fa3e9f 3613 struct vcpu_svm *svm = to_svm(vcpu);
d9e368d6 3614
2041a06a
JR		 3615 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3616 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3617 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3618
a12713c2
LP		 3619 /*
3620 * Disable singlestep if we're injecting an interrupt/exception.
3621 * We don't want our modified rflags to be pushed on the stack where
3622 * we might not be able to easily reset them if we disabled NMI
3623 * singlestep later.
3624 */
3625 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3626 /*
3627 * Event injection happens before external interrupts cause a
3628 * vmexit and interrupts are disabled here, so smp_send_reschedule
3629 * is enough to force an immediate vmexit.
3630 */
3631 disable_nmi_singlestep(svm);
3632 smp_send_reschedule(vcpu->cpu);
3633 }
3634
e756fc62 3635 pre_svm_run(svm);
6aa8b732 3636
649d6864
JR		 3637 sync_lapic_to_cr8(vcpu);
3638
7e8e6eed
CA		 3639 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3640 svm->vmcb->control.asid = svm->asid;
3641 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3642 }
cda0ffdd 3643 svm->vmcb->save.cr2 = vcpu->arch.cr2;
6aa8b732 3644
d67668e9
PB		 3645 /*
3646 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3647 * of a #DB.
3648 */
3649 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3650 svm_set_dr6(svm, vcpu->arch.dr6);
3651 else
3652 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3653
04d2cc77 3654 clgi();
139a12cf 3655 kvm_load_guest_xsave_state(vcpu);
04d2cc77 3656
010fd37f 3657 kvm_wait_lapic_expire(vcpu);
b6c4bc65 3658
b2ac58f9
KA		 3659 /*
3660 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3661 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3662 * is no need to worry about the conditional branch over the wrmsr
3663 * being speculatively taken.
3664 */
ccbcd267 3665 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
b2ac58f9 3666
135961e0 3667 svm_vcpu_enter_exit(vcpu, svm);
15e6c22f 3668
b2ac58f9
KA		 3669 /*
3670 * We do not use IBRS in the kernel. If this vCPU has used the
3671 * SPEC_CTRL MSR it may have left it on; save the value and
3672 * turn it off. This is much more efficient than blindly adding
3673 * it to the atomic save/restore list. Especially as the former
3674 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3675 *
3676 * For non-nested case:
3677 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3678 * save it.
3679 *
3680 * For nested case:
3681 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3682 * save it.
3683 */
946fbbc1 3684 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
ecb586bd 3685 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b2ac58f9 3686
6aa8b732
AK		 3687 reload_tss(vcpu);
3688
024d83ca
TG		 3689 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3690
13c34e07
AK		 3691 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3692 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3693 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3694 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3695
3781c01c 3696 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3697 kvm_before_interrupt(&svm->vcpu);
3781c01c 3698
139a12cf 3699 kvm_load_host_xsave_state(vcpu);
3781c01c
JR		 3700 stgi();
3701
3702 /* Any pending NMI will happen here */
3703
3704 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
dd60d217 3705 kvm_after_interrupt(&svm->vcpu);
3781c01c 3706
d7bf8221
JR		 3707 sync_cr8_to_lapic(vcpu);
3708
a2fa3e9f 3709 svm->next_rip = 0;
2d8a42be
PB		 3710 if (is_guest_mode(&svm->vcpu)) {
3711 sync_nested_vmcb_control(svm);
3712 svm->nested.nested_run_pending = 0;
3713 }
9222be18 3714
38e5e92f 3715 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
e42c6828 3716 vmcb_mark_all_clean(svm->vmcb);
38e5e92f 3717
631bc487
GN		 3718 /* if exit due to PF check for async PF */
3719 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
68fd66f1
VK		 3720 svm->vcpu.arch.apf.host_apf_flags =
3721 kvm_read_and_reset_apf_flags();
631bc487 3722
6de4f3ad
AK		 3723 if (npt_enabled) {
3724 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3725 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3726 }
fe5913e4
JR		 3727
3728 /*
3729 * We need to handle MC intercepts here before the vcpu has a chance to
3730 * change the physical cpu
3731 */
3732 if (unlikely(svm->vmcb->control.exit_code ==
3733 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3734 svm_handle_mce(svm);
8d28fec4 3735
e42c6828 3736 svm_complete_interrupts(svm);
4e810adb
WL		 3737
3738 if (is_guest_mode(vcpu))
3739 return EXIT_FASTPATH_NONE;
3740
3741 return svm_exit_handlers_fastpath(vcpu);
6aa8b732
AK		 3742}
3743
2a40b900
SC		 3744static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3745 int root_level)
6aa8b732 3746{
a2fa3e9f 3747 struct vcpu_svm *svm = to_svm(vcpu);
689f3bf2 3748 unsigned long cr3;
a2fa3e9f 3749
689f3bf2
PB		 3750 cr3 = __sme_set(root);
3751 if (npt_enabled) {
3752 svm->vmcb->control.nested_cr3 = cr3;
06e7852c 3753 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
1c97f0a0 3754
689f3bf2 3755 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
978ce583
PB		 3756 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3757 return;
3758 cr3 = vcpu->arch.cr3;
689f3bf2 3759 }
1c97f0a0 3760
978ce583 3761 svm->vmcb->save.cr3 = cr3;
06e7852c 3762 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1c97f0a0
JR		 3763}
3764
6aa8b732
AK		 3765static int is_disabled(void)
3766{
6031a61c
JR		 3767 u64 vm_cr;
3768
3769 rdmsrl(MSR_VM_CR, vm_cr);
3770 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3771 return 1;
3772
6aa8b732
AK		 3773 return 0;
3774}
3775
102d8325
IM		 3776static void
3777svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3778{
3779 /*
3780 * Patch in the VMMCALL instruction:
3781 */
3782 hypercall[0] = 0x0f;
3783 hypercall[1] = 0x01;
3784 hypercall[2] = 0xd9;
102d8325
IM		 3785}
3786
f257d6dc 3787static int __init svm_check_processor_compat(void)
002c7f7c 3788{
f257d6dc 3789 return 0;
002c7f7c
YS		 3790}
3791
774ead3a
AK		 3792static bool svm_cpu_has_accelerated_tpr(void)
3793{
3794 return false;
3795}
3796
cb97c2d6 3797static bool svm_has_emulated_msr(u32 index)
6d396b55 3798{
e87555e5
VK		 3799 switch (index) {
3800 case MSR_IA32_MCG_EXT_CTL:
95c5c7c7 3801 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
e87555e5
VK		 3802 return false;
3803 default:
3804 break;
3805 }
3806
6d396b55
PB		 3807 return true;
3808}
3809
fc07e76a
PB		 3810static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3811{
3812 return 0;
3813}
3814
7c1b761b 3815static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
0e851880 3816{
6092d3d3 3817 struct vcpu_svm *svm = to_svm(vcpu);
96308b06 3818 struct kvm_cpuid_entry2 *best;
6092d3d3 3819
7204160e 3820 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
96be4e06 3821 boot_cpu_has(X86_FEATURE_XSAVE) &&
7204160e
AL		 3822 boot_cpu_has(X86_FEATURE_XSAVES);
3823
6092d3d3 3824 /* Update nrips enabled cache */
4eb87460
SC		 3825 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3826 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
46781eae 3827
4407a797
BM		 3828 /* Check again if INVPCID interception if required */
3829 svm_check_invpcid(svm);
3830
96308b06
BM		 3831 /* For sev guests, the memory encryption bit is not reserved in CR3. */
3832 if (sev_guest(vcpu->kvm)) {
3833 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3834 if (best)
3835 vcpu->arch.cr3_lm_rsvd_bits &= ~(1UL << (best->ebx & 0x3f));
3836 }
3837
46781eae
SS		 3838 if (!kvm_vcpu_apicv_active(vcpu))
3839 return;
3840
cc7f5577
OU		 3841 /*
3842 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3843 * is exposed to the guest, disable AVIC.
3844 */
3845 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3846 kvm_request_apicv_update(vcpu->kvm, false,
3847 APICV_INHIBIT_REASON_X2APIC);
9a0bf054
SS		 3848
3849 /*
3850 * Currently, AVIC does not work with nested virtualization.
3851 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3852 */
3853 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3854 kvm_request_apicv_update(vcpu->kvm, false,
3855 APICV_INHIBIT_REASON_NESTED);
0e851880
SY		 3856}
3857
f5f48ee1
SY		 3858static bool svm_has_wbinvd_exit(void)
3859{
3860 return true;
3861}
3862
8061252e 3863#define PRE_EX(exit) { .exit_code = (exit), \
40e19b51 3864 .stage = X86_ICPT_PRE_EXCEPT, }
cfec82cb 3865#define POST_EX(exit) { .exit_code = (exit), \
40e19b51 3866 .stage = X86_ICPT_POST_EXCEPT, }
d7eb8203 3867#define POST_MEM(exit) { .exit_code = (exit), \
40e19b51 3868 .stage = X86_ICPT_POST_MEMACCESS, }
cfec82cb 3869
09941fbb 3870static const struct __x86_intercept {
cfec82cb
JR		 3871 u32 exit_code;
3872 enum x86_intercept_stage stage;
cfec82cb
JR		 3873} x86_intercept_map[] = {
3874 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3875 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3876 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3877 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3878 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3b88e41a
JR		 3879 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3880 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
dee6bb70
JR		 3881 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3882 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3883 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3884 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3885 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3886 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3887 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3888 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
01de8b09
JR		 3889 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3890 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3891 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3892 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3893 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3894 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3895 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3896 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
d7eb8203
JR		 3897 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3898 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3899 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
8061252e
JR		 3900 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3901 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3902 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3903 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3904 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3905 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3906 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3907 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3908 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
bf608f88
JR		 3909 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3910 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3911 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3912 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3913 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3914 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3915 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
f6511935
JR		 3916 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3917 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3918 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3919 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
02d4160f 3920 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
cfec82cb
JR		 3921};
3922
8061252e 3923#undef PRE_EX
cfec82cb 3924#undef POST_EX
d7eb8203 3925#undef POST_MEM
cfec82cb 3926
8a76d7f2
JR		 3927static int svm_check_intercept(struct kvm_vcpu *vcpu,
3928 struct x86_instruction_info *info,
21f1b8f2
SC		 3929 enum x86_intercept_stage stage,
3930 struct x86_exception *exception)
8a76d7f2 3931{
cfec82cb
JR		 3932 struct vcpu_svm *svm = to_svm(vcpu);
3933 int vmexit, ret = X86EMUL_CONTINUE;
3934 struct __x86_intercept icpt_info;
3935 struct vmcb *vmcb = svm->vmcb;
3936
3937 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3938 goto out;
3939
3940 icpt_info = x86_intercept_map[info->intercept];
3941
40e19b51 3942 if (stage != icpt_info.stage)
cfec82cb
JR		 3943 goto out;
3944
3945 switch (icpt_info.exit_code) {
3946 case SVM_EXIT_READ_CR0:
3947 if (info->intercept == x86_intercept_cr_read)
3948 icpt_info.exit_code += info->modrm_reg;
3949 break;
3950 case SVM_EXIT_WRITE_CR0: {
3951 unsigned long cr0, val;
cfec82cb
JR		 3952
3953 if (info->intercept == x86_intercept_cr_write)
3954 icpt_info.exit_code += info->modrm_reg;
3955
62baf44c
JK		 3956 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3957 info->intercept == x86_intercept_clts)
cfec82cb
JR		 3958 break;
3959
c62e2e94
BM		 3960 if (!(vmcb_is_intercept(&svm->nested.ctl,
3961 INTERCEPT_SELECTIVE_CR0)))
cfec82cb
JR		 3962 break;
3963
3964 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3965 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3966
3967 if (info->intercept == x86_intercept_lmsw) {
3968 cr0 &= 0xfUL;
3969 val &= 0xfUL;
3970 /* lmsw can't clear PE - catch this here */
3971 if (cr0 & X86_CR0_PE)
3972 val |= X86_CR0_PE;
3973 }
3974
3975 if (cr0 ^ val)
3976 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3977
3978 break;
3979 }
3b88e41a
JR		 3980 case SVM_EXIT_READ_DR0:
3981 case SVM_EXIT_WRITE_DR0:
3982 icpt_info.exit_code += info->modrm_reg;
3983 break;
8061252e
JR		 3984 case SVM_EXIT_MSR:
3985 if (info->intercept == x86_intercept_wrmsr)
3986 vmcb->control.exit_info_1 = 1;
3987 else
3988 vmcb->control.exit_info_1 = 0;
3989 break;
bf608f88
JR		 3990 case SVM_EXIT_PAUSE:
3991 /*
3992 * We get this for NOP only, but pause
3993 * is rep not, check this here
3994 */
3995 if (info->rep_prefix != REPE_PREFIX)
3996 goto out;
49a8afca 3997 break;
f6511935
JR		 3998 case SVM_EXIT_IOIO: {
3999 u64 exit_info;
4000 u32 bytes;
4001
f6511935
JR		 4002 if (info->intercept == x86_intercept_in ||
4003 info->intercept == x86_intercept_ins) {
6cbc5f5a
JK		 4004 exit_info = ((info->src_val & 0xffff) << 16) |
4005 SVM_IOIO_TYPE_MASK;
f6511935 4006 bytes = info->dst_bytes;
6493f157 4007 } else {
6cbc5f5a 4008 exit_info = (info->dst_val & 0xffff) << 16;
6493f157 4009 bytes = info->src_bytes;
f6511935
JR		 4010 }
4011
4012 if (info->intercept == x86_intercept_outs ||
4013 info->intercept == x86_intercept_ins)
4014 exit_info |= SVM_IOIO_STR_MASK;
4015
4016 if (info->rep_prefix)
4017 exit_info |= SVM_IOIO_REP_MASK;
4018
4019 bytes = min(bytes, 4u);
4020
4021 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4022
4023 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4024
4025 vmcb->control.exit_info_1 = exit_info;
4026 vmcb->control.exit_info_2 = info->next_rip;
4027
4028 break;
4029 }
cfec82cb
JR		 4030 default:
4031 break;
4032 }
4033
f104765b
BD		 4034 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4035 if (static_cpu_has(X86_FEATURE_NRIPS))
4036 vmcb->control.next_rip = info->next_rip;
cfec82cb
JR		 4037 vmcb->control.exit_code = icpt_info.exit_code;
4038 vmexit = nested_svm_exit_handled(svm);
4039
4040 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4041 : X86EMUL_CONTINUE;
4042
4043out:
4044 return ret;
8a76d7f2
JR		 4045}
4046
a9ab13ff 4047static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
a547c6db 4048{
a547c6db
YZ		 4049}
4050
ae97a3b8
RK		 4051static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4052{
830f01b0 4053 if (!kvm_pause_in_guest(vcpu->kvm))
8566ac8b 4054 shrink_ple_window(vcpu);
ae97a3b8
RK		 4055}
4056
74f16909
BP		 4057static void svm_setup_mce(struct kvm_vcpu *vcpu)
4058{
4059 /* [63:9] are reserved. */
4060 vcpu->arch.mcg_cap &= 0x1ff;
4061}
4062
cae96af1 4063bool svm_smi_blocked(struct kvm_vcpu *vcpu)
72d7b374 4064{
05cade71
LP		 4065 struct vcpu_svm *svm = to_svm(vcpu);
4066
4067 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4068 if (!gif_set(svm))
cae96af1
PB		 4069 return true;
4070
4071 return is_smm(vcpu);
4072}
4073
c9d40913 4074static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
cae96af1
PB		 4075{
4076 struct vcpu_svm *svm = to_svm(vcpu);
4077 if (svm->nested.nested_run_pending)
c9d40913 4078 return -EBUSY;
05cade71 4079
c300ab9f
PB		 4080 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4081 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
c9d40913 4082 return -EBUSY;
c300ab9f 4083
cae96af1 4084 return !svm_smi_blocked(vcpu);
72d7b374
LP		 4085}
4086
0234bf88
LP		 4087static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4088{
05cade71
LP		 4089 struct vcpu_svm *svm = to_svm(vcpu);
4090 int ret;
4091
4092 if (is_guest_mode(vcpu)) {
4093 /* FED8h - SVM Guest */
4094 put_smstate(u64, smstate, 0x7ed8, 1);
4095 /* FEE0h - SVM Guest VMCB Physical Address */
0dd16b5b 4096 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
05cade71
LP		 4097
4098 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4099 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4100 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4101
4102 ret = nested_svm_vmexit(svm);
4103 if (ret)
4104 return ret;
4105 }
0234bf88
LP		 4106 return 0;
4107}
4108
ed19321f 4109static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
0234bf88 4110{
05cade71 4111 struct vcpu_svm *svm = to_svm(vcpu);
8c5fbf1a 4112 struct kvm_host_map map;
59cd9bc5 4113 int ret = 0;
05cade71 4114
3ebb5d26
ML		 4115 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4116 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4117 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
0dd16b5b 4118 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
05cade71 4119
3ebb5d26
ML		 4120 if (guest) {
4121 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4122 return 1;
4123
4124 if (!(saved_efer & EFER_SVME))
4125 return 1;
4126
4127 if (kvm_vcpu_map(&svm->vcpu,
0dd16b5b 4128 gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
3ebb5d26
ML		 4129 return 1;
4130
2fcf4876 4131 if (svm_allocate_nested(svm))
3ebb5d26
ML		 4132 return 1;
4133
0dd16b5b 4134 ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
3ebb5d26
ML		 4135 kvm_vcpu_unmap(&svm->vcpu, &map, true);
4136 }
05cade71 4137 }
59cd9bc5
VK		 4138
4139 return ret;
0234bf88
LP		 4140}
4141
c9d40913 4142static void enable_smi_window(struct kvm_vcpu *vcpu)
cc3d967f
LP		 4143{
4144 struct vcpu_svm *svm = to_svm(vcpu);
4145
4146 if (!gif_set(svm)) {
4147 if (vgif_enabled(svm))
a284ba56 4148 svm_set_intercept(svm, INTERCEPT_STGI);
cc3d967f 4149 /* STGI will cause a vm exit */
c9d40913
PB		 4150 } else {
4151 /* We must be in SMM; RSM will cause a vmexit anyway. */
cc3d967f 4152 }
cc3d967f
LP		 4153}
4154
09e3e2a1 4155static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
05d5a486 4156{
09e3e2a1
SC		 4157 bool smep, smap, is_user;
4158 unsigned long cr4;
e72436bc 4159
bc624d9f
TL		 4160 /*
4161 * When the guest is an SEV-ES guest, emulation is not possible.
4162 */
4163 if (sev_es_guest(vcpu->kvm))
4164 return false;
4165
05d5a486 4166 /*
118154bd
LA		 4167 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4168 *
4169 * Errata:
4170 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4171 * possible that CPU microcode implementing DecodeAssist will fail
4172 * to read bytes of instruction which caused #NPF. In this case,
4173 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4174 * return 0 instead of the correct guest instruction bytes.
4175 *
4176 * This happens because CPU microcode reading instruction bytes
4177 * uses a special opcode which attempts to read data using CPL=0
4178 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4179 * fault, it gives up and returns no instruction bytes.
4180 *
4181 * Detection:
4182 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4183 * returned 0 in GuestIntrBytes field of the VMCB.
4184 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4185 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4186 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4187 * a SMEP fault instead of #NPF).
4188 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4189 * As most guests enable SMAP if they have also enabled SMEP, use above
4190 * logic in order to attempt minimize false-positive of detecting errata
4191 * while still preserving all cases semantic correctness.
4192 *
4193 * Workaround:
4194 * To determine what instruction the guest was executing, the hypervisor
4195 * will have to decode the instruction at the instruction pointer.
05d5a486
SB		 4196 *
4197 * In non SEV guest, hypervisor will be able to read the guest
4198 * memory to decode the instruction pointer when insn_len is zero
4199 * so we return true to indicate that decoding is possible.
4200 *
4201 * But in the SEV guest, the guest memory is encrypted with the
4202 * guest specific key and hypervisor will not be able to decode the
4203 * instruction pointer so we will not able to workaround it. Lets
4204 * print the error and request to kill the guest.
4205 */
09e3e2a1
SC		 4206 if (likely(!insn || insn_len))
4207 return true;
4208
4209 /*
4210 * If RIP is invalid, go ahead with emulation which will cause an
4211 * internal error exit.
4212 */
4213 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4214 return true;
4215
4216 cr4 = kvm_read_cr4(vcpu);
4217 smep = cr4 & X86_CR4_SMEP;
4218 smap = cr4 & X86_CR4_SMAP;
4219 is_user = svm_get_cpl(vcpu) == 3;
118154bd 4220 if (smap && (!smep || is_user)) {
05d5a486
SB		 4221 if (!sev_guest(vcpu->kvm))
4222 return true;
4223
118154bd 4224 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
05d5a486
SB		 4225 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4226 }
4227
4228 return false;
4229}
4230
4b9852f4
LA		 4231static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4232{
4233 struct vcpu_svm *svm = to_svm(vcpu);
4234
4235 /*
4236 * TODO: Last condition latch INIT signals on vCPU when
4237 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
33b22172
PB		 4238 * To properly emulate the INIT intercept,
4239 * svm_check_nested_events() should call nested_svm_vmexit()
4240 * if an INIT signal is pending.
4b9852f4
LA		 4241 */
4242 return !gif_set(svm) ||
c62e2e94 4243 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4b9852f4
LA		 4244}
4245
eaf78265
JR		 4246static void svm_vm_destroy(struct kvm *kvm)
4247{
4248 avic_vm_destroy(kvm);
4249 sev_vm_destroy(kvm);
4250}
4251
4252static int svm_vm_init(struct kvm *kvm)
4253{
830f01b0
WL		 4254 if (!pause_filter_count || !pause_filter_thresh)
4255 kvm->arch.pause_in_guest = true;
4256
eaf78265
JR		 4257 if (avic) {
4258 int ret = avic_vm_init(kvm);
4259 if (ret)
4260 return ret;
4261 }
4262
4263 kvm_apicv_init(kvm, avic);
4264 return 0;
4265}
4266
9c14ee21 4267static struct kvm_x86_ops svm_x86_ops __initdata = {
dd58f3c9 4268 .hardware_unsetup = svm_hardware_teardown,
6aa8b732
AK		 4269 .hardware_enable = svm_hardware_enable,
4270 .hardware_disable = svm_hardware_disable,
774ead3a 4271 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
bc226f07 4272 .has_emulated_msr = svm_has_emulated_msr,
6aa8b732
AK		 4273
4274 .vcpu_create = svm_create_vcpu,
4275 .vcpu_free = svm_free_vcpu,
04d2cc77 4276 .vcpu_reset = svm_vcpu_reset,
6aa8b732 4277
562b6b08 4278 .vm_size = sizeof(struct kvm_svm),
4e19c36f 4279 .vm_init = svm_vm_init,
1654efcb 4280 .vm_destroy = svm_vm_destroy,
44a95dae 4281
04d2cc77 4282 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 4283 .vcpu_load = svm_vcpu_load,
4284 .vcpu_put = svm_vcpu_put,
8221c137
SS		 4285 .vcpu_blocking = svm_vcpu_blocking,
4286 .vcpu_unblocking = svm_vcpu_unblocking,
6aa8b732 4287
6986982f 4288 .update_exception_bitmap = update_exception_bitmap,
801e459a 4289 .get_msr_feature = svm_get_msr_feature,
6aa8b732
AK		 4290 .get_msr = svm_get_msr,
4291 .set_msr = svm_set_msr,
4292 .get_segment_base = svm_get_segment_base,
4293 .get_segment = svm_get_segment,
4294 .set_segment = svm_set_segment,
2e4d2653 4295 .get_cpl = svm_get_cpl,
1747fb71 4296 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
6aa8b732 4297 .set_cr0 = svm_set_cr0,
c2fe3cd4 4298 .is_valid_cr4 = svm_is_valid_cr4,
6aa8b732
AK		 4299 .set_cr4 = svm_set_cr4,
4300 .set_efer = svm_set_efer,
4301 .get_idt = svm_get_idt,
4302 .set_idt = svm_set_idt,
4303 .get_gdt = svm_get_gdt,
4304 .set_gdt = svm_set_gdt,
020df079 4305 .set_dr7 = svm_set_dr7,
facb0139 4306 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
6de4f3ad 4307 .cache_reg = svm_cache_reg,
6aa8b732
AK		 4308 .get_rflags = svm_get_rflags,
4309 .set_rflags = svm_set_rflags,
be94f6b7 4310
7780938c 4311 .tlb_flush_all = svm_flush_tlb,
eeeb4f67 4312 .tlb_flush_current = svm_flush_tlb,
faff8758 4313 .tlb_flush_gva = svm_flush_tlb_gva,
72b38320 4314 .tlb_flush_guest = svm_flush_tlb,
6aa8b732 4315
6aa8b732 4316 .run = svm_vcpu_run,
04d2cc77 4317 .handle_exit = handle_exit,
6aa8b732 4318 .skip_emulated_instruction = skip_emulated_instruction,
5ef8acbd 4319 .update_emulated_instruction = NULL,
2809f5d2
GC		 4320 .set_interrupt_shadow = svm_set_interrupt_shadow,
4321 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 4322 .patch_hypercall = svm_patch_hypercall,
2a8067f1 4323 .set_irq = svm_set_irq,
95ba8273 4324 .set_nmi = svm_inject_nmi,
298101da 4325 .queue_exception = svm_queue_exception,
b463a6f7 4326 .cancel_injection = svm_cancel_injection,
78646121 4327 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 4328 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 4329 .get_nmi_mask = svm_get_nmi_mask,
4330 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 4331 .enable_nmi_window = enable_nmi_window,
4332 .enable_irq_window = enable_irq_window,
4333 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 4334 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
d62caabb 4335 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
ef8efd7a 4336 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
2de9d0cc 4337 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
c7c9c56c 4338 .load_eoi_exitmap = svm_load_eoi_exitmap,
44a95dae
SS		 4339 .hwapic_irr_update = svm_hwapic_irr_update,
4340 .hwapic_isr_update = svm_hwapic_isr_update,
fa59cc00 4341 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
be8ca170 4342 .apicv_post_state_restore = avic_post_state_restore,
cbc94022
IE		 4343
4344 .set_tss_addr = svm_set_tss_addr,
2ac52ab8 4345 .set_identity_map_addr = svm_set_identity_map_addr,
4b12f0de 4346 .get_mt_mask = svm_get_mt_mask,
229456fc 4347
586f9607 4348 .get_exit_info = svm_get_exit_info,
586f9607 4349
7c1b761b 4350 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4e47c7a6 4351
f5f48ee1 4352 .has_wbinvd_exit = svm_has_wbinvd_exit,
99e3e30a 4353
326e7425 4354 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
1c97f0a0 4355
727a7e27 4356 .load_mmu_pgd = svm_load_mmu_pgd,
8a76d7f2
JR		 4357
4358 .check_intercept = svm_check_intercept,
95b5a48c 4359 .handle_exit_irqoff = svm_handle_exit_irqoff,
ae97a3b8 4360
d264ee0c
SC		 4361 .request_immediate_exit = __kvm_request_immediate_exit,
4362
ae97a3b8 4363 .sched_in = svm_sched_in,
25462f7f
WH		 4364
4365 .pmu_ops = &amd_pmu_ops,
33b22172
PB		 4366 .nested_ops = &svm_nested_ops,
4367
340d3bc3 4368 .deliver_posted_interrupt = svm_deliver_avic_intr,
17e433b5 4369 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
411b44ba 4370 .update_pi_irte = svm_update_pi_irte,
74f16909 4371 .setup_mce = svm_setup_mce,
0234bf88 4372
72d7b374 4373 .smi_allowed = svm_smi_allowed,
0234bf88
LP		 4374 .pre_enter_smm = svm_pre_enter_smm,
4375 .pre_leave_smm = svm_pre_leave_smm,
cc3d967f 4376 .enable_smi_window = enable_smi_window,
1654efcb
BS		 4377
4378 .mem_enc_op = svm_mem_enc_op,
1e80fdc0
BS		 4379 .mem_enc_reg_region = svm_register_enc_region,
4380 .mem_enc_unreg_region = svm_unregister_enc_region,
57b119da 4381
09e3e2a1 4382 .can_emulate_instruction = svm_can_emulate_instruction,
4b9852f4
LA		 4383
4384 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
fd6fa73d
AG		 4385
4386 .msr_filter_changed = svm_msr_filter_changed,
f1c6366e 4387 .complete_emulated_msr = svm_complete_emulated_msr,
6aa8b732
AK		 4388};
4389
d008dfdb
SC		 4390static struct kvm_x86_init_ops svm_init_ops __initdata = {
4391 .cpu_has_kvm_support = has_svm,
4392 .disabled_by_bios = is_disabled,
4393 .hardware_setup = svm_hardware_setup,
4394 .check_processor_compatibility = svm_check_processor_compat,
4395
4396 .runtime_ops = &svm_x86_ops,
6aa8b732
AK		 4397};
4398
4399static int __init svm_init(void)
4400{
d07f46f9
TL		 4401 __unused_size_checks();
4402
d008dfdb 4403 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
0ee75bea 4404 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 4405}
4406
4407static void __exit svm_exit(void)
4408{
cb498ea2 4409 kvm_exit();
6aa8b732
AK		 4410}
4411
4412module_init(svm_init)
4413module_exit(svm_exit)
Empty description
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