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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux.git] / drivers / net / mlx4 / fw.h
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225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef MLX4_FW_H
36#define MLX4_FW_H
37
38#include "mlx4.h"
39#include "icm.h"
40
2d928651
VS		 41struct mlx4_mod_stat_cfg {
42 u8 log_pg_sz;
43 u8 log_pg_sz_m;
44};
45
225c7b1f
RD		 46struct mlx4_dev_cap {
47 int max_srq_sz;
48 int max_qp_sz;
49 int reserved_qps;
50 int max_qps;
51 int reserved_srqs;
52 int max_srqs;
53 int max_cq_sz;
54 int reserved_cqs;
55 int max_cqs;
56 int max_mpts;
57 int reserved_eqs;
58 int max_eqs;
59 int reserved_mtts;
60 int max_mrw_sz;
61 int reserved_mrws;
62 int max_mtt_seg;
63 int max_requester_per_qp;
64 int max_responder_per_qp;
65 int max_rdma_global;
66 int local_ca_ack_delay;
225c7b1f 67 int num_ports;
149983af 68 u32 max_msg_sz;
b79acb49 69 int ib_mtu[MLX4_MAX_PORTS + 1];
5ae2a7a8
RD		 70 int max_port_width[MLX4_MAX_PORTS + 1];
71 int max_vl[MLX4_MAX_PORTS + 1];
72 int max_gids[MLX4_MAX_PORTS + 1];
73 int max_pkeys[MLX4_MAX_PORTS + 1];
b79acb49
YP		 74 u64 def_mac[MLX4_MAX_PORTS + 1];
75 u16 eth_mtu[MLX4_MAX_PORTS + 1];
225c7b1f 76 u16 stat_rate_support;
225c7b1f
RD		 77 u32 flags;
78 int reserved_uars;
79 int uar_size;
80 int min_page_sz;
81 int bf_reg_size;
82 int bf_regs_per_page;
83 int max_sq_sg;
84 int max_sq_desc_sz;
85 int max_rq_sg;
86 int max_rq_desc_sz;
87 int max_qp_per_mcg;
88 int reserved_mgms;
89 int max_mcgs;
90 int reserved_pds;
91 int max_pds;
92 int qpc_entry_sz;
93 int rdmarc_entry_sz;
94 int altc_entry_sz;
95 int aux_entry_sz;
96 int srq_entry_sz;
97 int cqc_entry_sz;
98 int eqc_entry_sz;
99 int dmpt_entry_sz;
100 int cmpt_entry_sz;
101 int mtt_entry_sz;
102 int resize_srq;
95d04f07 103 u32 bmme_flags;
225c7b1f
RD		 104 u32 reserved_lkey;
105 u64 max_icm_sz;
b832be1e 106 int max_gso_sz;
7ff93f8b 107 u8 supported_port_types[MLX4_MAX_PORTS + 1];
93fc9e1b
YP		 108 u8 log_max_macs[MLX4_MAX_PORTS + 1];
109 u8 log_max_vlans[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 110};
111
112struct mlx4_adapter {
225c7b1f
RD		 113 char board_id[MLX4_BOARD_ID_LEN];
114 u8 inta_pin;
115};
116
117struct mlx4_init_hca_param {
118 u64 qpc_base;
119 u64 rdmarc_base;
120 u64 auxc_base;
121 u64 altc_base;
122 u64 srqc_base;
123 u64 cqc_base;
124 u64 eqc_base;
125 u64 mc_base;
126 u64 dmpt_base;
127 u64 cmpt_base;
128 u64 mtt_base;
129 u16 log_mc_entry_sz;
130 u16 log_mc_hash_sz;
131 u8 log_num_qps;
132 u8 log_num_srqs;
133 u8 log_num_cqs;
134 u8 log_num_eqs;
135 u8 log_rd_per_qp;
136 u8 log_mc_table_sz;
137 u8 log_mpt_sz;
138 u8 log_uar_sz;
139};
140
141struct mlx4_init_ib_param {
142 int port_width;
143 int vl_cap;
144 int mtu_cap;
145 u16 gid_cap;
146 u16 pkey_cap;
147 int set_guid0;
148 u64 guid0;
149 int set_node_guid;
150 u64 node_guid;
151 int set_si_guid;
152 u64 si_guid;
153};
154
155struct mlx4_set_ib_param {
156 int set_si_guid;
157 int reset_qkey_viol;
158 u64 si_guid;
159 u32 cap_mask;
160};
161
162int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
163int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm);
164int mlx4_UNMAP_FA(struct mlx4_dev *dev);
165int mlx4_RUN_FW(struct mlx4_dev *dev);
166int mlx4_QUERY_FW(struct mlx4_dev *dev);
167int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter);
168int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
169int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
170int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt);
171int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages);
172int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
173int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
174int mlx4_NOP(struct mlx4_dev *dev);
2d928651 175int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
225c7b1f
RD		 176
177#endif /* MLX4_FW_H */
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