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2707e444 ZW |
1 | /* |
2 | * GTT virtualization | |
3 | * | |
4 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
23 | * SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Zhi Wang <[email protected]> | |
27 | * Zhenyu Wang <[email protected]> | |
28 | * Xiao Zheng <[email protected]> | |
29 | * | |
30 | * Contributors: | |
31 | * Min He <[email protected]> | |
32 | * Bing Niu <[email protected]> | |
33 | * | |
34 | */ | |
35 | ||
36 | #include "i915_drv.h" | |
feddf6e8 ZW |
37 | #include "gvt.h" |
38 | #include "i915_pvinfo.h" | |
2707e444 ZW |
39 | #include "trace.h" |
40 | ||
41 | static bool enable_out_of_sync = false; | |
42 | static int preallocated_oos_pages = 8192; | |
43 | ||
44 | /* | |
45 | * validate a gm address and related range size, | |
46 | * translate it to host gm address | |
47 | */ | |
48 | bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size) | |
49 | { | |
50 | if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size | |
51 | && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) { | |
52 | gvt_err("vgpu%d: invalid range gmadr 0x%llx size 0x%x\n", | |
53 | vgpu->id, addr, size); | |
54 | return false; | |
55 | } | |
56 | return true; | |
57 | } | |
58 | ||
59 | /* translate a guest gmadr to host gmadr */ | |
60 | int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr) | |
61 | { | |
62 | if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr), | |
63 | "invalid guest gmadr %llx\n", g_addr)) | |
64 | return -EACCES; | |
65 | ||
66 | if (vgpu_gmadr_is_aperture(vgpu, g_addr)) | |
67 | *h_addr = vgpu_aperture_gmadr_base(vgpu) | |
68 | + (g_addr - vgpu_aperture_offset(vgpu)); | |
69 | else | |
70 | *h_addr = vgpu_hidden_gmadr_base(vgpu) | |
71 | + (g_addr - vgpu_hidden_offset(vgpu)); | |
72 | return 0; | |
73 | } | |
74 | ||
75 | /* translate a host gmadr to guest gmadr */ | |
76 | int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr) | |
77 | { | |
78 | if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr), | |
79 | "invalid host gmadr %llx\n", h_addr)) | |
80 | return -EACCES; | |
81 | ||
82 | if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr)) | |
83 | *g_addr = vgpu_aperture_gmadr_base(vgpu) | |
84 | + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt)); | |
85 | else | |
86 | *g_addr = vgpu_hidden_gmadr_base(vgpu) | |
87 | + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt)); | |
88 | return 0; | |
89 | } | |
90 | ||
91 | int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, | |
92 | unsigned long *h_index) | |
93 | { | |
94 | u64 h_addr; | |
95 | int ret; | |
96 | ||
97 | ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << GTT_PAGE_SHIFT, | |
98 | &h_addr); | |
99 | if (ret) | |
100 | return ret; | |
101 | ||
102 | *h_index = h_addr >> GTT_PAGE_SHIFT; | |
103 | return 0; | |
104 | } | |
105 | ||
106 | int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, | |
107 | unsigned long *g_index) | |
108 | { | |
109 | u64 g_addr; | |
110 | int ret; | |
111 | ||
112 | ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << GTT_PAGE_SHIFT, | |
113 | &g_addr); | |
114 | if (ret) | |
115 | return ret; | |
116 | ||
117 | *g_index = g_addr >> GTT_PAGE_SHIFT; | |
118 | return 0; | |
119 | } | |
120 | ||
121 | #define gtt_type_is_entry(type) \ | |
122 | (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \ | |
123 | && type != GTT_TYPE_PPGTT_PTE_ENTRY \ | |
124 | && type != GTT_TYPE_PPGTT_ROOT_ENTRY) | |
125 | ||
126 | #define gtt_type_is_pt(type) \ | |
127 | (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX) | |
128 | ||
129 | #define gtt_type_is_pte_pt(type) \ | |
130 | (type == GTT_TYPE_PPGTT_PTE_PT) | |
131 | ||
132 | #define gtt_type_is_root_pointer(type) \ | |
133 | (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY) | |
134 | ||
135 | #define gtt_init_entry(e, t, p, v) do { \ | |
136 | (e)->type = t; \ | |
137 | (e)->pdev = p; \ | |
138 | memcpy(&(e)->val64, &v, sizeof(v)); \ | |
139 | } while (0) | |
140 | ||
2707e444 ZW |
141 | /* |
142 | * Mappings between GTT_TYPE* enumerations. | |
143 | * Following information can be found according to the given type: | |
144 | * - type of next level page table | |
145 | * - type of entry inside this level page table | |
146 | * - type of entry with PSE set | |
147 | * | |
148 | * If the given type doesn't have such a kind of information, | |
149 | * e.g. give a l4 root entry type, then request to get its PSE type, | |
150 | * give a PTE page table type, then request to get its next level page | |
151 | * table type, as we know l4 root entry doesn't have a PSE bit, | |
152 | * and a PTE page table doesn't have a next level page table type, | |
153 | * GTT_TYPE_INVALID will be returned. This is useful when traversing a | |
154 | * page table. | |
155 | */ | |
156 | ||
157 | struct gtt_type_table_entry { | |
158 | int entry_type; | |
159 | int next_pt_type; | |
160 | int pse_entry_type; | |
161 | }; | |
162 | ||
163 | #define GTT_TYPE_TABLE_ENTRY(type, e_type, npt_type, pse_type) \ | |
164 | [type] = { \ | |
165 | .entry_type = e_type, \ | |
166 | .next_pt_type = npt_type, \ | |
167 | .pse_entry_type = pse_type, \ | |
168 | } | |
169 | ||
170 | static struct gtt_type_table_entry gtt_type_table[] = { | |
171 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY, | |
172 | GTT_TYPE_PPGTT_ROOT_L4_ENTRY, | |
173 | GTT_TYPE_PPGTT_PML4_PT, | |
174 | GTT_TYPE_INVALID), | |
175 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT, | |
176 | GTT_TYPE_PPGTT_PML4_ENTRY, | |
177 | GTT_TYPE_PPGTT_PDP_PT, | |
178 | GTT_TYPE_INVALID), | |
179 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY, | |
180 | GTT_TYPE_PPGTT_PML4_ENTRY, | |
181 | GTT_TYPE_PPGTT_PDP_PT, | |
182 | GTT_TYPE_INVALID), | |
183 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT, | |
184 | GTT_TYPE_PPGTT_PDP_ENTRY, | |
185 | GTT_TYPE_PPGTT_PDE_PT, | |
186 | GTT_TYPE_PPGTT_PTE_1G_ENTRY), | |
187 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY, | |
188 | GTT_TYPE_PPGTT_ROOT_L3_ENTRY, | |
189 | GTT_TYPE_PPGTT_PDE_PT, | |
190 | GTT_TYPE_PPGTT_PTE_1G_ENTRY), | |
191 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY, | |
192 | GTT_TYPE_PPGTT_PDP_ENTRY, | |
193 | GTT_TYPE_PPGTT_PDE_PT, | |
194 | GTT_TYPE_PPGTT_PTE_1G_ENTRY), | |
195 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT, | |
196 | GTT_TYPE_PPGTT_PDE_ENTRY, | |
197 | GTT_TYPE_PPGTT_PTE_PT, | |
198 | GTT_TYPE_PPGTT_PTE_2M_ENTRY), | |
199 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY, | |
200 | GTT_TYPE_PPGTT_PDE_ENTRY, | |
201 | GTT_TYPE_PPGTT_PTE_PT, | |
202 | GTT_TYPE_PPGTT_PTE_2M_ENTRY), | |
203 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT, | |
204 | GTT_TYPE_PPGTT_PTE_4K_ENTRY, | |
205 | GTT_TYPE_INVALID, | |
206 | GTT_TYPE_INVALID), | |
207 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY, | |
208 | GTT_TYPE_PPGTT_PTE_4K_ENTRY, | |
209 | GTT_TYPE_INVALID, | |
210 | GTT_TYPE_INVALID), | |
211 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY, | |
212 | GTT_TYPE_PPGTT_PDE_ENTRY, | |
213 | GTT_TYPE_INVALID, | |
214 | GTT_TYPE_PPGTT_PTE_2M_ENTRY), | |
215 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY, | |
216 | GTT_TYPE_PPGTT_PDP_ENTRY, | |
217 | GTT_TYPE_INVALID, | |
218 | GTT_TYPE_PPGTT_PTE_1G_ENTRY), | |
219 | GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE, | |
220 | GTT_TYPE_GGTT_PTE, | |
221 | GTT_TYPE_INVALID, | |
222 | GTT_TYPE_INVALID), | |
223 | }; | |
224 | ||
225 | static inline int get_next_pt_type(int type) | |
226 | { | |
227 | return gtt_type_table[type].next_pt_type; | |
228 | } | |
229 | ||
230 | static inline int get_entry_type(int type) | |
231 | { | |
232 | return gtt_type_table[type].entry_type; | |
233 | } | |
234 | ||
235 | static inline int get_pse_type(int type) | |
236 | { | |
237 | return gtt_type_table[type].pse_entry_type; | |
238 | } | |
239 | ||
240 | static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index) | |
241 | { | |
321927db | 242 | void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index; |
905a5035 CD |
243 | |
244 | return readq(addr); | |
2707e444 ZW |
245 | } |
246 | ||
247 | static void write_pte64(struct drm_i915_private *dev_priv, | |
248 | unsigned long index, u64 pte) | |
249 | { | |
321927db | 250 | void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index; |
2707e444 | 251 | |
2707e444 | 252 | writeq(pte, addr); |
905a5035 | 253 | |
2707e444 ZW |
254 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
255 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
256 | } | |
257 | ||
258 | static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt, | |
259 | struct intel_gvt_gtt_entry *e, | |
260 | unsigned long index, bool hypervisor_access, unsigned long gpa, | |
261 | struct intel_vgpu *vgpu) | |
262 | { | |
263 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; | |
264 | int ret; | |
265 | ||
266 | if (WARN_ON(info->gtt_entry_size != 8)) | |
267 | return e; | |
268 | ||
269 | if (hypervisor_access) { | |
270 | ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa + | |
271 | (index << info->gtt_entry_size_shift), | |
272 | &e->val64, 8); | |
273 | WARN_ON(ret); | |
274 | } else if (!pt) { | |
275 | e->val64 = read_pte64(vgpu->gvt->dev_priv, index); | |
276 | } else { | |
277 | e->val64 = *((u64 *)pt + index); | |
278 | } | |
279 | return e; | |
280 | } | |
281 | ||
282 | static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt, | |
283 | struct intel_gvt_gtt_entry *e, | |
284 | unsigned long index, bool hypervisor_access, unsigned long gpa, | |
285 | struct intel_vgpu *vgpu) | |
286 | { | |
287 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; | |
288 | int ret; | |
289 | ||
290 | if (WARN_ON(info->gtt_entry_size != 8)) | |
291 | return e; | |
292 | ||
293 | if (hypervisor_access) { | |
294 | ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa + | |
295 | (index << info->gtt_entry_size_shift), | |
296 | &e->val64, 8); | |
297 | WARN_ON(ret); | |
298 | } else if (!pt) { | |
299 | write_pte64(vgpu->gvt->dev_priv, index, e->val64); | |
300 | } else { | |
301 | *((u64 *)pt + index) = e->val64; | |
302 | } | |
303 | return e; | |
304 | } | |
305 | ||
306 | #define GTT_HAW 46 | |
307 | ||
308 | #define ADDR_1G_MASK (((1UL << (GTT_HAW - 30 + 1)) - 1) << 30) | |
309 | #define ADDR_2M_MASK (((1UL << (GTT_HAW - 21 + 1)) - 1) << 21) | |
310 | #define ADDR_4K_MASK (((1UL << (GTT_HAW - 12 + 1)) - 1) << 12) | |
311 | ||
312 | static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e) | |
313 | { | |
314 | unsigned long pfn; | |
315 | ||
316 | if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) | |
317 | pfn = (e->val64 & ADDR_1G_MASK) >> 12; | |
318 | else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) | |
319 | pfn = (e->val64 & ADDR_2M_MASK) >> 12; | |
320 | else | |
321 | pfn = (e->val64 & ADDR_4K_MASK) >> 12; | |
322 | return pfn; | |
323 | } | |
324 | ||
325 | static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn) | |
326 | { | |
327 | if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) { | |
328 | e->val64 &= ~ADDR_1G_MASK; | |
329 | pfn &= (ADDR_1G_MASK >> 12); | |
330 | } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) { | |
331 | e->val64 &= ~ADDR_2M_MASK; | |
332 | pfn &= (ADDR_2M_MASK >> 12); | |
333 | } else { | |
334 | e->val64 &= ~ADDR_4K_MASK; | |
335 | pfn &= (ADDR_4K_MASK >> 12); | |
336 | } | |
337 | ||
338 | e->val64 |= (pfn << 12); | |
339 | } | |
340 | ||
341 | static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e) | |
342 | { | |
343 | /* Entry doesn't have PSE bit. */ | |
344 | if (get_pse_type(e->type) == GTT_TYPE_INVALID) | |
345 | return false; | |
346 | ||
347 | e->type = get_entry_type(e->type); | |
348 | if (!(e->val64 & (1 << 7))) | |
349 | return false; | |
350 | ||
351 | e->type = get_pse_type(e->type); | |
352 | return true; | |
353 | } | |
354 | ||
355 | static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e) | |
356 | { | |
357 | /* | |
358 | * i915 writes PDP root pointer registers without present bit, | |
359 | * it also works, so we need to treat root pointer entry | |
360 | * specifically. | |
361 | */ | |
362 | if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY | |
363 | || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) | |
364 | return (e->val64 != 0); | |
365 | else | |
366 | return (e->val64 & (1 << 0)); | |
367 | } | |
368 | ||
369 | static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e) | |
370 | { | |
371 | e->val64 &= ~(1 << 0); | |
372 | } | |
373 | ||
374 | /* | |
375 | * Per-platform GMA routines. | |
376 | */ | |
377 | static unsigned long gma_to_ggtt_pte_index(unsigned long gma) | |
378 | { | |
379 | unsigned long x = (gma >> GTT_PAGE_SHIFT); | |
380 | ||
381 | trace_gma_index(__func__, gma, x); | |
382 | return x; | |
383 | } | |
384 | ||
385 | #define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \ | |
386 | static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \ | |
387 | { \ | |
388 | unsigned long x = (exp); \ | |
389 | trace_gma_index(__func__, gma, x); \ | |
390 | return x; \ | |
391 | } | |
392 | ||
393 | DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff)); | |
394 | DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff)); | |
395 | DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3)); | |
396 | DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff)); | |
397 | DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff)); | |
398 | ||
399 | static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = { | |
400 | .get_entry = gtt_get_entry64, | |
401 | .set_entry = gtt_set_entry64, | |
402 | .clear_present = gtt_entry_clear_present, | |
403 | .test_present = gen8_gtt_test_present, | |
404 | .test_pse = gen8_gtt_test_pse, | |
405 | .get_pfn = gen8_gtt_get_pfn, | |
406 | .set_pfn = gen8_gtt_set_pfn, | |
407 | }; | |
408 | ||
409 | static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = { | |
410 | .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index, | |
411 | .gma_to_pte_index = gen8_gma_to_pte_index, | |
412 | .gma_to_pde_index = gen8_gma_to_pde_index, | |
413 | .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index, | |
414 | .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index, | |
415 | .gma_to_pml4_index = gen8_gma_to_pml4_index, | |
416 | }; | |
417 | ||
418 | static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p, | |
419 | struct intel_gvt_gtt_entry *m) | |
420 | { | |
421 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; | |
422 | unsigned long gfn, mfn; | |
423 | ||
424 | *m = *p; | |
425 | ||
426 | if (!ops->test_present(p)) | |
427 | return 0; | |
428 | ||
429 | gfn = ops->get_pfn(p); | |
430 | ||
431 | mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn); | |
432 | if (mfn == INTEL_GVT_INVALID_ADDR) { | |
433 | gvt_err("fail to translate gfn: 0x%lx\n", gfn); | |
434 | return -ENXIO; | |
435 | } | |
436 | ||
437 | ops->set_pfn(m, mfn); | |
438 | return 0; | |
439 | } | |
440 | ||
441 | /* | |
442 | * MM helpers. | |
443 | */ | |
444 | struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm, | |
445 | void *page_table, struct intel_gvt_gtt_entry *e, | |
446 | unsigned long index) | |
447 | { | |
448 | struct intel_gvt *gvt = mm->vgpu->gvt; | |
449 | struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; | |
450 | ||
451 | e->type = mm->page_table_entry_type; | |
452 | ||
453 | ops->get_entry(page_table, e, index, false, 0, mm->vgpu); | |
454 | ops->test_pse(e); | |
455 | return e; | |
456 | } | |
457 | ||
458 | struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, | |
459 | void *page_table, struct intel_gvt_gtt_entry *e, | |
460 | unsigned long index) | |
461 | { | |
462 | struct intel_gvt *gvt = mm->vgpu->gvt; | |
463 | struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; | |
464 | ||
465 | return ops->set_entry(page_table, e, index, false, 0, mm->vgpu); | |
466 | } | |
467 | ||
468 | /* | |
469 | * PPGTT shadow page table helpers. | |
470 | */ | |
471 | static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry( | |
472 | struct intel_vgpu_ppgtt_spt *spt, | |
473 | void *page_table, int type, | |
474 | struct intel_gvt_gtt_entry *e, unsigned long index, | |
475 | bool guest) | |
476 | { | |
477 | struct intel_gvt *gvt = spt->vgpu->gvt; | |
478 | struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; | |
479 | ||
480 | e->type = get_entry_type(type); | |
481 | ||
482 | if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n")) | |
483 | return e; | |
484 | ||
485 | ops->get_entry(page_table, e, index, guest, | |
486 | spt->guest_page.gfn << GTT_PAGE_SHIFT, | |
487 | spt->vgpu); | |
488 | ops->test_pse(e); | |
489 | return e; | |
490 | } | |
491 | ||
492 | static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry( | |
493 | struct intel_vgpu_ppgtt_spt *spt, | |
494 | void *page_table, int type, | |
495 | struct intel_gvt_gtt_entry *e, unsigned long index, | |
496 | bool guest) | |
497 | { | |
498 | struct intel_gvt *gvt = spt->vgpu->gvt; | |
499 | struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; | |
500 | ||
501 | if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n")) | |
502 | return e; | |
503 | ||
504 | return ops->set_entry(page_table, e, index, guest, | |
505 | spt->guest_page.gfn << GTT_PAGE_SHIFT, | |
506 | spt->vgpu); | |
507 | } | |
508 | ||
509 | #define ppgtt_get_guest_entry(spt, e, index) \ | |
510 | ppgtt_spt_get_entry(spt, NULL, \ | |
511 | spt->guest_page_type, e, index, true) | |
512 | ||
513 | #define ppgtt_set_guest_entry(spt, e, index) \ | |
514 | ppgtt_spt_set_entry(spt, NULL, \ | |
515 | spt->guest_page_type, e, index, true) | |
516 | ||
517 | #define ppgtt_get_shadow_entry(spt, e, index) \ | |
518 | ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \ | |
519 | spt->shadow_page.type, e, index, false) | |
520 | ||
521 | #define ppgtt_set_shadow_entry(spt, e, index) \ | |
522 | ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \ | |
523 | spt->shadow_page.type, e, index, false) | |
524 | ||
525 | /** | |
526 | * intel_vgpu_init_guest_page - init a guest page data structure | |
527 | * @vgpu: a vGPU | |
528 | * @p: a guest page data structure | |
529 | * @gfn: guest memory page frame number | |
530 | * @handler: function will be called when target guest memory page has | |
531 | * been modified. | |
532 | * | |
533 | * This function is called when user wants to track a guest memory page. | |
534 | * | |
535 | * Returns: | |
536 | * Zero on success, negative error code if failed. | |
537 | */ | |
538 | int intel_vgpu_init_guest_page(struct intel_vgpu *vgpu, | |
539 | struct intel_vgpu_guest_page *p, | |
540 | unsigned long gfn, | |
541 | int (*handler)(void *, u64, void *, int), | |
542 | void *data) | |
543 | { | |
544 | INIT_HLIST_NODE(&p->node); | |
545 | ||
546 | p->writeprotection = false; | |
547 | p->gfn = gfn; | |
548 | p->handler = handler; | |
549 | p->data = data; | |
550 | p->oos_page = NULL; | |
551 | p->write_cnt = 0; | |
552 | ||
553 | hash_add(vgpu->gtt.guest_page_hash_table, &p->node, p->gfn); | |
554 | return 0; | |
555 | } | |
556 | ||
557 | static int detach_oos_page(struct intel_vgpu *vgpu, | |
558 | struct intel_vgpu_oos_page *oos_page); | |
559 | ||
560 | /** | |
561 | * intel_vgpu_clean_guest_page - release the resource owned by guest page data | |
562 | * structure | |
563 | * @vgpu: a vGPU | |
564 | * @p: a tracked guest page | |
565 | * | |
566 | * This function is called when user tries to stop tracking a guest memory | |
567 | * page. | |
568 | */ | |
569 | void intel_vgpu_clean_guest_page(struct intel_vgpu *vgpu, | |
570 | struct intel_vgpu_guest_page *p) | |
571 | { | |
572 | if (!hlist_unhashed(&p->node)) | |
573 | hash_del(&p->node); | |
574 | ||
575 | if (p->oos_page) | |
576 | detach_oos_page(vgpu, p->oos_page); | |
577 | ||
578 | if (p->writeprotection) | |
579 | intel_gvt_hypervisor_unset_wp_page(vgpu, p); | |
580 | } | |
581 | ||
582 | /** | |
583 | * intel_vgpu_find_guest_page - find a guest page data structure by GFN. | |
584 | * @vgpu: a vGPU | |
585 | * @gfn: guest memory page frame number | |
586 | * | |
587 | * This function is called when emulation logic wants to know if a trapped GFN | |
588 | * is a tracked guest page. | |
589 | * | |
590 | * Returns: | |
591 | * Pointer to guest page data structure, NULL if failed. | |
592 | */ | |
593 | struct intel_vgpu_guest_page *intel_vgpu_find_guest_page( | |
594 | struct intel_vgpu *vgpu, unsigned long gfn) | |
595 | { | |
596 | struct intel_vgpu_guest_page *p; | |
597 | ||
598 | hash_for_each_possible(vgpu->gtt.guest_page_hash_table, | |
599 | p, node, gfn) { | |
600 | if (p->gfn == gfn) | |
601 | return p; | |
602 | } | |
603 | return NULL; | |
604 | } | |
605 | ||
606 | static inline int init_shadow_page(struct intel_vgpu *vgpu, | |
607 | struct intel_vgpu_shadow_page *p, int type) | |
608 | { | |
5de6bd4c CD |
609 | struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev; |
610 | dma_addr_t daddr; | |
611 | ||
612 | daddr = dma_map_page(kdev, p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
613 | if (dma_mapping_error(kdev, daddr)) { | |
614 | gvt_err("fail to map dma addr\n"); | |
615 | return -EINVAL; | |
616 | } | |
617 | ||
2707e444 ZW |
618 | p->vaddr = page_address(p->page); |
619 | p->type = type; | |
620 | ||
621 | INIT_HLIST_NODE(&p->node); | |
622 | ||
5de6bd4c | 623 | p->mfn = daddr >> GTT_PAGE_SHIFT; |
2707e444 ZW |
624 | hash_add(vgpu->gtt.shadow_page_hash_table, &p->node, p->mfn); |
625 | return 0; | |
626 | } | |
627 | ||
5de6bd4c CD |
628 | static inline void clean_shadow_page(struct intel_vgpu *vgpu, |
629 | struct intel_vgpu_shadow_page *p) | |
2707e444 | 630 | { |
5de6bd4c CD |
631 | struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev; |
632 | ||
633 | dma_unmap_page(kdev, p->mfn << GTT_PAGE_SHIFT, 4096, | |
634 | PCI_DMA_BIDIRECTIONAL); | |
635 | ||
2707e444 ZW |
636 | if (!hlist_unhashed(&p->node)) |
637 | hash_del(&p->node); | |
638 | } | |
639 | ||
640 | static inline struct intel_vgpu_shadow_page *find_shadow_page( | |
641 | struct intel_vgpu *vgpu, unsigned long mfn) | |
642 | { | |
643 | struct intel_vgpu_shadow_page *p; | |
644 | ||
645 | hash_for_each_possible(vgpu->gtt.shadow_page_hash_table, | |
646 | p, node, mfn) { | |
647 | if (p->mfn == mfn) | |
648 | return p; | |
649 | } | |
650 | return NULL; | |
651 | } | |
652 | ||
653 | #define guest_page_to_ppgtt_spt(ptr) \ | |
654 | container_of(ptr, struct intel_vgpu_ppgtt_spt, guest_page) | |
655 | ||
656 | #define shadow_page_to_ppgtt_spt(ptr) \ | |
657 | container_of(ptr, struct intel_vgpu_ppgtt_spt, shadow_page) | |
658 | ||
659 | static void *alloc_spt(gfp_t gfp_mask) | |
660 | { | |
661 | struct intel_vgpu_ppgtt_spt *spt; | |
662 | ||
663 | spt = kzalloc(sizeof(*spt), gfp_mask); | |
664 | if (!spt) | |
665 | return NULL; | |
666 | ||
667 | spt->shadow_page.page = alloc_page(gfp_mask); | |
668 | if (!spt->shadow_page.page) { | |
669 | kfree(spt); | |
670 | return NULL; | |
671 | } | |
672 | return spt; | |
673 | } | |
674 | ||
675 | static void free_spt(struct intel_vgpu_ppgtt_spt *spt) | |
676 | { | |
677 | __free_page(spt->shadow_page.page); | |
678 | kfree(spt); | |
679 | } | |
680 | ||
681 | static void ppgtt_free_shadow_page(struct intel_vgpu_ppgtt_spt *spt) | |
682 | { | |
683 | trace_spt_free(spt->vgpu->id, spt, spt->shadow_page.type); | |
684 | ||
5de6bd4c | 685 | clean_shadow_page(spt->vgpu, &spt->shadow_page); |
2707e444 ZW |
686 | intel_vgpu_clean_guest_page(spt->vgpu, &spt->guest_page); |
687 | list_del_init(&spt->post_shadow_list); | |
688 | ||
689 | free_spt(spt); | |
690 | } | |
691 | ||
692 | static void ppgtt_free_all_shadow_page(struct intel_vgpu *vgpu) | |
693 | { | |
694 | struct hlist_node *n; | |
695 | struct intel_vgpu_shadow_page *sp; | |
696 | int i; | |
697 | ||
698 | hash_for_each_safe(vgpu->gtt.shadow_page_hash_table, i, n, sp, node) | |
699 | ppgtt_free_shadow_page(shadow_page_to_ppgtt_spt(sp)); | |
700 | } | |
701 | ||
702 | static int ppgtt_handle_guest_write_page_table_bytes(void *gp, | |
703 | u64 pa, void *p_data, int bytes); | |
704 | ||
705 | static int ppgtt_write_protection_handler(void *gp, u64 pa, | |
706 | void *p_data, int bytes) | |
707 | { | |
708 | struct intel_vgpu_guest_page *gpt = (struct intel_vgpu_guest_page *)gp; | |
709 | int ret; | |
710 | ||
711 | if (bytes != 4 && bytes != 8) | |
712 | return -EINVAL; | |
713 | ||
714 | if (!gpt->writeprotection) | |
715 | return -EINVAL; | |
716 | ||
717 | ret = ppgtt_handle_guest_write_page_table_bytes(gp, | |
718 | pa, p_data, bytes); | |
719 | if (ret) | |
720 | return ret; | |
721 | return ret; | |
722 | } | |
723 | ||
724 | static int reclaim_one_mm(struct intel_gvt *gvt); | |
725 | ||
726 | static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_shadow_page( | |
727 | struct intel_vgpu *vgpu, int type, unsigned long gfn) | |
728 | { | |
729 | struct intel_vgpu_ppgtt_spt *spt = NULL; | |
730 | int ret; | |
731 | ||
732 | retry: | |
733 | spt = alloc_spt(GFP_KERNEL | __GFP_ZERO); | |
734 | if (!spt) { | |
735 | if (reclaim_one_mm(vgpu->gvt)) | |
736 | goto retry; | |
737 | ||
738 | gvt_err("fail to allocate ppgtt shadow page\n"); | |
739 | return ERR_PTR(-ENOMEM); | |
740 | } | |
741 | ||
742 | spt->vgpu = vgpu; | |
743 | spt->guest_page_type = type; | |
744 | atomic_set(&spt->refcount, 1); | |
745 | INIT_LIST_HEAD(&spt->post_shadow_list); | |
746 | ||
747 | /* | |
748 | * TODO: guest page type may be different with shadow page type, | |
749 | * when we support PSE page in future. | |
750 | */ | |
751 | ret = init_shadow_page(vgpu, &spt->shadow_page, type); | |
752 | if (ret) { | |
753 | gvt_err("fail to initialize shadow page for spt\n"); | |
754 | goto err; | |
755 | } | |
756 | ||
757 | ret = intel_vgpu_init_guest_page(vgpu, &spt->guest_page, | |
758 | gfn, ppgtt_write_protection_handler, NULL); | |
759 | if (ret) { | |
760 | gvt_err("fail to initialize guest page for spt\n"); | |
761 | goto err; | |
762 | } | |
763 | ||
764 | trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn); | |
765 | return spt; | |
766 | err: | |
767 | ppgtt_free_shadow_page(spt); | |
768 | return ERR_PTR(ret); | |
769 | } | |
770 | ||
771 | static struct intel_vgpu_ppgtt_spt *ppgtt_find_shadow_page( | |
772 | struct intel_vgpu *vgpu, unsigned long mfn) | |
773 | { | |
774 | struct intel_vgpu_shadow_page *p = find_shadow_page(vgpu, mfn); | |
775 | ||
776 | if (p) | |
777 | return shadow_page_to_ppgtt_spt(p); | |
778 | ||
779 | gvt_err("vgpu%d: fail to find ppgtt shadow page: 0x%lx\n", | |
780 | vgpu->id, mfn); | |
781 | return NULL; | |
782 | } | |
783 | ||
784 | #define pt_entry_size_shift(spt) \ | |
785 | ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift) | |
786 | ||
787 | #define pt_entries(spt) \ | |
788 | (GTT_PAGE_SIZE >> pt_entry_size_shift(spt)) | |
789 | ||
790 | #define for_each_present_guest_entry(spt, e, i) \ | |
791 | for (i = 0; i < pt_entries(spt); i++) \ | |
792 | if (spt->vgpu->gvt->gtt.pte_ops->test_present( \ | |
793 | ppgtt_get_guest_entry(spt, e, i))) | |
794 | ||
795 | #define for_each_present_shadow_entry(spt, e, i) \ | |
796 | for (i = 0; i < pt_entries(spt); i++) \ | |
797 | if (spt->vgpu->gvt->gtt.pte_ops->test_present( \ | |
798 | ppgtt_get_shadow_entry(spt, e, i))) | |
799 | ||
800 | static void ppgtt_get_shadow_page(struct intel_vgpu_ppgtt_spt *spt) | |
801 | { | |
802 | int v = atomic_read(&spt->refcount); | |
803 | ||
804 | trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1)); | |
805 | ||
806 | atomic_inc(&spt->refcount); | |
807 | } | |
808 | ||
809 | static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt); | |
810 | ||
811 | static int ppgtt_invalidate_shadow_page_by_shadow_entry(struct intel_vgpu *vgpu, | |
812 | struct intel_gvt_gtt_entry *e) | |
813 | { | |
814 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; | |
815 | struct intel_vgpu_ppgtt_spt *s; | |
3b6411c2 | 816 | intel_gvt_gtt_type_t cur_pt_type; |
2707e444 ZW |
817 | |
818 | if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(e->type)))) | |
819 | return -EINVAL; | |
820 | ||
3b6411c2 PG |
821 | if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY |
822 | && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { | |
823 | cur_pt_type = get_next_pt_type(e->type) + 1; | |
824 | if (ops->get_pfn(e) == | |
825 | vgpu->gtt.scratch_pt[cur_pt_type].page_mfn) | |
826 | return 0; | |
827 | } | |
2707e444 ZW |
828 | s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e)); |
829 | if (!s) { | |
830 | gvt_err("vgpu%d: fail to find shadow page: mfn: 0x%lx\n", | |
831 | vgpu->id, ops->get_pfn(e)); | |
832 | return -ENXIO; | |
833 | } | |
834 | return ppgtt_invalidate_shadow_page(s); | |
835 | } | |
836 | ||
837 | static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt *spt) | |
838 | { | |
839 | struct intel_gvt_gtt_entry e; | |
840 | unsigned long index; | |
841 | int ret; | |
842 | int v = atomic_read(&spt->refcount); | |
843 | ||
844 | trace_spt_change(spt->vgpu->id, "die", spt, | |
845 | spt->guest_page.gfn, spt->shadow_page.type); | |
846 | ||
847 | trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1)); | |
848 | ||
849 | if (atomic_dec_return(&spt->refcount) > 0) | |
850 | return 0; | |
851 | ||
852 | if (gtt_type_is_pte_pt(spt->shadow_page.type)) | |
853 | goto release; | |
854 | ||
855 | for_each_present_shadow_entry(spt, &e, index) { | |
856 | if (!gtt_type_is_pt(get_next_pt_type(e.type))) { | |
857 | gvt_err("GVT doesn't support pse bit for now\n"); | |
858 | return -EINVAL; | |
859 | } | |
860 | ret = ppgtt_invalidate_shadow_page_by_shadow_entry( | |
861 | spt->vgpu, &e); | |
862 | if (ret) | |
863 | goto fail; | |
864 | } | |
865 | release: | |
866 | trace_spt_change(spt->vgpu->id, "release", spt, | |
867 | spt->guest_page.gfn, spt->shadow_page.type); | |
868 | ppgtt_free_shadow_page(spt); | |
869 | return 0; | |
870 | fail: | |
871 | gvt_err("vgpu%d: fail: shadow page %p shadow entry 0x%llx type %d\n", | |
872 | spt->vgpu->id, spt, e.val64, e.type); | |
873 | return ret; | |
874 | } | |
875 | ||
876 | static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt); | |
877 | ||
878 | static struct intel_vgpu_ppgtt_spt *ppgtt_populate_shadow_page_by_guest_entry( | |
879 | struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we) | |
880 | { | |
881 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; | |
882 | struct intel_vgpu_ppgtt_spt *s = NULL; | |
883 | struct intel_vgpu_guest_page *g; | |
884 | int ret; | |
885 | ||
886 | if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(we->type)))) { | |
887 | ret = -EINVAL; | |
888 | goto fail; | |
889 | } | |
890 | ||
891 | g = intel_vgpu_find_guest_page(vgpu, ops->get_pfn(we)); | |
892 | if (g) { | |
893 | s = guest_page_to_ppgtt_spt(g); | |
894 | ppgtt_get_shadow_page(s); | |
895 | } else { | |
896 | int type = get_next_pt_type(we->type); | |
897 | ||
898 | s = ppgtt_alloc_shadow_page(vgpu, type, ops->get_pfn(we)); | |
899 | if (IS_ERR(s)) { | |
900 | ret = PTR_ERR(s); | |
901 | goto fail; | |
902 | } | |
903 | ||
904 | ret = intel_gvt_hypervisor_set_wp_page(vgpu, &s->guest_page); | |
905 | if (ret) | |
906 | goto fail; | |
907 | ||
908 | ret = ppgtt_populate_shadow_page(s); | |
909 | if (ret) | |
910 | goto fail; | |
911 | ||
912 | trace_spt_change(vgpu->id, "new", s, s->guest_page.gfn, | |
913 | s->shadow_page.type); | |
914 | } | |
915 | return s; | |
916 | fail: | |
917 | gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n", | |
918 | vgpu->id, s, we->val64, we->type); | |
919 | return ERR_PTR(ret); | |
920 | } | |
921 | ||
922 | static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se, | |
923 | struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge) | |
924 | { | |
925 | struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops; | |
926 | ||
927 | se->type = ge->type; | |
928 | se->val64 = ge->val64; | |
929 | ||
930 | ops->set_pfn(se, s->shadow_page.mfn); | |
931 | } | |
932 | ||
933 | static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt *spt) | |
934 | { | |
935 | struct intel_vgpu *vgpu = spt->vgpu; | |
936 | struct intel_vgpu_ppgtt_spt *s; | |
937 | struct intel_gvt_gtt_entry se, ge; | |
938 | unsigned long i; | |
939 | int ret; | |
940 | ||
941 | trace_spt_change(spt->vgpu->id, "born", spt, | |
942 | spt->guest_page.gfn, spt->shadow_page.type); | |
943 | ||
944 | if (gtt_type_is_pte_pt(spt->shadow_page.type)) { | |
945 | for_each_present_guest_entry(spt, &ge, i) { | |
946 | ret = gtt_entry_p2m(vgpu, &ge, &se); | |
947 | if (ret) | |
948 | goto fail; | |
949 | ppgtt_set_shadow_entry(spt, &se, i); | |
950 | } | |
951 | return 0; | |
952 | } | |
953 | ||
954 | for_each_present_guest_entry(spt, &ge, i) { | |
955 | if (!gtt_type_is_pt(get_next_pt_type(ge.type))) { | |
956 | gvt_err("GVT doesn't support pse bit now\n"); | |
957 | ret = -EINVAL; | |
958 | goto fail; | |
959 | } | |
960 | ||
961 | s = ppgtt_populate_shadow_page_by_guest_entry(vgpu, &ge); | |
962 | if (IS_ERR(s)) { | |
963 | ret = PTR_ERR(s); | |
964 | goto fail; | |
965 | } | |
966 | ppgtt_get_shadow_entry(spt, &se, i); | |
967 | ppgtt_generate_shadow_entry(&se, s, &ge); | |
968 | ppgtt_set_shadow_entry(spt, &se, i); | |
969 | } | |
970 | return 0; | |
971 | fail: | |
972 | gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n", | |
973 | vgpu->id, spt, ge.val64, ge.type); | |
974 | return ret; | |
975 | } | |
976 | ||
977 | static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, | |
9baf0920 | 978 | unsigned long index) |
2707e444 ZW |
979 | { |
980 | struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); | |
981 | struct intel_vgpu_shadow_page *sp = &spt->shadow_page; | |
982 | struct intel_vgpu *vgpu = spt->vgpu; | |
983 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; | |
984 | struct intel_gvt_gtt_entry e; | |
985 | int ret; | |
986 | ||
2707e444 | 987 | ppgtt_get_shadow_entry(spt, &e, index); |
9baf0920 BN |
988 | |
989 | trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, e.val64, | |
990 | index); | |
991 | ||
2707e444 ZW |
992 | if (!ops->test_present(&e)) |
993 | return 0; | |
994 | ||
3b6411c2 | 995 | if (ops->get_pfn(&e) == vgpu->gtt.scratch_pt[sp->type].page_mfn) |
2707e444 ZW |
996 | return 0; |
997 | ||
9baf0920 BN |
998 | if (gtt_type_is_pt(get_next_pt_type(e.type))) { |
999 | struct intel_vgpu_ppgtt_spt *s = | |
1000 | ppgtt_find_shadow_page(vgpu, ops->get_pfn(&e)); | |
1001 | if (!s) { | |
2707e444 ZW |
1002 | gvt_err("fail to find guest page\n"); |
1003 | ret = -ENXIO; | |
1004 | goto fail; | |
1005 | } | |
9baf0920 | 1006 | ret = ppgtt_invalidate_shadow_page(s); |
2707e444 ZW |
1007 | if (ret) |
1008 | goto fail; | |
1009 | } | |
3b6411c2 | 1010 | ops->set_pfn(&e, vgpu->gtt.scratch_pt[sp->type].page_mfn); |
2707e444 ZW |
1011 | ppgtt_set_shadow_entry(spt, &e, index); |
1012 | return 0; | |
1013 | fail: | |
1014 | gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d\n", | |
9baf0920 | 1015 | vgpu->id, spt, e.val64, e.type); |
2707e444 ZW |
1016 | return ret; |
1017 | } | |
1018 | ||
1019 | static int ppgtt_handle_guest_entry_add(struct intel_vgpu_guest_page *gpt, | |
1020 | struct intel_gvt_gtt_entry *we, unsigned long index) | |
1021 | { | |
1022 | struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); | |
1023 | struct intel_vgpu_shadow_page *sp = &spt->shadow_page; | |
1024 | struct intel_vgpu *vgpu = spt->vgpu; | |
1025 | struct intel_gvt_gtt_entry m; | |
1026 | struct intel_vgpu_ppgtt_spt *s; | |
1027 | int ret; | |
1028 | ||
1029 | trace_gpt_change(spt->vgpu->id, "add", spt, sp->type, | |
1030 | we->val64, index); | |
1031 | ||
1032 | if (gtt_type_is_pt(get_next_pt_type(we->type))) { | |
1033 | s = ppgtt_populate_shadow_page_by_guest_entry(vgpu, we); | |
1034 | if (IS_ERR(s)) { | |
1035 | ret = PTR_ERR(s); | |
1036 | goto fail; | |
1037 | } | |
1038 | ppgtt_get_shadow_entry(spt, &m, index); | |
1039 | ppgtt_generate_shadow_entry(&m, s, we); | |
1040 | ppgtt_set_shadow_entry(spt, &m, index); | |
1041 | } else { | |
1042 | ret = gtt_entry_p2m(vgpu, we, &m); | |
1043 | if (ret) | |
1044 | goto fail; | |
1045 | ppgtt_set_shadow_entry(spt, &m, index); | |
1046 | } | |
1047 | return 0; | |
1048 | fail: | |
1049 | gvt_err("vgpu%d: fail: spt %p guest entry 0x%llx type %d\n", vgpu->id, | |
1050 | spt, we->val64, we->type); | |
1051 | return ret; | |
1052 | } | |
1053 | ||
1054 | static int sync_oos_page(struct intel_vgpu *vgpu, | |
1055 | struct intel_vgpu_oos_page *oos_page) | |
1056 | { | |
1057 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; | |
1058 | struct intel_gvt *gvt = vgpu->gvt; | |
1059 | struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; | |
1060 | struct intel_vgpu_ppgtt_spt *spt = | |
1061 | guest_page_to_ppgtt_spt(oos_page->guest_page); | |
1062 | struct intel_gvt_gtt_entry old, new, m; | |
1063 | int index; | |
1064 | int ret; | |
1065 | ||
1066 | trace_oos_change(vgpu->id, "sync", oos_page->id, | |
1067 | oos_page->guest_page, spt->guest_page_type); | |
1068 | ||
1069 | old.type = new.type = get_entry_type(spt->guest_page_type); | |
1070 | old.val64 = new.val64 = 0; | |
1071 | ||
1072 | for (index = 0; index < (GTT_PAGE_SIZE >> info->gtt_entry_size_shift); | |
1073 | index++) { | |
1074 | ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu); | |
1075 | ops->get_entry(NULL, &new, index, true, | |
1076 | oos_page->guest_page->gfn << PAGE_SHIFT, vgpu); | |
1077 | ||
1078 | if (old.val64 == new.val64 | |
1079 | && !test_and_clear_bit(index, spt->post_shadow_bitmap)) | |
1080 | continue; | |
1081 | ||
1082 | trace_oos_sync(vgpu->id, oos_page->id, | |
1083 | oos_page->guest_page, spt->guest_page_type, | |
1084 | new.val64, index); | |
1085 | ||
1086 | ret = gtt_entry_p2m(vgpu, &new, &m); | |
1087 | if (ret) | |
1088 | return ret; | |
1089 | ||
1090 | ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu); | |
1091 | ppgtt_set_shadow_entry(spt, &m, index); | |
1092 | } | |
1093 | ||
1094 | oos_page->guest_page->write_cnt = 0; | |
1095 | list_del_init(&spt->post_shadow_list); | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | static int detach_oos_page(struct intel_vgpu *vgpu, | |
1100 | struct intel_vgpu_oos_page *oos_page) | |
1101 | { | |
1102 | struct intel_gvt *gvt = vgpu->gvt; | |
1103 | struct intel_vgpu_ppgtt_spt *spt = | |
1104 | guest_page_to_ppgtt_spt(oos_page->guest_page); | |
1105 | ||
1106 | trace_oos_change(vgpu->id, "detach", oos_page->id, | |
1107 | oos_page->guest_page, spt->guest_page_type); | |
1108 | ||
1109 | oos_page->guest_page->write_cnt = 0; | |
1110 | oos_page->guest_page->oos_page = NULL; | |
1111 | oos_page->guest_page = NULL; | |
1112 | ||
1113 | list_del_init(&oos_page->vm_list); | |
1114 | list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head); | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | static int attach_oos_page(struct intel_vgpu *vgpu, | |
1120 | struct intel_vgpu_oos_page *oos_page, | |
1121 | struct intel_vgpu_guest_page *gpt) | |
1122 | { | |
1123 | struct intel_gvt *gvt = vgpu->gvt; | |
1124 | int ret; | |
1125 | ||
1126 | ret = intel_gvt_hypervisor_read_gpa(vgpu, gpt->gfn << GTT_PAGE_SHIFT, | |
1127 | oos_page->mem, GTT_PAGE_SIZE); | |
1128 | if (ret) | |
1129 | return ret; | |
1130 | ||
1131 | oos_page->guest_page = gpt; | |
1132 | gpt->oos_page = oos_page; | |
1133 | ||
1134 | list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head); | |
1135 | ||
1136 | trace_oos_change(vgpu->id, "attach", gpt->oos_page->id, | |
1137 | gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type); | |
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | static int ppgtt_set_guest_page_sync(struct intel_vgpu *vgpu, | |
1142 | struct intel_vgpu_guest_page *gpt) | |
1143 | { | |
1144 | int ret; | |
1145 | ||
1146 | ret = intel_gvt_hypervisor_set_wp_page(vgpu, gpt); | |
1147 | if (ret) | |
1148 | return ret; | |
1149 | ||
1150 | trace_oos_change(vgpu->id, "set page sync", gpt->oos_page->id, | |
1151 | gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type); | |
1152 | ||
1153 | list_del_init(&gpt->oos_page->vm_list); | |
1154 | return sync_oos_page(vgpu, gpt->oos_page); | |
1155 | } | |
1156 | ||
1157 | static int ppgtt_allocate_oos_page(struct intel_vgpu *vgpu, | |
1158 | struct intel_vgpu_guest_page *gpt) | |
1159 | { | |
1160 | struct intel_gvt *gvt = vgpu->gvt; | |
1161 | struct intel_gvt_gtt *gtt = &gvt->gtt; | |
1162 | struct intel_vgpu_oos_page *oos_page = gpt->oos_page; | |
1163 | int ret; | |
1164 | ||
1165 | WARN(oos_page, "shadow PPGTT page has already has a oos page\n"); | |
1166 | ||
1167 | if (list_empty(>t->oos_page_free_list_head)) { | |
1168 | oos_page = container_of(gtt->oos_page_use_list_head.next, | |
1169 | struct intel_vgpu_oos_page, list); | |
1170 | ret = ppgtt_set_guest_page_sync(vgpu, oos_page->guest_page); | |
1171 | if (ret) | |
1172 | return ret; | |
1173 | ret = detach_oos_page(vgpu, oos_page); | |
1174 | if (ret) | |
1175 | return ret; | |
1176 | } else | |
1177 | oos_page = container_of(gtt->oos_page_free_list_head.next, | |
1178 | struct intel_vgpu_oos_page, list); | |
1179 | return attach_oos_page(vgpu, oos_page, gpt); | |
1180 | } | |
1181 | ||
1182 | static int ppgtt_set_guest_page_oos(struct intel_vgpu *vgpu, | |
1183 | struct intel_vgpu_guest_page *gpt) | |
1184 | { | |
1185 | struct intel_vgpu_oos_page *oos_page = gpt->oos_page; | |
1186 | ||
1187 | if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n")) | |
1188 | return -EINVAL; | |
1189 | ||
1190 | trace_oos_change(vgpu->id, "set page out of sync", gpt->oos_page->id, | |
1191 | gpt, guest_page_to_ppgtt_spt(gpt)->guest_page_type); | |
1192 | ||
1193 | list_add_tail(&oos_page->vm_list, &vgpu->gtt.oos_page_list_head); | |
1194 | return intel_gvt_hypervisor_unset_wp_page(vgpu, gpt); | |
1195 | } | |
1196 | ||
1197 | /** | |
1198 | * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU | |
1199 | * @vgpu: a vGPU | |
1200 | * | |
1201 | * This function is called before submitting a guest workload to host, | |
1202 | * to sync all the out-of-synced shadow for vGPU | |
1203 | * | |
1204 | * Returns: | |
1205 | * Zero on success, negative error code if failed. | |
1206 | */ | |
1207 | int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu) | |
1208 | { | |
1209 | struct list_head *pos, *n; | |
1210 | struct intel_vgpu_oos_page *oos_page; | |
1211 | int ret; | |
1212 | ||
1213 | if (!enable_out_of_sync) | |
1214 | return 0; | |
1215 | ||
1216 | list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) { | |
1217 | oos_page = container_of(pos, | |
1218 | struct intel_vgpu_oos_page, vm_list); | |
1219 | ret = ppgtt_set_guest_page_sync(vgpu, oos_page->guest_page); | |
1220 | if (ret) | |
1221 | return ret; | |
1222 | } | |
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | /* | |
1227 | * The heart of PPGTT shadow page table. | |
1228 | */ | |
1229 | static int ppgtt_handle_guest_write_page_table( | |
1230 | struct intel_vgpu_guest_page *gpt, | |
1231 | struct intel_gvt_gtt_entry *we, unsigned long index) | |
1232 | { | |
1233 | struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); | |
1234 | struct intel_vgpu *vgpu = spt->vgpu; | |
1235 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; | |
2707e444 | 1236 | |
2707e444 | 1237 | int ret; |
9baf0920 | 1238 | int new_present; |
2707e444 | 1239 | |
2707e444 ZW |
1240 | new_present = ops->test_present(we); |
1241 | ||
9baf0920 BN |
1242 | ret = ppgtt_handle_guest_entry_removal(gpt, index); |
1243 | if (ret) | |
1244 | goto fail; | |
2707e444 | 1245 | |
2707e444 ZW |
1246 | if (new_present) { |
1247 | ret = ppgtt_handle_guest_entry_add(gpt, we, index); | |
1248 | if (ret) | |
1249 | goto fail; | |
1250 | } | |
1251 | return 0; | |
1252 | fail: | |
1253 | gvt_err("vgpu%d: fail: shadow page %p guest entry 0x%llx type %d.\n", | |
1254 | vgpu->id, spt, we->val64, we->type); | |
1255 | return ret; | |
1256 | } | |
1257 | ||
1258 | static inline bool can_do_out_of_sync(struct intel_vgpu_guest_page *gpt) | |
1259 | { | |
1260 | return enable_out_of_sync | |
1261 | && gtt_type_is_pte_pt( | |
1262 | guest_page_to_ppgtt_spt(gpt)->guest_page_type) | |
1263 | && gpt->write_cnt >= 2; | |
1264 | } | |
1265 | ||
1266 | static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt, | |
1267 | unsigned long index) | |
1268 | { | |
1269 | set_bit(index, spt->post_shadow_bitmap); | |
1270 | if (!list_empty(&spt->post_shadow_list)) | |
1271 | return; | |
1272 | ||
1273 | list_add_tail(&spt->post_shadow_list, | |
1274 | &spt->vgpu->gtt.post_shadow_list_head); | |
1275 | } | |
1276 | ||
1277 | /** | |
1278 | * intel_vgpu_flush_post_shadow - flush the post shadow transactions | |
1279 | * @vgpu: a vGPU | |
1280 | * | |
1281 | * This function is called before submitting a guest workload to host, | |
1282 | * to flush all the post shadows for a vGPU. | |
1283 | * | |
1284 | * Returns: | |
1285 | * Zero on success, negative error code if failed. | |
1286 | */ | |
1287 | int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu) | |
1288 | { | |
1289 | struct list_head *pos, *n; | |
1290 | struct intel_vgpu_ppgtt_spt *spt; | |
9baf0920 | 1291 | struct intel_gvt_gtt_entry ge; |
2707e444 ZW |
1292 | unsigned long index; |
1293 | int ret; | |
1294 | ||
1295 | list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) { | |
1296 | spt = container_of(pos, struct intel_vgpu_ppgtt_spt, | |
1297 | post_shadow_list); | |
1298 | ||
1299 | for_each_set_bit(index, spt->post_shadow_bitmap, | |
1300 | GTT_ENTRY_NUM_IN_ONE_PAGE) { | |
1301 | ppgtt_get_guest_entry(spt, &ge, index); | |
2707e444 ZW |
1302 | |
1303 | ret = ppgtt_handle_guest_write_page_table( | |
1304 | &spt->guest_page, &ge, index); | |
1305 | if (ret) | |
1306 | return ret; | |
1307 | clear_bit(index, spt->post_shadow_bitmap); | |
1308 | } | |
1309 | list_del_init(&spt->post_shadow_list); | |
1310 | } | |
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | static int ppgtt_handle_guest_write_page_table_bytes(void *gp, | |
1315 | u64 pa, void *p_data, int bytes) | |
1316 | { | |
1317 | struct intel_vgpu_guest_page *gpt = (struct intel_vgpu_guest_page *)gp; | |
1318 | struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); | |
1319 | struct intel_vgpu *vgpu = spt->vgpu; | |
1320 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; | |
1321 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; | |
1322 | struct intel_gvt_gtt_entry we; | |
1323 | unsigned long index; | |
1324 | int ret; | |
1325 | ||
1326 | index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift; | |
1327 | ||
1328 | ppgtt_get_guest_entry(spt, &we, index); | |
2707e444 ZW |
1329 | |
1330 | ops->test_pse(&we); | |
1331 | ||
1332 | if (bytes == info->gtt_entry_size) { | |
1333 | ret = ppgtt_handle_guest_write_page_table(gpt, &we, index); | |
1334 | if (ret) | |
1335 | return ret; | |
1336 | } else { | |
2707e444 | 1337 | if (!test_bit(index, spt->post_shadow_bitmap)) { |
9baf0920 | 1338 | ret = ppgtt_handle_guest_entry_removal(gpt, index); |
2707e444 ZW |
1339 | if (ret) |
1340 | return ret; | |
1341 | } | |
1342 | ||
1343 | ppgtt_set_post_shadow(spt, index); | |
2707e444 ZW |
1344 | } |
1345 | ||
1346 | if (!enable_out_of_sync) | |
1347 | return 0; | |
1348 | ||
1349 | gpt->write_cnt++; | |
1350 | ||
1351 | if (gpt->oos_page) | |
1352 | ops->set_entry(gpt->oos_page->mem, &we, index, | |
1353 | false, 0, vgpu); | |
1354 | ||
1355 | if (can_do_out_of_sync(gpt)) { | |
1356 | if (!gpt->oos_page) | |
1357 | ppgtt_allocate_oos_page(vgpu, gpt); | |
1358 | ||
1359 | ret = ppgtt_set_guest_page_oos(vgpu, gpt); | |
1360 | if (ret < 0) | |
1361 | return ret; | |
1362 | } | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | /* | |
1367 | * mm page table allocation policy for bdw+ | |
1368 | * - for ggtt, only virtual page table will be allocated. | |
1369 | * - for ppgtt, dedicated virtual/shadow page table will be allocated. | |
1370 | */ | |
1371 | static int gen8_mm_alloc_page_table(struct intel_vgpu_mm *mm) | |
1372 | { | |
1373 | struct intel_vgpu *vgpu = mm->vgpu; | |
1374 | struct intel_gvt *gvt = vgpu->gvt; | |
1375 | const struct intel_gvt_device_info *info = &gvt->device_info; | |
1376 | void *mem; | |
1377 | ||
1378 | if (mm->type == INTEL_GVT_MM_PPGTT) { | |
1379 | mm->page_table_entry_cnt = 4; | |
1380 | mm->page_table_entry_size = mm->page_table_entry_cnt * | |
1381 | info->gtt_entry_size; | |
1382 | mem = kzalloc(mm->has_shadow_page_table ? | |
1383 | mm->page_table_entry_size * 2 | |
9631739f | 1384 | : mm->page_table_entry_size, GFP_KERNEL); |
2707e444 ZW |
1385 | if (!mem) |
1386 | return -ENOMEM; | |
1387 | mm->virtual_page_table = mem; | |
1388 | if (!mm->has_shadow_page_table) | |
1389 | return 0; | |
1390 | mm->shadow_page_table = mem + mm->page_table_entry_size; | |
1391 | } else if (mm->type == INTEL_GVT_MM_GGTT) { | |
1392 | mm->page_table_entry_cnt = | |
1393 | (gvt_ggtt_gm_sz(gvt) >> GTT_PAGE_SHIFT); | |
1394 | mm->page_table_entry_size = mm->page_table_entry_cnt * | |
1395 | info->gtt_entry_size; | |
1396 | mem = vzalloc(mm->page_table_entry_size); | |
1397 | if (!mem) | |
1398 | return -ENOMEM; | |
1399 | mm->virtual_page_table = mem; | |
1400 | } | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | static void gen8_mm_free_page_table(struct intel_vgpu_mm *mm) | |
1405 | { | |
1406 | if (mm->type == INTEL_GVT_MM_PPGTT) { | |
1407 | kfree(mm->virtual_page_table); | |
1408 | } else if (mm->type == INTEL_GVT_MM_GGTT) { | |
1409 | if (mm->virtual_page_table) | |
1410 | vfree(mm->virtual_page_table); | |
1411 | } | |
1412 | mm->virtual_page_table = mm->shadow_page_table = NULL; | |
1413 | } | |
1414 | ||
1415 | static void invalidate_mm(struct intel_vgpu_mm *mm) | |
1416 | { | |
1417 | struct intel_vgpu *vgpu = mm->vgpu; | |
1418 | struct intel_gvt *gvt = vgpu->gvt; | |
1419 | struct intel_gvt_gtt *gtt = &gvt->gtt; | |
1420 | struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops; | |
1421 | struct intel_gvt_gtt_entry se; | |
1422 | int i; | |
1423 | ||
1424 | if (WARN_ON(!mm->has_shadow_page_table || !mm->shadowed)) | |
1425 | return; | |
1426 | ||
1427 | for (i = 0; i < mm->page_table_entry_cnt; i++) { | |
1428 | ppgtt_get_shadow_root_entry(mm, &se, i); | |
1429 | if (!ops->test_present(&se)) | |
1430 | continue; | |
1431 | ppgtt_invalidate_shadow_page_by_shadow_entry( | |
1432 | vgpu, &se); | |
1433 | se.val64 = 0; | |
1434 | ppgtt_set_shadow_root_entry(mm, &se, i); | |
1435 | ||
1436 | trace_gpt_change(vgpu->id, "destroy root pointer", | |
1437 | NULL, se.type, se.val64, i); | |
1438 | } | |
1439 | mm->shadowed = false; | |
1440 | } | |
1441 | ||
1442 | /** | |
1443 | * intel_vgpu_destroy_mm - destroy a mm object | |
1444 | * @mm: a kref object | |
1445 | * | |
1446 | * This function is used to destroy a mm object for vGPU | |
1447 | * | |
1448 | */ | |
1449 | void intel_vgpu_destroy_mm(struct kref *mm_ref) | |
1450 | { | |
1451 | struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref); | |
1452 | struct intel_vgpu *vgpu = mm->vgpu; | |
1453 | struct intel_gvt *gvt = vgpu->gvt; | |
1454 | struct intel_gvt_gtt *gtt = &gvt->gtt; | |
1455 | ||
1456 | if (!mm->initialized) | |
1457 | goto out; | |
1458 | ||
1459 | list_del(&mm->list); | |
1460 | list_del(&mm->lru_list); | |
1461 | ||
1462 | if (mm->has_shadow_page_table) | |
1463 | invalidate_mm(mm); | |
1464 | ||
1465 | gtt->mm_free_page_table(mm); | |
1466 | out: | |
1467 | kfree(mm); | |
1468 | } | |
1469 | ||
1470 | static int shadow_mm(struct intel_vgpu_mm *mm) | |
1471 | { | |
1472 | struct intel_vgpu *vgpu = mm->vgpu; | |
1473 | struct intel_gvt *gvt = vgpu->gvt; | |
1474 | struct intel_gvt_gtt *gtt = &gvt->gtt; | |
1475 | struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops; | |
1476 | struct intel_vgpu_ppgtt_spt *spt; | |
1477 | struct intel_gvt_gtt_entry ge, se; | |
1478 | int i; | |
1479 | int ret; | |
1480 | ||
1481 | if (WARN_ON(!mm->has_shadow_page_table || mm->shadowed)) | |
1482 | return 0; | |
1483 | ||
1484 | mm->shadowed = true; | |
1485 | ||
1486 | for (i = 0; i < mm->page_table_entry_cnt; i++) { | |
1487 | ppgtt_get_guest_root_entry(mm, &ge, i); | |
1488 | if (!ops->test_present(&ge)) | |
1489 | continue; | |
1490 | ||
1491 | trace_gpt_change(vgpu->id, __func__, NULL, | |
1492 | ge.type, ge.val64, i); | |
1493 | ||
1494 | spt = ppgtt_populate_shadow_page_by_guest_entry(vgpu, &ge); | |
1495 | if (IS_ERR(spt)) { | |
1496 | gvt_err("fail to populate guest root pointer\n"); | |
1497 | ret = PTR_ERR(spt); | |
1498 | goto fail; | |
1499 | } | |
1500 | ppgtt_generate_shadow_entry(&se, spt, &ge); | |
1501 | ppgtt_set_shadow_root_entry(mm, &se, i); | |
1502 | ||
1503 | trace_gpt_change(vgpu->id, "populate root pointer", | |
1504 | NULL, se.type, se.val64, i); | |
1505 | } | |
1506 | return 0; | |
1507 | fail: | |
1508 | invalidate_mm(mm); | |
1509 | return ret; | |
1510 | } | |
1511 | ||
1512 | /** | |
1513 | * intel_vgpu_create_mm - create a mm object for a vGPU | |
1514 | * @vgpu: a vGPU | |
1515 | * @mm_type: mm object type, should be PPGTT or GGTT | |
1516 | * @virtual_page_table: page table root pointers. Could be NULL if user wants | |
1517 | * to populate shadow later. | |
1518 | * @page_table_level: describe the page table level of the mm object | |
1519 | * @pde_base_index: pde root pointer base in GGTT MMIO. | |
1520 | * | |
1521 | * This function is used to create a mm object for a vGPU. | |
1522 | * | |
1523 | * Returns: | |
1524 | * Zero on success, negative error code in pointer if failed. | |
1525 | */ | |
1526 | struct intel_vgpu_mm *intel_vgpu_create_mm(struct intel_vgpu *vgpu, | |
1527 | int mm_type, void *virtual_page_table, int page_table_level, | |
1528 | u32 pde_base_index) | |
1529 | { | |
1530 | struct intel_gvt *gvt = vgpu->gvt; | |
1531 | struct intel_gvt_gtt *gtt = &gvt->gtt; | |
1532 | struct intel_vgpu_mm *mm; | |
1533 | int ret; | |
1534 | ||
9631739f | 1535 | mm = kzalloc(sizeof(*mm), GFP_KERNEL); |
2707e444 ZW |
1536 | if (!mm) { |
1537 | ret = -ENOMEM; | |
1538 | goto fail; | |
1539 | } | |
1540 | ||
1541 | mm->type = mm_type; | |
1542 | ||
1543 | if (page_table_level == 1) | |
1544 | mm->page_table_entry_type = GTT_TYPE_GGTT_PTE; | |
1545 | else if (page_table_level == 3) | |
1546 | mm->page_table_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; | |
1547 | else if (page_table_level == 4) | |
1548 | mm->page_table_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; | |
1549 | else { | |
1550 | WARN_ON(1); | |
1551 | ret = -EINVAL; | |
1552 | goto fail; | |
1553 | } | |
1554 | ||
1555 | mm->page_table_level = page_table_level; | |
1556 | mm->pde_base_index = pde_base_index; | |
1557 | ||
1558 | mm->vgpu = vgpu; | |
1559 | mm->has_shadow_page_table = !!(mm_type == INTEL_GVT_MM_PPGTT); | |
1560 | ||
1561 | kref_init(&mm->ref); | |
1562 | atomic_set(&mm->pincount, 0); | |
1563 | INIT_LIST_HEAD(&mm->list); | |
1564 | INIT_LIST_HEAD(&mm->lru_list); | |
1565 | list_add_tail(&mm->list, &vgpu->gtt.mm_list_head); | |
1566 | ||
1567 | ret = gtt->mm_alloc_page_table(mm); | |
1568 | if (ret) { | |
1569 | gvt_err("fail to allocate page table for mm\n"); | |
1570 | goto fail; | |
1571 | } | |
1572 | ||
1573 | mm->initialized = true; | |
1574 | ||
1575 | if (virtual_page_table) | |
1576 | memcpy(mm->virtual_page_table, virtual_page_table, | |
1577 | mm->page_table_entry_size); | |
1578 | ||
1579 | if (mm->has_shadow_page_table) { | |
1580 | ret = shadow_mm(mm); | |
1581 | if (ret) | |
1582 | goto fail; | |
1583 | list_add_tail(&mm->lru_list, &gvt->gtt.mm_lru_list_head); | |
1584 | } | |
1585 | return mm; | |
1586 | fail: | |
1587 | gvt_err("fail to create mm\n"); | |
1588 | if (mm) | |
1589 | intel_gvt_mm_unreference(mm); | |
1590 | return ERR_PTR(ret); | |
1591 | } | |
1592 | ||
1593 | /** | |
1594 | * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object | |
1595 | * @mm: a vGPU mm object | |
1596 | * | |
1597 | * This function is called when user doesn't want to use a vGPU mm object | |
1598 | */ | |
1599 | void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm) | |
1600 | { | |
1601 | if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT)) | |
1602 | return; | |
1603 | ||
1604 | atomic_dec(&mm->pincount); | |
1605 | } | |
1606 | ||
1607 | /** | |
1608 | * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object | |
1609 | * @vgpu: a vGPU | |
1610 | * | |
1611 | * This function is called when user wants to use a vGPU mm object. If this | |
1612 | * mm object hasn't been shadowed yet, the shadow will be populated at this | |
1613 | * time. | |
1614 | * | |
1615 | * Returns: | |
1616 | * Zero on success, negative error code if failed. | |
1617 | */ | |
1618 | int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm) | |
1619 | { | |
1620 | int ret; | |
1621 | ||
1622 | if (WARN_ON(mm->type != INTEL_GVT_MM_PPGTT)) | |
1623 | return 0; | |
1624 | ||
1625 | atomic_inc(&mm->pincount); | |
1626 | ||
1627 | if (!mm->shadowed) { | |
1628 | ret = shadow_mm(mm); | |
1629 | if (ret) | |
1630 | return ret; | |
1631 | } | |
1632 | ||
1633 | list_del_init(&mm->lru_list); | |
1634 | list_add_tail(&mm->lru_list, &mm->vgpu->gvt->gtt.mm_lru_list_head); | |
1635 | return 0; | |
1636 | } | |
1637 | ||
1638 | static int reclaim_one_mm(struct intel_gvt *gvt) | |
1639 | { | |
1640 | struct intel_vgpu_mm *mm; | |
1641 | struct list_head *pos, *n; | |
1642 | ||
1643 | list_for_each_safe(pos, n, &gvt->gtt.mm_lru_list_head) { | |
1644 | mm = container_of(pos, struct intel_vgpu_mm, lru_list); | |
1645 | ||
1646 | if (mm->type != INTEL_GVT_MM_PPGTT) | |
1647 | continue; | |
1648 | if (atomic_read(&mm->pincount)) | |
1649 | continue; | |
1650 | ||
1651 | list_del_init(&mm->lru_list); | |
1652 | invalidate_mm(mm); | |
1653 | return 1; | |
1654 | } | |
1655 | return 0; | |
1656 | } | |
1657 | ||
1658 | /* | |
1659 | * GMA translation APIs. | |
1660 | */ | |
1661 | static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm, | |
1662 | struct intel_gvt_gtt_entry *e, unsigned long index, bool guest) | |
1663 | { | |
1664 | struct intel_vgpu *vgpu = mm->vgpu; | |
1665 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; | |
1666 | struct intel_vgpu_ppgtt_spt *s; | |
1667 | ||
1668 | if (WARN_ON(!mm->has_shadow_page_table)) | |
1669 | return -EINVAL; | |
1670 | ||
1671 | s = ppgtt_find_shadow_page(vgpu, ops->get_pfn(e)); | |
1672 | if (!s) | |
1673 | return -ENXIO; | |
1674 | ||
1675 | if (!guest) | |
1676 | ppgtt_get_shadow_entry(s, e, index); | |
1677 | else | |
1678 | ppgtt_get_guest_entry(s, e, index); | |
1679 | return 0; | |
1680 | } | |
1681 | ||
1682 | /** | |
1683 | * intel_vgpu_gma_to_gpa - translate a gma to GPA | |
1684 | * @mm: mm object. could be a PPGTT or GGTT mm object | |
1685 | * @gma: graphics memory address in this mm object | |
1686 | * | |
1687 | * This function is used to translate a graphics memory address in specific | |
1688 | * graphics memory space to guest physical address. | |
1689 | * | |
1690 | * Returns: | |
1691 | * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed. | |
1692 | */ | |
1693 | unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) | |
1694 | { | |
1695 | struct intel_vgpu *vgpu = mm->vgpu; | |
1696 | struct intel_gvt *gvt = vgpu->gvt; | |
1697 | struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops; | |
1698 | struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops; | |
1699 | unsigned long gpa = INTEL_GVT_INVALID_ADDR; | |
1700 | unsigned long gma_index[4]; | |
1701 | struct intel_gvt_gtt_entry e; | |
1702 | int i, index; | |
1703 | int ret; | |
1704 | ||
1705 | if (mm->type != INTEL_GVT_MM_GGTT && mm->type != INTEL_GVT_MM_PPGTT) | |
1706 | return INTEL_GVT_INVALID_ADDR; | |
1707 | ||
1708 | if (mm->type == INTEL_GVT_MM_GGTT) { | |
1709 | if (!vgpu_gmadr_is_valid(vgpu, gma)) | |
1710 | goto err; | |
1711 | ||
1712 | ggtt_get_guest_entry(mm, &e, | |
1713 | gma_ops->gma_to_ggtt_pte_index(gma)); | |
1714 | gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT) | |
1715 | + (gma & ~GTT_PAGE_MASK); | |
1716 | ||
1717 | trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa); | |
1718 | return gpa; | |
1719 | } | |
1720 | ||
1721 | switch (mm->page_table_level) { | |
1722 | case 4: | |
1723 | ppgtt_get_shadow_root_entry(mm, &e, 0); | |
1724 | gma_index[0] = gma_ops->gma_to_pml4_index(gma); | |
1725 | gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma); | |
1726 | gma_index[2] = gma_ops->gma_to_pde_index(gma); | |
1727 | gma_index[3] = gma_ops->gma_to_pte_index(gma); | |
1728 | index = 4; | |
1729 | break; | |
1730 | case 3: | |
1731 | ppgtt_get_shadow_root_entry(mm, &e, | |
1732 | gma_ops->gma_to_l3_pdp_index(gma)); | |
1733 | gma_index[0] = gma_ops->gma_to_pde_index(gma); | |
1734 | gma_index[1] = gma_ops->gma_to_pte_index(gma); | |
1735 | index = 2; | |
1736 | break; | |
1737 | case 2: | |
1738 | ppgtt_get_shadow_root_entry(mm, &e, | |
1739 | gma_ops->gma_to_pde_index(gma)); | |
1740 | gma_index[0] = gma_ops->gma_to_pte_index(gma); | |
1741 | index = 1; | |
1742 | break; | |
1743 | default: | |
1744 | WARN_ON(1); | |
1745 | goto err; | |
1746 | } | |
1747 | ||
1748 | /* walk into the shadow page table and get gpa from guest entry */ | |
1749 | for (i = 0; i < index; i++) { | |
1750 | ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i], | |
1751 | (i == index - 1)); | |
1752 | if (ret) | |
1753 | goto err; | |
1754 | } | |
1755 | ||
1756 | gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT) | |
1757 | + (gma & ~GTT_PAGE_MASK); | |
1758 | ||
1759 | trace_gma_translate(vgpu->id, "ppgtt", 0, | |
1760 | mm->page_table_level, gma, gpa); | |
1761 | return gpa; | |
1762 | err: | |
1763 | gvt_err("invalid mm type: %d gma %lx\n", mm->type, gma); | |
1764 | return INTEL_GVT_INVALID_ADDR; | |
1765 | } | |
1766 | ||
1767 | static int emulate_gtt_mmio_read(struct intel_vgpu *vgpu, | |
1768 | unsigned int off, void *p_data, unsigned int bytes) | |
1769 | { | |
1770 | struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm; | |
1771 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; | |
1772 | unsigned long index = off >> info->gtt_entry_size_shift; | |
1773 | struct intel_gvt_gtt_entry e; | |
1774 | ||
1775 | if (bytes != 4 && bytes != 8) | |
1776 | return -EINVAL; | |
1777 | ||
1778 | ggtt_get_guest_entry(ggtt_mm, &e, index); | |
1779 | memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)), | |
1780 | bytes); | |
1781 | return 0; | |
1782 | } | |
1783 | ||
1784 | /** | |
1785 | * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read | |
1786 | * @vgpu: a vGPU | |
1787 | * @off: register offset | |
1788 | * @p_data: data will be returned to guest | |
1789 | * @bytes: data length | |
1790 | * | |
1791 | * This function is used to emulate the GTT MMIO register read | |
1792 | * | |
1793 | * Returns: | |
1794 | * Zero on success, error code if failed. | |
1795 | */ | |
1796 | int intel_vgpu_emulate_gtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off, | |
1797 | void *p_data, unsigned int bytes) | |
1798 | { | |
1799 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; | |
1800 | int ret; | |
1801 | ||
1802 | if (bytes != 4 && bytes != 8) | |
1803 | return -EINVAL; | |
1804 | ||
1805 | off -= info->gtt_start_offset; | |
1806 | ret = emulate_gtt_mmio_read(vgpu, off, p_data, bytes); | |
1807 | return ret; | |
1808 | } | |
1809 | ||
1810 | static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, | |
1811 | void *p_data, unsigned int bytes) | |
1812 | { | |
1813 | struct intel_gvt *gvt = vgpu->gvt; | |
1814 | const struct intel_gvt_device_info *info = &gvt->device_info; | |
1815 | struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm; | |
1816 | struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; | |
1817 | unsigned long g_gtt_index = off >> info->gtt_entry_size_shift; | |
1818 | unsigned long gma; | |
1819 | struct intel_gvt_gtt_entry e, m; | |
1820 | int ret; | |
1821 | ||
1822 | if (bytes != 4 && bytes != 8) | |
1823 | return -EINVAL; | |
1824 | ||
1825 | gma = g_gtt_index << GTT_PAGE_SHIFT; | |
1826 | ||
1827 | /* the VM may configure the whole GM space when ballooning is used */ | |
1828 | if (WARN_ONCE(!vgpu_gmadr_is_valid(vgpu, gma), | |
1829 | "vgpu%d: found oob ggtt write, offset %x\n", | |
1830 | vgpu->id, off)) { | |
1831 | return 0; | |
1832 | } | |
1833 | ||
1834 | ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index); | |
1835 | ||
1836 | memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data, | |
1837 | bytes); | |
1838 | ||
1839 | if (ops->test_present(&e)) { | |
1840 | ret = gtt_entry_p2m(vgpu, &e, &m); | |
1841 | if (ret) { | |
1842 | gvt_err("vgpu%d: fail to translate guest gtt entry\n", | |
1843 | vgpu->id); | |
1844 | return ret; | |
1845 | } | |
1846 | } else { | |
1847 | m = e; | |
1848 | m.val64 = 0; | |
1849 | } | |
1850 | ||
1851 | ggtt_set_shadow_entry(ggtt_mm, &m, g_gtt_index); | |
1852 | ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index); | |
1853 | return 0; | |
1854 | } | |
1855 | ||
1856 | /* | |
1857 | * intel_vgpu_emulate_gtt_mmio_write - emulate GTT MMIO register write | |
1858 | * @vgpu: a vGPU | |
1859 | * @off: register offset | |
1860 | * @p_data: data from guest write | |
1861 | * @bytes: data length | |
1862 | * | |
1863 | * This function is used to emulate the GTT MMIO register write | |
1864 | * | |
1865 | * Returns: | |
1866 | * Zero on success, error code if failed. | |
1867 | */ | |
1868 | int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, | |
1869 | void *p_data, unsigned int bytes) | |
1870 | { | |
1871 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; | |
1872 | int ret; | |
1873 | ||
1874 | if (bytes != 4 && bytes != 8) | |
1875 | return -EINVAL; | |
1876 | ||
1877 | off -= info->gtt_start_offset; | |
1878 | ret = emulate_gtt_mmio_write(vgpu, off, p_data, bytes); | |
1879 | return ret; | |
1880 | } | |
1881 | ||
3b6411c2 PG |
1882 | static int alloc_scratch_pages(struct intel_vgpu *vgpu, |
1883 | intel_gvt_gtt_type_t type) | |
2707e444 ZW |
1884 | { |
1885 | struct intel_vgpu_gtt *gtt = &vgpu->gtt; | |
3b6411c2 PG |
1886 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; |
1887 | int page_entry_num = GTT_PAGE_SIZE >> | |
1888 | vgpu->gvt->device_info.gtt_entry_size_shift; | |
9631739f | 1889 | void *scratch_pt; |
3b6411c2 | 1890 | int i; |
5de6bd4c CD |
1891 | struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; |
1892 | dma_addr_t daddr; | |
2707e444 | 1893 | |
3b6411c2 PG |
1894 | if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX)) |
1895 | return -EINVAL; | |
1896 | ||
9631739f | 1897 | scratch_pt = (void *)get_zeroed_page(GFP_KERNEL); |
3b6411c2 PG |
1898 | if (!scratch_pt) { |
1899 | gvt_err("fail to allocate scratch page\n"); | |
2707e444 ZW |
1900 | return -ENOMEM; |
1901 | } | |
1902 | ||
5de6bd4c CD |
1903 | daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0, |
1904 | 4096, PCI_DMA_BIDIRECTIONAL); | |
1905 | if (dma_mapping_error(dev, daddr)) { | |
1906 | gvt_err("fail to dmamap scratch_pt\n"); | |
1907 | __free_page(virt_to_page(scratch_pt)); | |
1908 | return -ENOMEM; | |
3b6411c2 | 1909 | } |
5de6bd4c CD |
1910 | gtt->scratch_pt[type].page_mfn = |
1911 | (unsigned long)(daddr >> GTT_PAGE_SHIFT); | |
9631739f | 1912 | gtt->scratch_pt[type].page = virt_to_page(scratch_pt); |
3b6411c2 | 1913 | gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n", |
5de6bd4c | 1914 | vgpu->id, type, gtt->scratch_pt[type].page_mfn); |
3b6411c2 PG |
1915 | |
1916 | /* Build the tree by full filled the scratch pt with the entries which | |
1917 | * point to the next level scratch pt or scratch page. The | |
1918 | * scratch_pt[type] indicate the scratch pt/scratch page used by the | |
1919 | * 'type' pt. | |
1920 | * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by | |
9631739f | 1921 | * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self |
3b6411c2 PG |
1922 | * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn. |
1923 | */ | |
1924 | if (type > GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX) { | |
1925 | struct intel_gvt_gtt_entry se; | |
1926 | ||
1927 | memset(&se, 0, sizeof(struct intel_gvt_gtt_entry)); | |
1928 | se.type = get_entry_type(type - 1); | |
1929 | ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn); | |
1930 | ||
1931 | /* The entry parameters like present/writeable/cache type | |
1932 | * set to the same as i915's scratch page tree. | |
1933 | */ | |
1934 | se.val64 |= _PAGE_PRESENT | _PAGE_RW; | |
1935 | if (type == GTT_TYPE_PPGTT_PDE_PT) | |
1936 | se.val64 |= PPAT_CACHED_INDEX; | |
1937 | ||
1938 | for (i = 0; i < page_entry_num; i++) | |
9631739f | 1939 | ops->set_entry(scratch_pt, &se, i, false, 0, vgpu); |
3b6411c2 PG |
1940 | } |
1941 | ||
3b6411c2 PG |
1942 | return 0; |
1943 | } | |
2707e444 | 1944 | |
3b6411c2 PG |
1945 | static int release_scratch_page_tree(struct intel_vgpu *vgpu) |
1946 | { | |
1947 | int i; | |
5de6bd4c CD |
1948 | struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev; |
1949 | dma_addr_t daddr; | |
3b6411c2 PG |
1950 | |
1951 | for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) { | |
1952 | if (vgpu->gtt.scratch_pt[i].page != NULL) { | |
5de6bd4c CD |
1953 | daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn << |
1954 | GTT_PAGE_SHIFT); | |
1955 | dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL); | |
3b6411c2 PG |
1956 | __free_page(vgpu->gtt.scratch_pt[i].page); |
1957 | vgpu->gtt.scratch_pt[i].page = NULL; | |
1958 | vgpu->gtt.scratch_pt[i].page_mfn = 0; | |
1959 | } | |
2707e444 ZW |
1960 | } |
1961 | ||
2707e444 ZW |
1962 | return 0; |
1963 | } | |
1964 | ||
3b6411c2 | 1965 | static int create_scratch_page_tree(struct intel_vgpu *vgpu) |
2707e444 | 1966 | { |
3b6411c2 PG |
1967 | int i, ret; |
1968 | ||
1969 | for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) { | |
1970 | ret = alloc_scratch_pages(vgpu, i); | |
1971 | if (ret) | |
1972 | goto err; | |
2707e444 | 1973 | } |
3b6411c2 PG |
1974 | |
1975 | return 0; | |
1976 | ||
1977 | err: | |
1978 | release_scratch_page_tree(vgpu); | |
1979 | return ret; | |
2707e444 ZW |
1980 | } |
1981 | ||
1982 | /** | |
1983 | * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization | |
1984 | * @vgpu: a vGPU | |
1985 | * | |
1986 | * This function is used to initialize per-vGPU graphics memory virtualization | |
1987 | * components. | |
1988 | * | |
1989 | * Returns: | |
1990 | * Zero on success, error code if failed. | |
1991 | */ | |
1992 | int intel_vgpu_init_gtt(struct intel_vgpu *vgpu) | |
1993 | { | |
1994 | struct intel_vgpu_gtt *gtt = &vgpu->gtt; | |
1995 | struct intel_vgpu_mm *ggtt_mm; | |
1996 | ||
1997 | hash_init(gtt->guest_page_hash_table); | |
1998 | hash_init(gtt->shadow_page_hash_table); | |
1999 | ||
2000 | INIT_LIST_HEAD(>t->mm_list_head); | |
2001 | INIT_LIST_HEAD(>t->oos_page_list_head); | |
2002 | INIT_LIST_HEAD(>t->post_shadow_list_head); | |
2003 | ||
d650ac06 PG |
2004 | intel_vgpu_reset_ggtt(vgpu); |
2005 | ||
2707e444 ZW |
2006 | ggtt_mm = intel_vgpu_create_mm(vgpu, INTEL_GVT_MM_GGTT, |
2007 | NULL, 1, 0); | |
2008 | if (IS_ERR(ggtt_mm)) { | |
2009 | gvt_err("fail to create mm for ggtt.\n"); | |
2010 | return PTR_ERR(ggtt_mm); | |
2011 | } | |
2012 | ||
2013 | gtt->ggtt_mm = ggtt_mm; | |
2014 | ||
3b6411c2 | 2015 | return create_scratch_page_tree(vgpu); |
2707e444 ZW |
2016 | } |
2017 | ||
2018 | /** | |
2019 | * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization | |
2020 | * @vgpu: a vGPU | |
2021 | * | |
2022 | * This function is used to clean up per-vGPU graphics memory virtualization | |
2023 | * components. | |
2024 | * | |
2025 | * Returns: | |
2026 | * Zero on success, error code if failed. | |
2027 | */ | |
2028 | void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu) | |
2029 | { | |
2030 | struct list_head *pos, *n; | |
2031 | struct intel_vgpu_mm *mm; | |
2032 | ||
2033 | ppgtt_free_all_shadow_page(vgpu); | |
3b6411c2 | 2034 | release_scratch_page_tree(vgpu); |
2707e444 ZW |
2035 | |
2036 | list_for_each_safe(pos, n, &vgpu->gtt.mm_list_head) { | |
2037 | mm = container_of(pos, struct intel_vgpu_mm, list); | |
2038 | vgpu->gvt->gtt.mm_free_page_table(mm); | |
2039 | list_del(&mm->list); | |
2040 | list_del(&mm->lru_list); | |
2041 | kfree(mm); | |
2042 | } | |
2043 | } | |
2044 | ||
2045 | static void clean_spt_oos(struct intel_gvt *gvt) | |
2046 | { | |
2047 | struct intel_gvt_gtt *gtt = &gvt->gtt; | |
2048 | struct list_head *pos, *n; | |
2049 | struct intel_vgpu_oos_page *oos_page; | |
2050 | ||
2051 | WARN(!list_empty(>t->oos_page_use_list_head), | |
2052 | "someone is still using oos page\n"); | |
2053 | ||
2054 | list_for_each_safe(pos, n, >t->oos_page_free_list_head) { | |
2055 | oos_page = container_of(pos, struct intel_vgpu_oos_page, list); | |
2056 | list_del(&oos_page->list); | |
2057 | kfree(oos_page); | |
2058 | } | |
2059 | } | |
2060 | ||
2061 | static int setup_spt_oos(struct intel_gvt *gvt) | |
2062 | { | |
2063 | struct intel_gvt_gtt *gtt = &gvt->gtt; | |
2064 | struct intel_vgpu_oos_page *oos_page; | |
2065 | int i; | |
2066 | int ret; | |
2067 | ||
2068 | INIT_LIST_HEAD(>t->oos_page_free_list_head); | |
2069 | INIT_LIST_HEAD(>t->oos_page_use_list_head); | |
2070 | ||
2071 | for (i = 0; i < preallocated_oos_pages; i++) { | |
2072 | oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL); | |
2073 | if (!oos_page) { | |
2074 | gvt_err("fail to pre-allocate oos page\n"); | |
2075 | ret = -ENOMEM; | |
2076 | goto fail; | |
2077 | } | |
2078 | ||
2079 | INIT_LIST_HEAD(&oos_page->list); | |
2080 | INIT_LIST_HEAD(&oos_page->vm_list); | |
2081 | oos_page->id = i; | |
2082 | list_add_tail(&oos_page->list, >t->oos_page_free_list_head); | |
2083 | } | |
2084 | ||
2085 | gvt_dbg_mm("%d oos pages preallocated\n", i); | |
2086 | ||
2087 | return 0; | |
2088 | fail: | |
2089 | clean_spt_oos(gvt); | |
2090 | return ret; | |
2091 | } | |
2092 | ||
2093 | /** | |
2094 | * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object | |
2095 | * @vgpu: a vGPU | |
2096 | * @page_table_level: PPGTT page table level | |
2097 | * @root_entry: PPGTT page table root pointers | |
2098 | * | |
2099 | * This function is used to find a PPGTT mm object from mm object pool | |
2100 | * | |
2101 | * Returns: | |
2102 | * pointer to mm object on success, NULL if failed. | |
2103 | */ | |
2104 | struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu, | |
2105 | int page_table_level, void *root_entry) | |
2106 | { | |
2107 | struct list_head *pos; | |
2108 | struct intel_vgpu_mm *mm; | |
2109 | u64 *src, *dst; | |
2110 | ||
2111 | list_for_each(pos, &vgpu->gtt.mm_list_head) { | |
2112 | mm = container_of(pos, struct intel_vgpu_mm, list); | |
2113 | if (mm->type != INTEL_GVT_MM_PPGTT) | |
2114 | continue; | |
2115 | ||
2116 | if (mm->page_table_level != page_table_level) | |
2117 | continue; | |
2118 | ||
2119 | src = root_entry; | |
2120 | dst = mm->virtual_page_table; | |
2121 | ||
2122 | if (page_table_level == 3) { | |
2123 | if (src[0] == dst[0] | |
2124 | && src[1] == dst[1] | |
2125 | && src[2] == dst[2] | |
2126 | && src[3] == dst[3]) | |
2127 | return mm; | |
2128 | } else { | |
2129 | if (src[0] == dst[0]) | |
2130 | return mm; | |
2131 | } | |
2132 | } | |
2133 | return NULL; | |
2134 | } | |
2135 | ||
2136 | /** | |
2137 | * intel_vgpu_g2v_create_ppgtt_mm - create a PPGTT mm object from | |
2138 | * g2v notification | |
2139 | * @vgpu: a vGPU | |
2140 | * @page_table_level: PPGTT page table level | |
2141 | * | |
2142 | * This function is used to create a PPGTT mm object from a guest to GVT-g | |
2143 | * notification. | |
2144 | * | |
2145 | * Returns: | |
2146 | * Zero on success, negative error code if failed. | |
2147 | */ | |
2148 | int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu, | |
2149 | int page_table_level) | |
2150 | { | |
2151 | u64 *pdp = (u64 *)&vgpu_vreg64(vgpu, vgtif_reg(pdp[0])); | |
2152 | struct intel_vgpu_mm *mm; | |
2153 | ||
2154 | if (WARN_ON((page_table_level != 4) && (page_table_level != 3))) | |
2155 | return -EINVAL; | |
2156 | ||
2157 | mm = intel_vgpu_find_ppgtt_mm(vgpu, page_table_level, pdp); | |
2158 | if (mm) { | |
2159 | intel_gvt_mm_reference(mm); | |
2160 | } else { | |
2161 | mm = intel_vgpu_create_mm(vgpu, INTEL_GVT_MM_PPGTT, | |
2162 | pdp, page_table_level, 0); | |
2163 | if (IS_ERR(mm)) { | |
2164 | gvt_err("fail to create mm\n"); | |
2165 | return PTR_ERR(mm); | |
2166 | } | |
2167 | } | |
2168 | return 0; | |
2169 | } | |
2170 | ||
2171 | /** | |
2172 | * intel_vgpu_g2v_destroy_ppgtt_mm - destroy a PPGTT mm object from | |
2173 | * g2v notification | |
2174 | * @vgpu: a vGPU | |
2175 | * @page_table_level: PPGTT page table level | |
2176 | * | |
2177 | * This function is used to create a PPGTT mm object from a guest to GVT-g | |
2178 | * notification. | |
2179 | * | |
2180 | * Returns: | |
2181 | * Zero on success, negative error code if failed. | |
2182 | */ | |
2183 | int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu *vgpu, | |
2184 | int page_table_level) | |
2185 | { | |
2186 | u64 *pdp = (u64 *)&vgpu_vreg64(vgpu, vgtif_reg(pdp[0])); | |
2187 | struct intel_vgpu_mm *mm; | |
2188 | ||
2189 | if (WARN_ON((page_table_level != 4) && (page_table_level != 3))) | |
2190 | return -EINVAL; | |
2191 | ||
2192 | mm = intel_vgpu_find_ppgtt_mm(vgpu, page_table_level, pdp); | |
2193 | if (!mm) { | |
2194 | gvt_err("fail to find ppgtt instance.\n"); | |
2195 | return -EINVAL; | |
2196 | } | |
2197 | intel_gvt_mm_unreference(mm); | |
2198 | return 0; | |
2199 | } | |
2200 | ||
2201 | /** | |
2202 | * intel_gvt_init_gtt - initialize mm components of a GVT device | |
2203 | * @gvt: GVT device | |
2204 | * | |
2205 | * This function is called at the initialization stage, to initialize | |
2206 | * the mm components of a GVT device. | |
2207 | * | |
2208 | * Returns: | |
2209 | * zero on success, negative error code if failed. | |
2210 | */ | |
2211 | int intel_gvt_init_gtt(struct intel_gvt *gvt) | |
2212 | { | |
2213 | int ret; | |
9631739f | 2214 | void *page; |
5de6bd4c CD |
2215 | struct device *dev = &gvt->dev_priv->drm.pdev->dev; |
2216 | dma_addr_t daddr; | |
2707e444 ZW |
2217 | |
2218 | gvt_dbg_core("init gtt\n"); | |
2219 | ||
2220 | if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) { | |
2221 | gvt->gtt.pte_ops = &gen8_gtt_pte_ops; | |
2222 | gvt->gtt.gma_ops = &gen8_gtt_gma_ops; | |
2223 | gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table; | |
2224 | gvt->gtt.mm_free_page_table = gen8_mm_free_page_table; | |
2225 | } else { | |
2226 | return -ENODEV; | |
2227 | } | |
2228 | ||
9631739f JS |
2229 | page = (void *)get_zeroed_page(GFP_KERNEL); |
2230 | if (!page) { | |
d650ac06 PG |
2231 | gvt_err("fail to allocate scratch ggtt page\n"); |
2232 | return -ENOMEM; | |
2233 | } | |
2234 | ||
5de6bd4c CD |
2235 | daddr = dma_map_page(dev, virt_to_page(page), 0, |
2236 | 4096, PCI_DMA_BIDIRECTIONAL); | |
2237 | if (dma_mapping_error(dev, daddr)) { | |
2238 | gvt_err("fail to dmamap scratch ggtt page\n"); | |
2239 | __free_page(virt_to_page(page)); | |
2240 | return -ENOMEM; | |
d650ac06 | 2241 | } |
5de6bd4c CD |
2242 | gvt->gtt.scratch_ggtt_page = virt_to_page(page); |
2243 | gvt->gtt.scratch_ggtt_mfn = (unsigned long)(daddr >> GTT_PAGE_SHIFT); | |
d650ac06 | 2244 | |
2707e444 ZW |
2245 | if (enable_out_of_sync) { |
2246 | ret = setup_spt_oos(gvt); | |
2247 | if (ret) { | |
2248 | gvt_err("fail to initialize SPT oos\n"); | |
2249 | return ret; | |
2250 | } | |
2251 | } | |
2252 | INIT_LIST_HEAD(&gvt->gtt.mm_lru_list_head); | |
2253 | return 0; | |
2254 | } | |
2255 | ||
2256 | /** | |
2257 | * intel_gvt_clean_gtt - clean up mm components of a GVT device | |
2258 | * @gvt: GVT device | |
2259 | * | |
2260 | * This function is called at the driver unloading stage, to clean up the | |
2261 | * the mm components of a GVT device. | |
2262 | * | |
2263 | */ | |
2264 | void intel_gvt_clean_gtt(struct intel_gvt *gvt) | |
2265 | { | |
5de6bd4c CD |
2266 | struct device *dev = &gvt->dev_priv->drm.pdev->dev; |
2267 | dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_ggtt_mfn << | |
2268 | GTT_PAGE_SHIFT); | |
2269 | ||
2270 | dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL); | |
2271 | ||
d650ac06 PG |
2272 | __free_page(gvt->gtt.scratch_ggtt_page); |
2273 | ||
2707e444 ZW |
2274 | if (enable_out_of_sync) |
2275 | clean_spt_oos(gvt); | |
2276 | } | |
d650ac06 PG |
2277 | |
2278 | /** | |
2279 | * intel_vgpu_reset_ggtt - reset the GGTT entry | |
2280 | * @vgpu: a vGPU | |
2281 | * | |
2282 | * This function is called at the vGPU create stage | |
2283 | * to reset all the GGTT entries. | |
2284 | * | |
2285 | */ | |
2286 | void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu) | |
2287 | { | |
2288 | struct intel_gvt *gvt = vgpu->gvt; | |
2289 | struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; | |
2290 | u32 index; | |
2291 | u32 offset; | |
2292 | u32 num_entries; | |
2293 | struct intel_gvt_gtt_entry e; | |
2294 | ||
2295 | memset(&e, 0, sizeof(struct intel_gvt_gtt_entry)); | |
2296 | e.type = GTT_TYPE_GGTT_PTE; | |
2297 | ops->set_pfn(&e, gvt->gtt.scratch_ggtt_mfn); | |
2298 | e.val64 |= _PAGE_PRESENT; | |
2299 | ||
2300 | index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT; | |
2301 | num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT; | |
2302 | for (offset = 0; offset < num_entries; offset++) | |
2303 | ops->set_entry(NULL, &e, index + offset, false, 0, vgpu); | |
2304 | ||
2305 | index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT; | |
2306 | num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT; | |
2307 | for (offset = 0; offset < num_entries; offset++) | |
2308 | ops->set_entry(NULL, &e, index + offset, false, 0, vgpu); | |
2309 | } | |
b611581b CD |
2310 | |
2311 | /** | |
2312 | * intel_vgpu_reset_gtt - reset the all GTT related status | |
2313 | * @vgpu: a vGPU | |
2314 | * @dmlr: true for vGPU Device Model Level Reset, false for GT Reset | |
2315 | * | |
2316 | * This function is called from vfio core to reset reset all | |
2317 | * GTT related status, including GGTT, PPGTT, scratch page. | |
2318 | * | |
2319 | */ | |
2320 | void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr) | |
2321 | { | |
2322 | int i; | |
2323 | ||
2324 | ppgtt_free_all_shadow_page(vgpu); | |
2325 | if (!dmlr) | |
2326 | return; | |
2327 | ||
2328 | intel_vgpu_reset_ggtt(vgpu); | |
2329 | ||
2330 | /* clear scratch page for security */ | |
2331 | for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) { | |
2332 | if (vgpu->gtt.scratch_pt[i].page != NULL) | |
2333 | memset(page_address(vgpu->gtt.scratch_pt[i].page), | |
2334 | 0, PAGE_SIZE); | |
2335 | } | |
2336 | } |