[linux.git] / drivers / clocksource / sh_mtu2.c

// SPDX-License-Identifier: GPL-2.0
/*
 * SuperH Timer Support - MTU2
 *
 *  Copyright (C) 2009 Magnus Damm
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#ifdef CONFIG_SUPERH
#include <asm/platform_early.h>
#endif

struct sh_mtu2_device;

struct sh_mtu2_channel {
	struct sh_mtu2_device *mtu;
	unsigned int index;

	void __iomem *base;

	struct clock_event_device ced;
};

struct sh_mtu2_device {
	struct platform_device *pdev;

	void __iomem *mapbase;
	struct clk *clk;

	raw_spinlock_t lock; /* Protect the shared registers */

	struct sh_mtu2_channel *channels;
	unsigned int num_channels;

	bool has_clockevent;
};

#define TSTR -1 /* shared register */
#define TCR  0 /* channel register */
#define TMDR 1 /* channel register */
#define TIOR 2 /* channel register */
#define TIER 3 /* channel register */
#define TSR  4 /* channel register */
#define TCNT 5 /* channel register */
#define TGR  6 /* channel register */

#define TCR_CCLR_NONE		(0 << 5)
#define TCR_CCLR_TGRA		(1 << 5)
#define TCR_CCLR_TGRB		(2 << 5)
#define TCR_CCLR_SYNC		(3 << 5)
#define TCR_CCLR_TGRC		(5 << 5)
#define TCR_CCLR_TGRD		(6 << 5)
#define TCR_CCLR_MASK		(7 << 5)
#define TCR_CKEG_RISING		(0 << 3)
#define TCR_CKEG_FALLING	(1 << 3)
#define TCR_CKEG_BOTH		(2 << 3)
#define TCR_CKEG_MASK		(3 << 3)
/* Values 4 to 7 are channel-dependent */
#define TCR_TPSC_P1		(0 << 0)
#define TCR_TPSC_P4		(1 << 0)
#define TCR_TPSC_P16		(2 << 0)
#define TCR_TPSC_P64		(3 << 0)
#define TCR_TPSC_CH0_TCLKA	(4 << 0)
#define TCR_TPSC_CH0_TCLKB	(5 << 0)
#define TCR_TPSC_CH0_TCLKC	(6 << 0)
#define TCR_TPSC_CH0_TCLKD	(7 << 0)
#define TCR_TPSC_CH1_TCLKA	(4 << 0)
#define TCR_TPSC_CH1_TCLKB	(5 << 0)
#define TCR_TPSC_CH1_P256	(6 << 0)
#define TCR_TPSC_CH1_TCNT2	(7 << 0)
#define TCR_TPSC_CH2_TCLKA	(4 << 0)
#define TCR_TPSC_CH2_TCLKB	(5 << 0)
#define TCR_TPSC_CH2_TCLKC	(6 << 0)
#define TCR_TPSC_CH2_P1024	(7 << 0)
#define TCR_TPSC_CH34_P256	(4 << 0)
#define TCR_TPSC_CH34_P1024	(5 << 0)
#define TCR_TPSC_CH34_TCLKA	(6 << 0)
#define TCR_TPSC_CH34_TCLKB	(7 << 0)
#define TCR_TPSC_MASK		(7 << 0)

#define TMDR_BFE		(1 << 6)
#define TMDR_BFB		(1 << 5)
#define TMDR_BFA		(1 << 4)
#define TMDR_MD_NORMAL		(0 << 0)
#define TMDR_MD_PWM_1		(2 << 0)
#define TMDR_MD_PWM_2		(3 << 0)
#define TMDR_MD_PHASE_1		(4 << 0)
#define TMDR_MD_PHASE_2		(5 << 0)
#define TMDR_MD_PHASE_3		(6 << 0)
#define TMDR_MD_PHASE_4		(7 << 0)
#define TMDR_MD_PWM_SYNC	(8 << 0)
#define TMDR_MD_PWM_COMP_CREST	(13 << 0)
#define TMDR_MD_PWM_COMP_TROUGH	(14 << 0)
#define TMDR_MD_PWM_COMP_BOTH	(15 << 0)
#define TMDR_MD_MASK		(15 << 0)

#define TIOC_IOCH(n)		((n) << 4)
#define TIOC_IOCL(n)		((n) << 0)
#define TIOR_OC_RETAIN		(0 << 0)
#define TIOR_OC_0_CLEAR		(1 << 0)
#define TIOR_OC_0_SET		(2 << 0)
#define TIOR_OC_0_TOGGLE	(3 << 0)
#define TIOR_OC_1_CLEAR		(5 << 0)
#define TIOR_OC_1_SET		(6 << 0)
#define TIOR_OC_1_TOGGLE	(7 << 0)
#define TIOR_IC_RISING		(8 << 0)
#define TIOR_IC_FALLING		(9 << 0)
#define TIOR_IC_BOTH		(10 << 0)
#define TIOR_IC_TCNT		(12 << 0)
#define TIOR_MASK		(15 << 0)

#define TIER_TTGE		(1 << 7)
#define TIER_TTGE2		(1 << 6)
#define TIER_TCIEU		(1 << 5)
#define TIER_TCIEV		(1 << 4)
#define TIER_TGIED		(1 << 3)
#define TIER_TGIEC		(1 << 2)
#define TIER_TGIEB		(1 << 1)
#define TIER_TGIEA		(1 << 0)

#define TSR_TCFD		(1 << 7)
#define TSR_TCFU		(1 << 5)
#define TSR_TCFV		(1 << 4)
#define TSR_TGFD		(1 << 3)
#define TSR_TGFC		(1 << 2)
#define TSR_TGFB		(1 << 1)
#define TSR_TGFA		(1 << 0)

static unsigned long mtu2_reg_offs[] = {
	[TCR] = 0,
	[TMDR] = 1,
	[TIOR] = 2,
	[TIER] = 4,
	[TSR] = 5,
	[TCNT] = 6,
	[TGR] = 8,
};

static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
{
	unsigned long offs;

	if (reg_nr == TSTR)
		return ioread8(ch->mtu->mapbase + 0x280);

	offs = mtu2_reg_offs[reg_nr];

	if ((reg_nr == TCNT) || (reg_nr == TGR))
		return ioread16(ch->base + offs);
	else
		return ioread8(ch->base + offs);
}

static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
				unsigned long value)
{
	unsigned long offs;

	if (reg_nr == TSTR)
		return iowrite8(value, ch->mtu->mapbase + 0x280);

	offs = mtu2_reg_offs[reg_nr];

	if ((reg_nr == TCNT) || (reg_nr == TGR))
		iowrite16(value, ch->base + offs);
	else
		iowrite8(value, ch->base + offs);
}

static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
{
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	raw_spin_lock_irqsave(&ch->mtu->lock, flags);
	value = sh_mtu2_read(ch, TSTR);

	if (start)
		value |= 1 << ch->index;
	else
		value &= ~(1 << ch->index);

	sh_mtu2_write(ch, TSTR, value);
	raw_spin_unlock_irqrestore(&ch->mtu->lock, flags);
}

static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
{
	unsigned long periodic;
	unsigned long rate;
	int ret;

	pm_runtime_get_sync(&ch->mtu->pdev->dev);
	dev_pm_syscore_device(&ch->mtu->pdev->dev, true);

	/* enable clock */
	ret = clk_enable(ch->mtu->clk);
	if (ret) {
		dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
			ch->index);
		return ret;
	}

	/* make sure channel is disabled */
	sh_mtu2_start_stop_ch(ch, 0);

	rate = clk_get_rate(ch->mtu->clk) / 64;
	periodic = (rate + HZ/2) / HZ;

	/*
	 * "Periodic Counter Operation"
	 * Clear on TGRA compare match, divide clock by 64.
	 */
	sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
	sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |
		      TIOC_IOCL(TIOR_OC_0_CLEAR));
	sh_mtu2_write(ch, TGR, periodic);
	sh_mtu2_write(ch, TCNT, 0);
	sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
	sh_mtu2_write(ch, TIER, TIER_TGIEA);

	/* enable channel */
	sh_mtu2_start_stop_ch(ch, 1);

	return 0;
}

static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
{
	/* disable channel */
	sh_mtu2_start_stop_ch(ch, 0);

	/* stop clock */
	clk_disable(ch->mtu->clk);

	dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
	pm_runtime_put(&ch->mtu->pdev->dev);
}

static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
{
	struct sh_mtu2_channel *ch = dev_id;

	/* acknowledge interrupt */
	sh_mtu2_read(ch, TSR);
	sh_mtu2_write(ch, TSR, ~TSR_TGFA);

	/* notify clockevent layer */
	ch->ced.event_handler(&ch->ced);
	return IRQ_HANDLED;
}

static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
{
	return container_of(ced, struct sh_mtu2_channel, ced);
}

static int sh_mtu2_clock_event_shutdown(struct clock_event_device *ced)
{
	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);

	if (clockevent_state_periodic(ced))
		sh_mtu2_disable(ch);

	return 0;
}

static int sh_mtu2_clock_event_set_periodic(struct clock_event_device *ced)
{
	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);

	if (clockevent_state_periodic(ced))
		sh_mtu2_disable(ch);

	dev_info(&ch->mtu->pdev->dev, "ch%u: used for periodic clock events\n",
		 ch->index);
	sh_mtu2_enable(ch);
	return 0;
}

static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
{
	dev_pm_genpd_suspend(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
}

static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
{
	dev_pm_genpd_resume(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
}

static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
					const char *name)
{
	struct clock_event_device *ced = &ch->ced;

	ced->name = name;
	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	ced->rating = 200;
	ced->cpumask = cpu_possible_mask;
	ced->set_state_shutdown = sh_mtu2_clock_event_shutdown;
	ced->set_state_periodic = sh_mtu2_clock_event_set_periodic;
	ced->suspend = sh_mtu2_clock_event_suspend;
	ced->resume = sh_mtu2_clock_event_resume;

	dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
		 ch->index);
	clockevents_register_device(ced);
}

static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name)
{
	ch->mtu->has_clockevent = true;
	sh_mtu2_register_clockevent(ch, name);

	return 0;
}

static const unsigned int sh_mtu2_channel_offsets[] = {
	0x300, 0x380, 0x000,
};

static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
				 struct sh_mtu2_device *mtu)
{
	char name[6];
	int irq;
	int ret;

	ch->mtu = mtu;

	sprintf(name, "tgi%ua", index);
	irq = platform_get_irq_byname(mtu->pdev, name);
	if (irq < 0) {
		/* Skip channels with no declared interrupt. */
		return 0;
	}

	ret = request_irq(irq, sh_mtu2_interrupt,
			  IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
			  dev_name(&ch->mtu->pdev->dev), ch);
	if (ret) {
		dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
			index, irq);
		return ret;
	}

	ch->base = mtu->mapbase + sh_mtu2_channel_offsets[index];
	ch->index = index;

	return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev));
}

static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
{
	struct resource *res;

	res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");
		return -ENXIO;
	}

	mtu->mapbase = ioremap(res->start, resource_size(res));
	if (mtu->mapbase == NULL)
		return -ENXIO;

	return 0;
}

static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
			 struct platform_device *pdev)
{
	unsigned int i;
	int ret;

	mtu->pdev = pdev;

	raw_spin_lock_init(&mtu->lock);

	/* Get hold of clock. */
	mtu->clk = clk_get(&mtu->pdev->dev, "fck");
	if (IS_ERR(mtu->clk)) {
		dev_err(&mtu->pdev->dev, "cannot get clock\n");
		return PTR_ERR(mtu->clk);
	}

	ret = clk_prepare(mtu->clk);
	if (ret < 0)
		goto err_clk_put;

	/* Map the memory resource. */
	ret = sh_mtu2_map_memory(mtu);
	if (ret < 0) {
		dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");
		goto err_clk_unprepare;
	}

	/* Allocate and setup the channels. */
	ret = platform_irq_count(pdev);
	if (ret < 0)
		goto err_unmap;

	mtu->num_channels = min_t(unsigned int, ret,
				  ARRAY_SIZE(sh_mtu2_channel_offsets));

	mtu->channels = kcalloc(mtu->num_channels, sizeof(*mtu->channels),
				GFP_KERNEL);
	if (mtu->channels == NULL) {
		ret = -ENOMEM;
		goto err_unmap;
	}

	for (i = 0; i < mtu->num_channels; ++i) {
		ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
		if (ret < 0)
			goto err_unmap;
	}

	platform_set_drvdata(pdev, mtu);

	return 0;

err_unmap:
	kfree(mtu->channels);
	iounmap(mtu->mapbase);
err_clk_unprepare:
	clk_unprepare(mtu->clk);
err_clk_put:
	clk_put(mtu->clk);
	return ret;
}

static int sh_mtu2_probe(struct platform_device *pdev)
{
	struct sh_mtu2_device *mtu = platform_get_drvdata(pdev);
	int ret;

	if (!is_sh_early_platform_device(pdev)) {
		pm_runtime_set_active(&pdev->dev);
		pm_runtime_enable(&pdev->dev);
	}

	if (mtu) {
		dev_info(&pdev->dev, "kept as earlytimer\n");
		goto out;
	}

	mtu = kzalloc(sizeof(*mtu), GFP_KERNEL);
	if (mtu == NULL)
		return -ENOMEM;

	ret = sh_mtu2_setup(mtu, pdev);
	if (ret) {
		kfree(mtu);
		pm_runtime_idle(&pdev->dev);
		return ret;
	}
	if (is_sh_early_platform_device(pdev))
		return 0;

 out:
	if (mtu->has_clockevent)
		pm_runtime_irq_safe(&pdev->dev);
	else
		pm_runtime_idle(&pdev->dev);

	return 0;
}

static const struct platform_device_id sh_mtu2_id_table[] = {
	{ "sh-mtu2", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);

static const struct of_device_id sh_mtu2_of_table[] __maybe_unused = {
	{ .compatible = "renesas,mtu2" },
	{ }
};
MODULE_DEVICE_TABLE(of, sh_mtu2_of_table);

static struct platform_driver sh_mtu2_device_driver = {
	.probe		= sh_mtu2_probe,
	.driver		= {
		.name	= "sh_mtu2",
		.of_match_table = of_match_ptr(sh_mtu2_of_table),
		.suppress_bind_attrs = true,
	},
	.id_table	= sh_mtu2_id_table,
};

static int __init sh_mtu2_init(void)
{
	return platform_driver_register(&sh_mtu2_device_driver);
}

static void __exit sh_mtu2_exit(void)
{
	platform_driver_unregister(&sh_mtu2_device_driver);
}

#ifdef CONFIG_SUPERH
sh_early_platform_init("earlytimer", &sh_mtu2_device_driver);
#endif

subsys_initcall(sh_mtu2_init);
module_exit(sh_mtu2_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
Commit	Line	Data
ddb89642	1	// SPDX-License-Identifier: GPL-2.0
d5ed4c2e MD	2	/*
	3	* SuperH Timer Support - MTU2
	4	*
	5	* Copyright (C) 2009 Magnus Damm
d5ed4c2e MD	6	*/
d5ed4c2e MD	7
346f5e76 LP	8	#include <linux/clk.h>
	9	#include <linux/clockchips.h>
	10	#include <linux/delay.h>
	11	#include <linux/err.h>
d5ed4c2e	12	#include <linux/init.h>
d5ed4c2e	13	#include <linux/interrupt.h>
d5ed4c2e	14	#include <linux/io.h>
346f5e76	15	#include <linux/ioport.h>
d5ed4c2e	16	#include <linux/irq.h>
7deeab5d	17	#include <linux/module.h>
cca8d059	18	#include <linux/of.h>
346f5e76	19	#include <linux/platform_device.h>
57d13370	20	#include <linux/pm_domain.h>
3cb6f10a	21	#include <linux/pm_runtime.h>
346f5e76 LP	22	#include <linux/sh_timer.h>
	23	#include <linux/slab.h>
	24	#include <linux/spinlock.h>
d5ed4c2e	25
507fd01d BG	26	#ifdef CONFIG_SUPERH
	27	#include <asm/platform_early.h>
	28	#endif
	29
7dad72de	30	struct sh_mtu2_device;
42752cc6 LP	31
42752cc6 LP	32	struct sh_mtu2_channel {
7dad72de	33	struct sh_mtu2_device *mtu;
d2b93177	34	unsigned int index;
da90a1c6 LP	35
da90a1c6 LP	36	void __iomem *base;
da90a1c6	37
42752cc6 LP	38	struct clock_event_device ced;
	39	};
	40
7dad72de	41	struct sh_mtu2_device {
42752cc6 LP	42	struct platform_device *pdev;
42752cc6 LP	43
d5ed4c2e MD	44	void __iomem *mapbase;
d5ed4c2e MD	45	struct clk *clk;
42752cc6	46
8b2463d8 LP	47	raw_spinlock_t lock; /* Protect the shared registers */
8b2463d8 LP	48
c54ccb43 LP	49	struct sh_mtu2_channel *channels;
c54ccb43 LP	50	unsigned int num_channels;
faf3f4f8	51
faf3f4f8	52	bool has_clockevent;
d5ed4c2e MD	53	};
d5ed4c2e MD	54
d5ed4c2e MD	55	#define TSTR -1 /* shared register */
	56	#define TCR 0 /* channel register */
	57	#define TMDR 1 /* channel register */
	58	#define TIOR 2 /* channel register */
	59	#define TIER 3 /* channel register */
	60	#define TSR 4 /* channel register */
	61	#define TCNT 5 /* channel register */
	62	#define TGR 6 /* channel register */
	63
f992c241 LP	64	#define TCR_CCLR_NONE (0 << 5)
	65	#define TCR_CCLR_TGRA (1 << 5)
	66	#define TCR_CCLR_TGRB (2 << 5)
	67	#define TCR_CCLR_SYNC (3 << 5)
	68	#define TCR_CCLR_TGRC (5 << 5)
	69	#define TCR_CCLR_TGRD (6 << 5)
	70	#define TCR_CCLR_MASK (7 << 5)
	71	#define TCR_CKEG_RISING (0 << 3)
	72	#define TCR_CKEG_FALLING (1 << 3)
	73	#define TCR_CKEG_BOTH (2 << 3)
	74	#define TCR_CKEG_MASK (3 << 3)
	75	/* Values 4 to 7 are channel-dependent */
	76	#define TCR_TPSC_P1 (0 << 0)
	77	#define TCR_TPSC_P4 (1 << 0)
	78	#define TCR_TPSC_P16 (2 << 0)
	79	#define TCR_TPSC_P64 (3 << 0)
	80	#define TCR_TPSC_CH0_TCLKA (4 << 0)
	81	#define TCR_TPSC_CH0_TCLKB (5 << 0)
	82	#define TCR_TPSC_CH0_TCLKC (6 << 0)
	83	#define TCR_TPSC_CH0_TCLKD (7 << 0)
	84	#define TCR_TPSC_CH1_TCLKA (4 << 0)
	85	#define TCR_TPSC_CH1_TCLKB (5 << 0)
	86	#define TCR_TPSC_CH1_P256 (6 << 0)
	87	#define TCR_TPSC_CH1_TCNT2 (7 << 0)
	88	#define TCR_TPSC_CH2_TCLKA (4 << 0)
	89	#define TCR_TPSC_CH2_TCLKB (5 << 0)
	90	#define TCR_TPSC_CH2_TCLKC (6 << 0)
	91	#define TCR_TPSC_CH2_P1024 (7 << 0)
	92	#define TCR_TPSC_CH34_P256 (4 << 0)
	93	#define TCR_TPSC_CH34_P1024 (5 << 0)
	94	#define TCR_TPSC_CH34_TCLKA (6 << 0)
	95	#define TCR_TPSC_CH34_TCLKB (7 << 0)
	96	#define TCR_TPSC_MASK (7 << 0)
	97
	98	#define TMDR_BFE (1 << 6)
	99	#define TMDR_BFB (1 << 5)
	100	#define TMDR_BFA (1 << 4)
	101	#define TMDR_MD_NORMAL (0 << 0)
	102	#define TMDR_MD_PWM_1 (2 << 0)
	103	#define TMDR_MD_PWM_2 (3 << 0)
	104	#define TMDR_MD_PHASE_1 (4 << 0)
	105	#define TMDR_MD_PHASE_2 (5 << 0)
	106	#define TMDR_MD_PHASE_3 (6 << 0)
	107	#define TMDR_MD_PHASE_4 (7 << 0)
	108	#define TMDR_MD_PWM_SYNC (8 << 0)
	109	#define TMDR_MD_PWM_COMP_CREST (13 << 0)
	110	#define TMDR_MD_PWM_COMP_TROUGH (14 << 0)
	111	#define TMDR_MD_PWM_COMP_BOTH (15 << 0)
	112	#define TMDR_MD_MASK (15 << 0)
	113
	114	#define TIOC_IOCH(n) ((n) << 4)
	115	#define TIOC_IOCL(n) ((n) << 0)
	116	#define TIOR_OC_RETAIN (0 << 0)
	117	#define TIOR_OC_0_CLEAR (1 << 0)
	118	#define TIOR_OC_0_SET (2 << 0)
	119	#define TIOR_OC_0_TOGGLE (3 << 0)
	120	#define TIOR_OC_1_CLEAR (5 << 0)
	121	#define TIOR_OC_1_SET (6 << 0)
	122	#define TIOR_OC_1_TOGGLE (7 << 0)
	123	#define TIOR_IC_RISING (8 << 0)
	124	#define TIOR_IC_FALLING (9 << 0)
	125	#define TIOR_IC_BOTH (10 << 0)
	126	#define TIOR_IC_TCNT (12 << 0)
	127	#define TIOR_MASK (15 << 0)
128
129	#define TIER_TTGE (1 << 7)
130	#define TIER_TTGE2 (1 << 6)
131	#define TIER_TCIEU (1 << 5)
132	#define TIER_TCIEV (1 << 4)
133	#define TIER_TGIED (1 << 3)
134	#define TIER_TGIEC (1 << 2)
135	#define TIER_TGIEB (1 << 1)
136	#define TIER_TGIEA (1 << 0)
137
138	#define TSR_TCFD (1 << 7)
139	#define TSR_TCFU (1 << 5)
140	#define TSR_TCFV (1 << 4)
141	#define TSR_TGFD (1 << 3)
142	#define TSR_TGFC (1 << 2)
143	#define TSR_TGFB (1 << 1)
144	#define TSR_TGFA (1 << 0)
145
d5ed4c2e MD	146	static unsigned long mtu2_reg_offs[] = {
	147	[TCR] = 0,
	148	[TMDR] = 1,
	149	[TIOR] = 2,
	150	[TIER] = 4,
	151	[TSR] = 5,
	152	[TCNT] = 6,
	153	[TGR] = 8,
	154	};
	155
42752cc6	156	static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
d5ed4c2e	157	{
d5ed4c2e MD	158	unsigned long offs;
d5ed4c2e MD	159
1a5da0e4 LP	160	if (reg_nr == TSTR)
1a5da0e4 LP	161	return ioread8(ch->mtu->mapbase + 0x280);
d5ed4c2e MD	162
	163	offs = mtu2_reg_offs[reg_nr];
	164
	165	if ((reg_nr == TCNT) \|\| (reg_nr == TGR))
da90a1c6	166	return ioread16(ch->base + offs);
d5ed4c2e	167	else
da90a1c6	168	return ioread8(ch->base + offs);
d5ed4c2e MD	169	}
d5ed4c2e MD	170
42752cc6	171	static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
d5ed4c2e MD	172	unsigned long value)
d5ed4c2e MD	173	{
d5ed4c2e MD	174	unsigned long offs;
d5ed4c2e MD	175
1a5da0e4 LP	176	if (reg_nr == TSTR)
1a5da0e4 LP	177	return iowrite8(value, ch->mtu->mapbase + 0x280);
d5ed4c2e MD	178
	179	offs = mtu2_reg_offs[reg_nr];
	180
	181	if ((reg_nr == TCNT) \|\| (reg_nr == TGR))
da90a1c6	182	iowrite16(value, ch->base + offs);
d5ed4c2e	183	else
da90a1c6	184	iowrite8(value, ch->base + offs);
d5ed4c2e MD	185	}
d5ed4c2e MD	186
42752cc6	187	static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
d5ed4c2e	188	{
d5ed4c2e MD	189	unsigned long flags, value;
	190
	191	/* start stop register shared by multiple timer channels */
8b2463d8	192	raw_spin_lock_irqsave(&ch->mtu->lock, flags);
42752cc6	193	value = sh_mtu2_read(ch, TSTR);
d5ed4c2e MD	194
d5ed4c2e MD	195	if (start)
d2b93177	196	value \|= 1 << ch->index;
d5ed4c2e	197	else
d2b93177	198	value &= ~(1 << ch->index);
d5ed4c2e	199
42752cc6	200	sh_mtu2_write(ch, TSTR, value);
8b2463d8	201	raw_spin_unlock_irqrestore(&ch->mtu->lock, flags);
d5ed4c2e MD	202	}
d5ed4c2e MD	203
42752cc6	204	static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
d5ed4c2e	205	{
f92d62f5 LP	206	unsigned long periodic;
f92d62f5 LP	207	unsigned long rate;
d5ed4c2e MD	208	int ret;
d5ed4c2e MD	209
42752cc6 LP	210	pm_runtime_get_sync(&ch->mtu->pdev->dev);
42752cc6 LP	211	dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
3cb6f10a	212
d5ed4c2e	213	/* enable clock */
42752cc6	214	ret = clk_enable(ch->mtu->clk);
d5ed4c2e	215	if (ret) {
d2b93177 LP	216	dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
d2b93177 LP	217	ch->index);
d5ed4c2e MD	218	return ret;
	219	}
	220
	221	/* make sure channel is disabled */
42752cc6	222	sh_mtu2_start_stop_ch(ch, 0);
d5ed4c2e	223
42752cc6	224	rate = clk_get_rate(ch->mtu->clk) / 64;
f92d62f5	225	periodic = (rate + HZ/2) / HZ;
d5ed4c2e	226
f992c241 LP	227	/*
	228	* "Periodic Counter Operation"
	229	* Clear on TGRA compare match, divide clock by 64.
	230	*/
	231	sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA \| TCR_TPSC_P64);
	232	sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) \|
	233	TIOC_IOCL(TIOR_OC_0_CLEAR));
42752cc6 LP	234	sh_mtu2_write(ch, TGR, periodic);
42752cc6 LP	235	sh_mtu2_write(ch, TCNT, 0);
f992c241 LP	236	sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
f992c241 LP	237	sh_mtu2_write(ch, TIER, TIER_TGIEA);
d5ed4c2e MD	238
d5ed4c2e MD	239	/* enable channel */
42752cc6	240	sh_mtu2_start_stop_ch(ch, 1);
d5ed4c2e MD	241
	242	return 0;
	243	}
	244
42752cc6	245	static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
d5ed4c2e MD	246	{
d5ed4c2e MD	247	/* disable channel */
42752cc6	248	sh_mtu2_start_stop_ch(ch, 0);
d5ed4c2e MD	249
d5ed4c2e MD	250	/* stop clock */
42752cc6	251	clk_disable(ch->mtu->clk);
3cb6f10a	252
42752cc6 LP	253	dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
42752cc6 LP	254	pm_runtime_put(&ch->mtu->pdev->dev);
d5ed4c2e MD	255	}
	256
	257	static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
	258	{
42752cc6	259	struct sh_mtu2_channel *ch = dev_id;
d5ed4c2e MD	260
d5ed4c2e MD	261	/* acknowledge interrupt */
42752cc6	262	sh_mtu2_read(ch, TSR);
f992c241	263	sh_mtu2_write(ch, TSR, ~TSR_TGFA);
d5ed4c2e MD	264
d5ed4c2e MD	265	/* notify clockevent layer */
42752cc6	266	ch->ced.event_handler(&ch->ced);
d5ed4c2e MD	267	return IRQ_HANDLED;
	268	}
	269
42752cc6	270	static struct sh_mtu2_channel ced_to_sh_mtu2(struct clock_event_device ced)
d5ed4c2e	271	{
42752cc6	272	return container_of(ced, struct sh_mtu2_channel, ced);
d5ed4c2e MD	273	}
d5ed4c2e MD	274
19a9ffb3	275	static int sh_mtu2_clock_event_shutdown(struct clock_event_device *ced)
d5ed4c2e	276	{
42752cc6	277	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
d5ed4c2e	278
fe326c5c MD	279	if (clockevent_state_periodic(ced))
	280	sh_mtu2_disable(ch);
	281
19a9ffb3 VK	282	return 0;
	283	}
	284
	285	static int sh_mtu2_clock_event_set_periodic(struct clock_event_device *ced)
	286	{
	287	struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
	288
	289	if (clockevent_state_periodic(ced))
42752cc6	290	sh_mtu2_disable(ch);
d5ed4c2e	291
19a9ffb3 VK	292	dev_info(&ch->mtu->pdev->dev, "ch%u: used for periodic clock events\n",
	293	ch->index);
	294	sh_mtu2_enable(ch);
	295	return 0;
d5ed4c2e MD	296	}
d5ed4c2e MD	297
cc7ad456 RW	298	static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
cc7ad456 RW	299	{
fc519890	300	dev_pm_genpd_suspend(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
cc7ad456 RW	301	}
	302
	303	static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
	304	{
fc519890	305	dev_pm_genpd_resume(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
cc7ad456 RW	306	}
cc7ad456 RW	307
42752cc6	308	static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
207e21a9	309	const char *name)
d5ed4c2e	310	{
42752cc6	311	struct clock_event_device *ced = &ch->ced;
d5ed4c2e	312
d5ed4c2e MD	313	ced->name = name;
d5ed4c2e MD	314	ced->features = CLOCK_EVT_FEAT_PERIODIC;
207e21a9	315	ced->rating = 200;
3cc95047	316	ced->cpumask = cpu_possible_mask;
19a9ffb3 VK	317	ced->set_state_shutdown = sh_mtu2_clock_event_shutdown;
19a9ffb3 VK	318	ced->set_state_periodic = sh_mtu2_clock_event_set_periodic;
cc7ad456 RW	319	ced->suspend = sh_mtu2_clock_event_suspend;
cc7ad456 RW	320	ced->resume = sh_mtu2_clock_event_resume;
d5ed4c2e	321
d2b93177 LP	322	dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
d2b93177 LP	323	ch->index);
da64c2a8	324	clockevents_register_device(ced);
d5ed4c2e MD	325	}
d5ed4c2e MD	326
1a5da0e4	327	static int sh_mtu2_register(struct sh_mtu2_channel ch, const char name)
d5ed4c2e	328	{
1a5da0e4 LP	329	ch->mtu->has_clockevent = true;
1a5da0e4 LP	330	sh_mtu2_register_clockevent(ch, name);
d5ed4c2e MD	331
	332	return 0;
	333	}
	334
7693de9f GU	335	static const unsigned int sh_mtu2_channel_offsets[] = {
	336	0x300, 0x380, 0x000,
	337	};
	338
faf3f4f8	339	static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
2e1a5326 LP	340	struct sh_mtu2_device *mtu)
2e1a5326 LP	341	{
1a5da0e4 LP	342	char name[6];
	343	int irq;
	344	int ret;
2e1a5326	345
2e1a5326 LP	346	ch->mtu = mtu;
2e1a5326 LP	347
1a5da0e4 LP	348	sprintf(name, "tgi%ua", index);
	349	irq = platform_get_irq_byname(mtu->pdev, name);
	350	if (irq < 0) {
faf3f4f8	351	/* Skip channels with no declared interrupt. */
1a5da0e4 LP	352	return 0;
1a5da0e4 LP	353	}
faf3f4f8	354
1a5da0e4 LP	355	ret = request_irq(irq, sh_mtu2_interrupt,
	356	IRQF_TIMER \| IRQF_IRQPOLL \| IRQF_NOBALANCING,
	357	dev_name(&ch->mtu->pdev->dev), ch);
	358	if (ret) {
	359	dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
	360	index, irq);
	361	return ret;
2e1a5326 LP	362	}
2e1a5326 LP	363
7693de9f	364	ch->base = mtu->mapbase + sh_mtu2_channel_offsets[index];
1a5da0e4 LP	365	ch->index = index;
	366
	367	return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev));
2e1a5326 LP	368	}
2e1a5326 LP	369
faf3f4f8	370	static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
d5ed4c2e	371	{
d5ed4c2e	372	struct resource *res;
d5ed4c2e	373
7dad72de	374	res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);
d5ed4c2e	375	if (!res) {
7dad72de	376	dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");
faf3f4f8	377	return -ENXIO;
d5ed4c2e MD	378	}
d5ed4c2e MD	379
4bdc0d67	380	mtu->mapbase = ioremap(res->start, resource_size(res));
faf3f4f8 LP	381	if (mtu->mapbase == NULL)
	382	return -ENXIO;
	383
faf3f4f8 LP	384	return 0;
	385	}
	386
faf3f4f8 LP	387	static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
	388	struct platform_device *pdev)
	389	{
faf3f4f8 LP	390	unsigned int i;
	391	int ret;
	392
	393	mtu->pdev = pdev;
da90a1c6	394
8b2463d8 LP	395	raw_spin_lock_init(&mtu->lock);
8b2463d8 LP	396
faf3f4f8	397	/* Get hold of clock. */
1a5da0e4	398	mtu->clk = clk_get(&mtu->pdev->dev, "fck");
7dad72de LP	399	if (IS_ERR(mtu->clk)) {
7dad72de LP	400	dev_err(&mtu->pdev->dev, "cannot get clock\n");
faf3f4f8	401	return PTR_ERR(mtu->clk);
d5ed4c2e MD	402	}
d5ed4c2e MD	403
7dad72de	404	ret = clk_prepare(mtu->clk);
bd754930	405	if (ret < 0)
faf3f4f8	406	goto err_clk_put;
bd754930	407
faf3f4f8 LP	408	/* Map the memory resource. */
	409	ret = sh_mtu2_map_memory(mtu);
	410	if (ret < 0) {
	411	dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");
	412	goto err_clk_unprepare;
	413	}
	414
	415	/* Allocate and setup the channels. */
7693de9f GU	416	ret = platform_irq_count(pdev);
	417	if (ret < 0)
	418	goto err_unmap;
	419
	420	mtu->num_channels = min_t(unsigned int, ret,
	421	ARRAY_SIZE(sh_mtu2_channel_offsets));
faf3f4f8	422
6396bb22	423	mtu->channels = kcalloc(mtu->num_channels, sizeof(*mtu->channels),
faf3f4f8	424	GFP_KERNEL);
c54ccb43 LP	425	if (mtu->channels == NULL) {
c54ccb43 LP	426	ret = -ENOMEM;
faf3f4f8	427	goto err_unmap;
c54ccb43 LP	428	}
c54ccb43 LP	429
1a5da0e4 LP	430	for (i = 0; i < mtu->num_channels; ++i) {
1a5da0e4 LP	431	ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
faf3f4f8 LP	432	if (ret < 0)
faf3f4f8 LP	433	goto err_unmap;
faf3f4f8	434	}
c54ccb43	435
faf3f4f8	436	platform_set_drvdata(pdev, mtu);
a4a5fc3b LP	437
a4a5fc3b LP	438	return 0;
faf3f4f8 LP	439
faf3f4f8 LP	440	err_unmap:
c54ccb43	441	kfree(mtu->channels);
1a5da0e4	442	iounmap(mtu->mapbase);
faf3f4f8	443	err_clk_unprepare:
7dad72de	444	clk_unprepare(mtu->clk);
faf3f4f8	445	err_clk_put:
7dad72de	446	clk_put(mtu->clk);
d5ed4c2e MD	447	return ret;
	448	}
	449
1850514b	450	static int sh_mtu2_probe(struct platform_device *pdev)
d5ed4c2e	451	{
7dad72de	452	struct sh_mtu2_device *mtu = platform_get_drvdata(pdev);
d5ed4c2e	453	int ret;
57d13370	454
201e9109	455	if (!is_sh_early_platform_device(pdev)) {
3cb6f10a RW	456	pm_runtime_set_active(&pdev->dev);
3cb6f10a RW	457	pm_runtime_enable(&pdev->dev);
cc7ad456	458	}
d5ed4c2e	459
7dad72de	460	if (mtu) {
214a607a	461	dev_info(&pdev->dev, "kept as earlytimer\n");
3cb6f10a	462	goto out;
d5ed4c2e MD	463	}
d5ed4c2e MD	464
810c6513	465	mtu = kzalloc(sizeof(*mtu), GFP_KERNEL);
c77a565b	466	if (mtu == NULL)
d5ed4c2e	467	return -ENOMEM;
d5ed4c2e	468
7dad72de	469	ret = sh_mtu2_setup(mtu, pdev);
d5ed4c2e	470	if (ret) {
7dad72de	471	kfree(mtu);
3cb6f10a RW	472	pm_runtime_idle(&pdev->dev);
3cb6f10a RW	473	return ret;
d5ed4c2e	474	}
201e9109	475	if (is_sh_early_platform_device(pdev))
3cb6f10a RW	476	return 0;
	477
	478	out:
faf3f4f8	479	if (mtu->has_clockevent)
3cb6f10a RW	480	pm_runtime_irq_safe(&pdev->dev);
	481	else
	482	pm_runtime_idle(&pdev->dev);
	483
	484	return 0;
d5ed4c2e MD	485	}
d5ed4c2e MD	486
faf3f4f8	487	static const struct platform_device_id sh_mtu2_id_table[] = {
faf3f4f8 LP	488	{ "sh-mtu2", 0 },
	489	{ },
	490	};
	491	MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);
	492
cca8d059 LP	493	static const struct of_device_id sh_mtu2_of_table[] __maybe_unused = {
	494	{ .compatible = "renesas,mtu2" },
	495	{ }
	496	};
	497	MODULE_DEVICE_TABLE(of, sh_mtu2_of_table);
	498
d5ed4c2e MD	499	static struct platform_driver sh_mtu2_device_driver = {
d5ed4c2e MD	500	.probe = sh_mtu2_probe,
d5ed4c2e MD	501	.driver = {
d5ed4c2e MD	502	.name = "sh_mtu2",
cca8d059	503	.of_match_table = of_match_ptr(sh_mtu2_of_table),
78012e38	504	.suppress_bind_attrs = true,
faf3f4f8 LP	505	},
faf3f4f8 LP	506	.id_table = sh_mtu2_id_table,
d5ed4c2e MD	507	};
	508
	509	static int __init sh_mtu2_init(void)
	510	{
	511	return platform_driver_register(&sh_mtu2_device_driver);
	512	}
	513
	514	static void __exit sh_mtu2_exit(void)
	515	{
	516	platform_driver_unregister(&sh_mtu2_device_driver);
	517	}
	518
507fd01d	519	#ifdef CONFIG_SUPERH
201e9109	520	sh_early_platform_init("earlytimer", &sh_mtu2_device_driver);
507fd01d BG	521	#endif
507fd01d BG	522
342896a5	523	subsys_initcall(sh_mtu2_init);
d5ed4c2e MD	524	module_exit(sh_mtu2_exit);
	525
	526	MODULE_AUTHOR("Magnus Damm");
	527	MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");