[linux.git] / drivers / clk / qcom / clk-alpha-pll.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */

#ifndef __QCOM_CLK_ALPHA_PLL_H__
#define __QCOM_CLK_ALPHA_PLL_H__

#include <linux/clk-provider.h>
#include "clk-regmap.h"

/* Alpha PLL types */
enum {
	CLK_ALPHA_PLL_TYPE_DEFAULT,
	CLK_ALPHA_PLL_TYPE_HUAYRA,
	CLK_ALPHA_PLL_TYPE_BRAMMO,
	CLK_ALPHA_PLL_TYPE_FABIA,
	CLK_ALPHA_PLL_TYPE_MAX,
};

enum {
	PLL_OFF_L_VAL,
	PLL_OFF_ALPHA_VAL,
	PLL_OFF_ALPHA_VAL_U,
	PLL_OFF_USER_CTL,
	PLL_OFF_USER_CTL_U,
	PLL_OFF_CONFIG_CTL,
	PLL_OFF_CONFIG_CTL_U,
	PLL_OFF_TEST_CTL,
	PLL_OFF_TEST_CTL_U,
	PLL_OFF_STATUS,
	PLL_OFF_OPMODE,
	PLL_OFF_FRAC,
	PLL_OFF_MAX_REGS
};

extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];

struct pll_vco {
	unsigned long min_freq;
	unsigned long max_freq;
	u32 val;
};

/**
 * struct clk_alpha_pll - phase locked loop (PLL)
 * @offset: base address of registers
 * @vco_table: array of VCO settings
 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
 * @clkr: regmap clock handle
 */
struct clk_alpha_pll {
	u32 offset;
	const u8 *regs;

	const struct pll_vco *vco_table;
	size_t num_vco;
#define SUPPORTS_OFFLINE_REQ	BIT(0)
#define SUPPORTS_FSM_MODE	BIT(2)
#define SUPPORTS_DYNAMIC_UPDATE	BIT(3)
	u8 flags;

	struct clk_regmap clkr;
};

/**
 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
 * @offset: base address of registers
 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
 * @width: width of post-divider
 * @post_div_shift: shift to differentiate between odd & even post-divider
 * @post_div_table: table with PLL odd and even post-divider settings
 * @num_post_div: Number of PLL post-divider settings
 *
 * @clkr: regmap clock handle
 */
struct clk_alpha_pll_postdiv {
	u32 offset;
	u8 width;
	const u8 *regs;

	struct clk_regmap clkr;
	int post_div_shift;
	const struct clk_div_table *post_div_table;
	size_t num_post_div;
};

struct alpha_pll_config {
	u32 l;
	u32 alpha;
	u32 alpha_hi;
	u32 config_ctl_val;
	u32 config_ctl_hi_val;
	u32 main_output_mask;
	u32 aux_output_mask;
	u32 aux2_output_mask;
	u32 early_output_mask;
	u32 alpha_en_mask;
	u32 alpha_mode_mask;
	u32 pre_div_val;
	u32 pre_div_mask;
	u32 post_div_val;
	u32 post_div_mask;
	u32 vco_val;
	u32 vco_mask;
};

extern const struct clk_ops clk_alpha_pll_ops;
extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
extern const struct clk_ops clk_alpha_pll_huayra_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;

extern const struct clk_ops clk_alpha_pll_fabia_ops;
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;

void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
			     const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
				const struct alpha_pll_config *config);

#endif
Commit	Line	Data
f9419783 TD	1	/* SPDX-License-Identifier: GPL-2.0 */
f9419783 TD	2	/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
8ff1f4c4 SB	3
	4	#ifndef __QCOM_CLK_ALPHA_PLL_H__
	5	#define __QCOM_CLK_ALPHA_PLL_H__
	6
	7	#include <linux/clk-provider.h>
	8	#include "clk-regmap.h"
	9
28d3f06e AS	10	/* Alpha PLL types */
	11	enum {
	12	CLK_ALPHA_PLL_TYPE_DEFAULT,
134b55b7	13	CLK_ALPHA_PLL_TYPE_HUAYRA,
c23e8a1f	14	CLK_ALPHA_PLL_TYPE_BRAMMO,
687d7a0c	15	CLK_ALPHA_PLL_TYPE_FABIA,
28d3f06e AS	16	CLK_ALPHA_PLL_TYPE_MAX,
	17	};
	18
	19	enum {
	20	PLL_OFF_L_VAL,
	21	PLL_OFF_ALPHA_VAL,
	22	PLL_OFF_ALPHA_VAL_U,
	23	PLL_OFF_USER_CTL,
	24	PLL_OFF_USER_CTL_U,
	25	PLL_OFF_CONFIG_CTL,
	26	PLL_OFF_CONFIG_CTL_U,
	27	PLL_OFF_TEST_CTL,
	28	PLL_OFF_TEST_CTL_U,
	29	PLL_OFF_STATUS,
687d7a0c AN	30	PLL_OFF_OPMODE,
687d7a0c AN	31	PLL_OFF_FRAC,
28d3f06e AS	32	PLL_OFF_MAX_REGS
	33	};
	34
	35	extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
	36
8ff1f4c4 SB	37	struct pll_vco {
	38	unsigned long min_freq;
	39	unsigned long max_freq;
	40	u32 val;
	41	};
	42
	43	/**
	44	* struct clk_alpha_pll - phase locked loop (PLL)
	45	* @offset: base address of registers
	46	* @vco_table: array of VCO settings
28d3f06e	47	* @regs: alpha pll register map (see @clk_alpha_pll_regs)
8ff1f4c4 SB	48	* @clkr: regmap clock handle
	49	*/
	50	struct clk_alpha_pll {
	51	u32 offset;
28d3f06e	52	const u8 *regs;
8ff1f4c4 SB	53
	54	const struct pll_vco *vco_table;
	55	size_t num_vco;
feb65645	56	#define SUPPORTS_OFFLINE_REQ BIT(0)
400d9fda	57	#define SUPPORTS_FSM_MODE BIT(2)
472796de	58	#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
feb65645	59	u8 flags;
8ff1f4c4 SB	60
	61	struct clk_regmap clkr;
	62	};
	63
	64	/**
	65	* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
	66	* @offset: base address of registers
28d3f06e	67	* @regs: alpha pll register map (see @clk_alpha_pll_regs)
8ff1f4c4	68	* @width: width of post-divider
687d7a0c AN	69	* @post_div_shift: shift to differentiate between odd & even post-divider
	70	* @post_div_table: table with PLL odd and even post-divider settings
	71	* @num_post_div: Number of PLL post-divider settings
	72	*
8ff1f4c4 SB	73	* @clkr: regmap clock handle
	74	*/
	75	struct clk_alpha_pll_postdiv {
	76	u32 offset;
	77	u8 width;
28d3f06e	78	const u8 *regs;
8ff1f4c4 SB	79
8ff1f4c4 SB	80	struct clk_regmap clkr;
687d7a0c AN	81	int post_div_shift;
	82	const struct clk_div_table *post_div_table;
	83	size_t num_post_div;
8ff1f4c4 SB	84	};
8ff1f4c4 SB	85
9f4e6277 RN	86	struct alpha_pll_config {
	87	u32 l;
	88	u32 alpha;
c45ae598	89	u32 alpha_hi;
9f4e6277 RN	90	u32 config_ctl_val;
	91	u32 config_ctl_hi_val;
	92	u32 main_output_mask;
	93	u32 aux_output_mask;
	94	u32 aux2_output_mask;
	95	u32 early_output_mask;
c45ae598 AS	96	u32 alpha_en_mask;
c45ae598 AS	97	u32 alpha_mode_mask;
9f4e6277 RN	98	u32 pre_div_val;
	99	u32 pre_div_mask;
	100	u32 post_div_val;
	101	u32 post_div_mask;
	102	u32 vco_val;
	103	u32 vco_mask;
	104	};
	105
8ff1f4c4	106	extern const struct clk_ops clk_alpha_pll_ops;
feb65645	107	extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
8ff1f4c4	108	extern const struct clk_ops clk_alpha_pll_postdiv_ops;
134b55b7	109	extern const struct clk_ops clk_alpha_pll_huayra_ops;
23c68cc9	110	extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
8ff1f4c4	111
687d7a0c AN	112	extern const struct clk_ops clk_alpha_pll_fabia_ops;
	113	extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
	114	extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
	115
9f4e6277 RN	116	void clk_alpha_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
9f4e6277 RN	117	const struct alpha_pll_config *config);
687d7a0c AN	118	void clk_fabia_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
687d7a0c AN	119	const struct alpha_pll_config *config);
9f4e6277	120
8ff1f4c4	121	#endif