[linux.git] / arch / arm / common / timer-sp.c

/*
 *  linux/arch/arm/common/timer-sp.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>

static long __init sp804_get_clock_rate(struct clk *clk)
{
	long rate;
	int err;

	err = clk_prepare(clk);
	if (err) {
		pr_err("sp804: clock failed to prepare: %d\n", err);
		clk_put(clk);
		return err;
	}

	err = clk_enable(clk);
	if (err) {
		pr_err("sp804: clock failed to enable: %d\n", err);
		clk_unprepare(clk);
		clk_put(clk);
		return err;
	}

	rate = clk_get_rate(clk);
	if (rate < 0) {
		pr_err("sp804: clock failed to get rate: %ld\n", rate);
		clk_disable(clk);
		clk_unprepare(clk);
		clk_put(clk);
	}

	return rate;
}

static void __iomem *sched_clock_base;

static u32 sp804_read(void)
{
	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
}

void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
						     const char *name,
						     struct clk *clk,
						     int use_sched_clock)
{
	long rate;

	if (!clk) {
		clk = clk_get_sys("sp804", name);
		if (IS_ERR(clk)) {
			pr_err("sp804: clock not found: %d\n",
			       (int)PTR_ERR(clk));
			return;
		}
	}

	rate = sp804_get_clock_rate(clk);

	if (rate < 0)
		return;

	/* setup timer 0 as free-running clocksource */
	writel(0, base + TIMER_CTRL);
	writel(0xffffffff, base + TIMER_LOAD);
	writel(0xffffffff, base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, name,
		rate, 200, 32, clocksource_mmio_readl_down);

	if (use_sched_clock) {
		sched_clock_base = base;
		setup_sched_clock(sp804_read, 32, rate);
	}
}


static void __iomem *clkevt_base;
static unsigned long clkevt_reload;

/*
 * IRQ handler for the timer
 */
static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static void sp804_set_mode(enum clock_event_mode mode,
	struct clock_event_device *evt)
{
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;

	writel(ctrl, clkevt_base + TIMER_CTRL);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		writel(clkevt_reload, clkevt_base + TIMER_LOAD);
		ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl |= TIMER_CTRL_ONESHOT;
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		break;
	}

	writel(ctrl, clkevt_base + TIMER_CTRL);
}

static int sp804_set_next_event(unsigned long next,
	struct clock_event_device *evt)
{
	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);

	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device sp804_clockevent = {
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
		CLOCK_EVT_FEAT_DYNIRQ,
	.set_mode	= sp804_set_mode,
	.set_next_event	= sp804_set_next_event,
	.rating		= 300,
};

static struct irqaction sp804_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= sp804_timer_interrupt,
	.dev_id		= &sp804_clockevent,
};

void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
{
	struct clock_event_device *evt = &sp804_clockevent;
	long rate;

	if (!clk)
		clk = clk_get_sys("sp804", name);
	if (IS_ERR(clk)) {
		pr_err("sp804: %s clock not found: %d\n", name,
			(int)PTR_ERR(clk));
		return;
	}

	rate = sp804_get_clock_rate(clk);
	if (rate < 0)
		return;

	clkevt_base = base;
	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
	evt->name = name;
	evt->irq = irq;
	evt->cpumask = cpu_possible_mask;

	writel(0, base + TIMER_CTRL);

	setup_irq(irq, &sp804_timer_irq);
	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
}

static void __init sp804_of_init(struct device_node *np)
{
	static bool initialized = false;
	void __iomem *base;
	int irq;
	u32 irq_num = 0;
	struct clk *clk1, *clk2;
	const char *name = of_get_property(np, "compatible", NULL);

	base = of_iomap(np, 0);
	if (WARN_ON(!base))
		return;

	/* Ensure timers are disabled */
	writel(0, base + TIMER_CTRL);
	writel(0, base + TIMER_2_BASE + TIMER_CTRL);

	if (initialized || !of_device_is_available(np))
		goto err;

	clk1 = of_clk_get(np, 0);
	if (IS_ERR(clk1))
		clk1 = NULL;

	/* Get the 2nd clock if the timer has 2 timer clocks */
	if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
		clk2 = of_clk_get(np, 1);
		if (IS_ERR(clk2)) {
			pr_err("sp804: %s clock not found: %d\n", np->name,
				(int)PTR_ERR(clk2));
			goto err;
		}
	} else
		clk2 = clk1;

	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0)
		goto err;

	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
	if (irq_num == 2) {
		__sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
		__sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
	} else {
		__sp804_clockevents_init(base, irq, clk1 , name);
		__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
							 name, clk2, 1);
	}
	initialized = true;

	return;
err:
	iounmap(base);
}
CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);

static void __init integrator_cp_of_init(struct device_node *np)
{
	static int init_count = 0;
	void __iomem *base;
	int irq;
	const char *name = of_get_property(np, "compatible", NULL);

	base = of_iomap(np, 0);
	if (WARN_ON(!base))
		return;

	/* Ensure timer is disabled */
	writel(0, base + TIMER_CTRL);

	if (init_count == 2 || !of_device_is_available(np))
		goto err;

	if (!init_count)
		sp804_clocksource_init(base, name);
	else {
		irq = irq_of_parse_and_map(np, 0);
		if (irq <= 0)
			goto err;

		sp804_clockevents_init(base, irq, name);
	}

	init_count++;
	return;
err:
	iounmap(base);
}
CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
Commit	Line	Data
e3887714	1	/*
8a9618f5	2	* linux/arch/arm/common/timer-sp.c
e3887714 RK	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
7ff550de	21	#include <linux/clk.h>
e3887714 RK	22	#include <linux/clocksource.h>
e3887714 RK	23	#include <linux/clockchips.h>
7ff550de	24	#include <linux/err.h>
e3887714 RK	25	#include <linux/interrupt.h>
	26	#include <linux/irq.h>
	27	#include <linux/io.h>
7a0eca71 RH	28	#include <linux/of.h>
	29	#include <linux/of_address.h>
	30	#include <linux/of_irq.h>
38ff87f7	31	#include <linux/sched_clock.h>
e3887714 RK	32
e3887714 RK	33	#include <asm/hardware/arm_timer.h>
870e2928	34	#include <asm/hardware/timer-sp.h>
e3887714	35
7a0eca71	36	static long __init sp804_get_clock_rate(struct clk *clk)
7ff550de	37	{
7ff550de RK	38	long rate;
	39	int err;
	40
6f5ad963 RK	41	err = clk_prepare(clk);
6f5ad963 RK	42	if (err) {
7a0eca71	43	pr_err("sp804: clock failed to prepare: %d\n", err);
6f5ad963 RK	44	clk_put(clk);
	45	return err;
	46	}
	47
7ff550de RK	48	err = clk_enable(clk);
7ff550de RK	49	if (err) {
7a0eca71	50	pr_err("sp804: clock failed to enable: %d\n", err);
6f5ad963	51	clk_unprepare(clk);
7ff550de RK	52	clk_put(clk);
	53	return err;
	54	}
	55
	56	rate = clk_get_rate(clk);
	57	if (rate < 0) {
7a0eca71	58	pr_err("sp804: clock failed to get rate: %ld\n", rate);
7ff550de	59	clk_disable(clk);
6f5ad963	60	clk_unprepare(clk);
7ff550de RK	61	clk_put(clk);
	62	}
	63
	64	return rate;
	65	}
	66
a7bf6162 RH	67	static void __iomem *sched_clock_base;
	68
	69	static u32 sp804_read(void)
	70	{
	71	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
	72	}
	73
	74	void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
	75	const char *name,
7a0eca71	76	struct clk *clk,
a7bf6162	77	int use_sched_clock)
e3887714	78	{
7a0eca71 RH	79	long rate;
	80
	81	if (!clk) {
	82	clk = clk_get_sys("sp804", name);
	83	if (IS_ERR(clk)) {
	84	pr_err("sp804: clock not found: %d\n",
	85	(int)PTR_ERR(clk));
	86	return;
	87	}
	88	}
	89
	90	rate = sp804_get_clock_rate(clk);
7ff550de RK	91
	92	if (rate < 0)
	93	return;
	94
e3887714	95	/* setup timer 0 as free-running clocksource */
bfe45e0b RK	96	writel(0, base + TIMER_CTRL);
	97	writel(0xffffffff, base + TIMER_LOAD);
	98	writel(0xffffffff, base + TIMER_VALUE);
e3887714	99	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
bfe45e0b	100	base + TIMER_CTRL);
e3887714	101
fb593cf3	102	clocksource_mmio_init(base + TIMER_VALUE, name,
7ff550de	103	rate, 200, 32, clocksource_mmio_readl_down);
a7bf6162 RH	104
	105	if (use_sched_clock) {
	106	sched_clock_base = base;
	107	setup_sched_clock(sp804_read, 32, rate);
	108	}
e3887714 RK	109	}
	110
	111
	112	static void __iomem *clkevt_base;
23828a7a	113	static unsigned long clkevt_reload;
e3887714 RK	114
	115	/*
	116	* IRQ handler for the timer
	117	*/
	118	static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
	119	{
	120	struct clock_event_device *evt = dev_id;
	121
	122	/* clear the interrupt */
	123	writel(1, clkevt_base + TIMER_INTCLR);
	124
	125	evt->event_handler(evt);
	126
	127	return IRQ_HANDLED;
	128	}
	129
	130	static void sp804_set_mode(enum clock_event_mode mode,
	131	struct clock_event_device *evt)
	132	{
	133	unsigned long ctrl = TIMER_CTRL_32BIT \| TIMER_CTRL_IE;
	134
	135	writel(ctrl, clkevt_base + TIMER_CTRL);
	136
	137	switch (mode) {
	138	case CLOCK_EVT_MODE_PERIODIC:
23828a7a	139	writel(clkevt_reload, clkevt_base + TIMER_LOAD);
e3887714 RK	140	ctrl \|= TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
	141	break;
	142
	143	case CLOCK_EVT_MODE_ONESHOT:
	144	/* period set, and timer enabled in 'next_event' hook */
	145	ctrl \|= TIMER_CTRL_ONESHOT;
	146	break;
	147
	148	case CLOCK_EVT_MODE_UNUSED:
	149	case CLOCK_EVT_MODE_SHUTDOWN:
	150	default:
	151	break;
	152	}
	153
	154	writel(ctrl, clkevt_base + TIMER_CTRL);
	155	}
	156
	157	static int sp804_set_next_event(unsigned long next,
	158	struct clock_event_device *evt)
	159	{
	160	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
	161
	162	writel(next, clkevt_base + TIMER_LOAD);
	163	writel(ctrl \| TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
	164
	165	return 0;
	166	}
	167
	168	static struct clock_event_device sp804_clockevent = {
887708f0 VK	169	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT \|
887708f0 VK	170	CLOCK_EVT_FEAT_DYNIRQ,
e3887714 RK	171	.set_mode = sp804_set_mode,
	172	.set_next_event = sp804_set_next_event,
	173	.rating = 300,
e3887714 RK	174	};
	175
	176	static struct irqaction sp804_timer_irq = {
	177	.name = "timer",
728fae6f	178	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
e3887714 RK	179	.handler = sp804_timer_interrupt,
	180	.dev_id = &sp804_clockevent,
	181	};
	182
7a0eca71	183	void __init __sp804_clockevents_init(void __iomem base, unsigned int irq, struct clk clk, const char *name)
e3887714 RK	184	{
e3887714 RK	185	struct clock_event_device *evt = &sp804_clockevent;
7a0eca71 RH	186	long rate;
	187
	188	if (!clk)
	189	clk = clk_get_sys("sp804", name);
	190	if (IS_ERR(clk)) {
	191	pr_err("sp804: %s clock not found: %d\n", name,
	192	(int)PTR_ERR(clk));
	193	return;
	194	}
23828a7a	195
7a0eca71	196	rate = sp804_get_clock_rate(clk);
23828a7a RK	197	if (rate < 0)
23828a7a RK	198	return;
e3887714 RK	199
e3887714 RK	200	clkevt_base = base;
23828a7a	201	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
57cc4f7d RK	202	evt->name = name;
57cc4f7d RK	203	evt->irq = irq;
ea3aacf5	204	evt->cpumask = cpu_possible_mask;
e3887714	205
7a0eca71 RH	206	writel(0, base + TIMER_CTRL);
7a0eca71 RH	207
57cc4f7d	208	setup_irq(irq, &sp804_timer_irq);
7c324d83	209	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
e3887714	210	}
7a0eca71 RH	211
	212	static void __init sp804_of_init(struct device_node *np)
	213	{
	214	static bool initialized = false;
	215	void __iomem *base;
	216	int irq;
	217	u32 irq_num = 0;
	218	struct clk clk1, clk2;
	219	const char *name = of_get_property(np, "compatible", NULL);
	220
	221	base = of_iomap(np, 0);
	222	if (WARN_ON(!base))
	223	return;
	224
	225	/* Ensure timers are disabled */
	226	writel(0, base + TIMER_CTRL);
	227	writel(0, base + TIMER_2_BASE + TIMER_CTRL);
	228
	229	if (initialized \|\| !of_device_is_available(np))
	230	goto err;
	231
	232	clk1 = of_clk_get(np, 0);
	233	if (IS_ERR(clk1))
	234	clk1 = NULL;
	235
	236	/* Get the 2nd clock if the timer has 2 timer clocks */
	237	if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
	238	clk2 = of_clk_get(np, 1);
	239	if (IS_ERR(clk2)) {
	240	pr_err("sp804: %s clock not found: %d\n", np->name,
	241	(int)PTR_ERR(clk2));
	242	goto err;
	243	}
	244	} else
	245	clk2 = clk1;
	246
	247	irq = irq_of_parse_and_map(np, 0);
	248	if (irq <= 0)
	249	goto err;
	250
	251	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
	252	if (irq_num == 2) {
	253	__sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
	254	__sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
	255	} else {
	256	__sp804_clockevents_init(base, irq, clk1 , name);
	257	__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
	258	name, clk2, 1);
	259	}
	260	initialized = true;
	261
	262	return;
	263	err:
	264	iounmap(base);
	265	}
	266	CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
870e2928 RH	267
	268	static void __init integrator_cp_of_init(struct device_node *np)
	269	{
	270	static int init_count = 0;
	271	void __iomem *base;
	272	int irq;
	273	const char *name = of_get_property(np, "compatible", NULL);
	274
	275	base = of_iomap(np, 0);
	276	if (WARN_ON(!base))
	277	return;
	278
	279	/* Ensure timer is disabled */
	280	writel(0, base + TIMER_CTRL);
	281
	282	if (init_count == 2 \|\| !of_device_is_available(np))
	283	goto err;
	284
	285	if (!init_count)
	286	sp804_clocksource_init(base, name);
	287	else {
	288	irq = irq_of_parse_and_map(np, 0);
	289	if (irq <= 0)
	290	goto err;
	291
	292	sp804_clockevents_init(base, irq, name);
	293	}
	294
	295	init_count++;
	296	return;
	297	err:
	298	iounmap(base);
	299	}
	300	CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);