[linux.git] / drivers / ata / pata_cmd64x.c

/*
 * pata_cmd64x.c 	- CMD64x PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <[email protected]>
 *
 * Based upon
 * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  ([email protected])
 * Copyright (C) 1998		David S. Miller ([email protected])
 *
 * Copyright (C) 1999-2002	Andre Hedrick <[email protected]>
 *
 * TODO
 *	Testing work
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_cmd64x"
#define DRV_VERSION "0.2.5"

/*
 * CMD64x specific registers definition.
 */

enum {
	CFR 		= 0x50,
		CFR_INTR_CH0  = 0x02,
	CNTRL 		= 0x51,
		CNTRL_DIS_RA0 = 0x40,
		CNTRL_DIS_RA1 = 0x80,
		CNTRL_ENA_2ND = 0x08,
	CMDTIM 		= 0x52,
	ARTTIM0 	= 0x53,
	DRWTIM0 	= 0x54,
	ARTTIM1 	= 0x55,
	DRWTIM1 	= 0x56,
	ARTTIM23 	= 0x57,
		ARTTIM23_DIS_RA2  = 0x04,
		ARTTIM23_DIS_RA3  = 0x08,
		ARTTIM23_INTR_CH1 = 0x10,
	ARTTIM2 	= 0x57,
	ARTTIM3 	= 0x57,
	DRWTIM23	= 0x58,
	DRWTIM2 	= 0x58,
	BRST 		= 0x59,
	DRWTIM3 	= 0x5b,
	BMIDECR0	= 0x70,
	MRDMODE		= 0x71,
		MRDMODE_INTR_CH0 = 0x04,
		MRDMODE_INTR_CH1 = 0x08,
		MRDMODE_BLK_CH0  = 0x10,
		MRDMODE_BLK_CH1	 = 0x20,
	BMIDESR0	= 0x72,
	UDIDETCR0	= 0x73,
	DTPR0		= 0x74,
	BMIDECR1	= 0x78,
	BMIDECSR	= 0x79,
	BMIDESR1	= 0x7A,
	UDIDETCR1	= 0x7B,
	DTPR1		= 0x7C
};

static int cmd648_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 r;

	/* Check cable detect bits */
	pci_read_config_byte(pdev, BMIDECSR, &r);
	if (r & (1 << ap->port_no))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	cmd64x_set_piomode	-	set PIO and MWDMA timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: mode
 *
 *	Called to do the PIO and MWDMA mode setup.
 */

static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_timing t;
	const unsigned long T = 1000000 / 33;
	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };

	u8 reg;

	/* Port layout is not logical so use a table */
	const u8 arttim_port[2][2] = {
		{ ARTTIM0, ARTTIM1 },
		{ ARTTIM23, ARTTIM23 }
	};
	const u8 drwtim_port[2][2] = {
		{ DRWTIM0, DRWTIM1 },
		{ DRWTIM2, DRWTIM3 }
	};

	int arttim = arttim_port[ap->port_no][adev->devno];
	int drwtim = drwtim_port[ap->port_no][adev->devno];

	/* ata_timing_compute is smart and will produce timings for MWDMA
	   that don't violate the drives PIO capabilities. */
	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
		return;
	}
	if (ap->port_no) {
		/* Slave has shared address setup */
		struct ata_device *pair = ata_dev_pair(adev);

		if (pair) {
			struct ata_timing tp;
			ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
			ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
		}
	}

	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
		t.active, t.recover, t.setup);
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)
		t.active = 16;

	/* Now convert the clocks into values we can actually stuff into
	   the chip */

	if (t.recover > 1)
		t.recover--;
	else
		t.recover = 15;

	if (t.setup > 4)
		t.setup = 0xC0;
	else
		t.setup = setup_data[t.setup];

	t.active &= 0x0F;	/* 0 = 16 */

	/* Load setup timing */
	pci_read_config_byte(pdev, arttim, &reg);
	reg &= 0x3F;
	reg |= t.setup;
	pci_write_config_byte(pdev, arttim, reg);

	/* Load active/recovery */
	pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}

/**
 *	cmd64x_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Used when configuring the devices ot set the PIO timings. All the
 *	actual work is done by the PIO/MWDMA setting helper
 */

static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	cmd64x_set_timing(ap, adev, adev->pio_mode);
}

/**
 *	cmd64x_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup.
 */

static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 udma_data[] = {
		0x30, 0x20, 0x10, 0x20, 0x10, 0x00
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 regU, regD;

	int pciU = UDIDETCR0 + 8 * ap->port_no;
	int pciD = BMIDESR0 + 8 * ap->port_no;
	int shift = 2 * adev->devno;

	pci_read_config_byte(pdev, pciD, &regD);
	pci_read_config_byte(pdev, pciU, &regU);

	/* DMA bits off */
	regD &= ~(0x20 << adev->devno);
	/* DMA control bits */
	regU &= ~(0x30 << shift);
	/* DMA timing bits */
	regU &= ~(0x05 << adev->devno);

	if (adev->dma_mode >= XFER_UDMA_0) {
		/* Merge the timing value */
		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
		/* Merge the control bits */
		regU |= 1 << adev->devno; /* UDMA on */
		if (adev->dma_mode > 2)	/* 15nS timing */
			regU |= 4 << adev->devno;
	} else {
		regU &= ~ (1 << adev->devno);	/* UDMA off */
		cmd64x_set_timing(ap, adev, adev->dma_mode);
	}

	regD |= 0x20 << adev->devno;

	pci_write_config_byte(pdev, pciU, regU);
	pci_write_config_byte(pdev, pciD, regD);
}

/**
 *	cmd648_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	DMA has completed.
 */

static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 dma_intr;
	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
	int dma_reg = ap->port_no ? ARTTIM2 : CFR;

	ata_bmdma_stop(qc);

	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}

/**
 *	cmd646r1_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	Stub for now while investigating the r1 quirk in the old driver.
 */

static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
{
	ata_bmdma_stop(qc);
}

static struct scsi_host_template cmd64x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations cmd64x_base_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
};

static struct ata_port_operations cmd64x_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd646r1_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.bmdma_stop	= cmd646r1_bmdma_stop,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd648_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.bmdma_stop	= cmd648_bmdma_stop,
	.cable_detect	= cmd648_cable_detect,
};

static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	u32 class_rev;

	static const struct ata_port_info cmd_info[6] = {
		{	/* CMD 643 - no UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with broken UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with working UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 rev 1  */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd646r1_port_ops
		},
		{	/* CMD 648 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &cmd648_port_ops
		},
		{	/* CMD 649 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &cmd648_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
	u8 mrdmode;
	int rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xFF;

	if (id->driver_data == 0)	/* 643 */
		ata_pci_bmdma_clear_simplex(pdev);

	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
		/* Does UDMA work ? */
		if (class_rev > 4)
			ppi[0] = &cmd_info[2];
		/* Early rev with other problems ? */
		else if (class_rev == 1)
			ppi[0] = &cmd_info[3];
	}

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);

	/* Force PIO 0 here.. */

	/* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif

	return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL);
}

#ifdef CONFIG_PM
static int cmd64x_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	u8 mrdmode;
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id cmd64x[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },

	{ },
};

static struct pci_driver cmd64x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cmd64x,
	.probe 		= cmd64x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cmd64x_reinit_one,
#endif
};

static int __init cmd64x_init(void)
{
	return pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cmd64x);
MODULE_VERSION(DRV_VERSION);

module_init(cmd64x_init);
module_exit(cmd64x_exit);
Commit	Line	Data
669a5db4	1	/*
fb9f8905	2	* pata_cmd64x.c - CMD64x PATA for new ATA layer
669a5db4	3	* (C) 2005 Red Hat Inc
ab771630	4	* Alan Cox <[email protected]>
669a5db4 JG	5	*
	6	* Based upon
	7	* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
	8	*
	9	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
	10	* Note, this driver is not used at all on other systems because
	11	* there the "BIOS" has done all of the following already.
	12	* Due to massive hardware bugs, UltraDMA is only supported
	13	* on the 646U2 and not on the 646U.
	14	*
	15	* Copyright (C) 1998 Eddie C. Dost ([email protected])
	16	* Copyright (C) 1998 David S. Miller ([email protected])
	17	*
	18	* Copyright (C) 1999-2002 Andre Hedrick <[email protected]>
	19	*
	20	* TODO
	21	* Testing work
	22	*/
85cd7251	23
669a5db4 JG	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/pci.h>
	27	#include <linux/init.h>
	28	#include <linux/blkdev.h>
	29	#include <linux/delay.h>
	30	#include <scsi/scsi_host.h>
	31	#include <linux/libata.h>
	32
	33	#define DRV_NAME "pata_cmd64x"
05d1efff	34	#define DRV_VERSION "0.2.5"
669a5db4 JG	35
	36	/*
	37	* CMD64x specific registers definition.
	38	*/
85cd7251	39
669a5db4 JG	40	enum {
	41	CFR = 0x50,
	42	CFR_INTR_CH0 = 0x02,
	43	CNTRL = 0x51,
	44	CNTRL_DIS_RA0 = 0x40,
	45	CNTRL_DIS_RA1 = 0x80,
	46	CNTRL_ENA_2ND = 0x08,
	47	CMDTIM = 0x52,
	48	ARTTIM0 = 0x53,
	49	DRWTIM0 = 0x54,
	50	ARTTIM1 = 0x55,
	51	DRWTIM1 = 0x56,
	52	ARTTIM23 = 0x57,
	53	ARTTIM23_DIS_RA2 = 0x04,
	54	ARTTIM23_DIS_RA3 = 0x08,
	55	ARTTIM23_INTR_CH1 = 0x10,
	56	ARTTIM2 = 0x57,
	57	ARTTIM3 = 0x57,
	58	DRWTIM23 = 0x58,
	59	DRWTIM2 = 0x58,
	60	BRST = 0x59,
	61	DRWTIM3 = 0x5b,
	62	BMIDECR0 = 0x70,
	63	MRDMODE = 0x71,
	64	MRDMODE_INTR_CH0 = 0x04,
	65	MRDMODE_INTR_CH1 = 0x08,
	66	MRDMODE_BLK_CH0 = 0x10,
	67	MRDMODE_BLK_CH1 = 0x20,
	68	BMIDESR0 = 0x72,
	69	UDIDETCR0 = 0x73,
	70	DTPR0 = 0x74,
	71	BMIDECR1 = 0x78,
	72	BMIDECSR = 0x79,
	73	BMIDESR1 = 0x7A,
	74	UDIDETCR1 = 0x7B,
	75	DTPR1 = 0x7C
	76	};
	77
a73984a0	78	static int cmd648_cable_detect(struct ata_port *ap)
669a5db4 JG	79	{
	80	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	81	u8 r;
	82
	83	/* Check cable detect bits */
	84	pci_read_config_byte(pdev, BMIDECSR, &r);
	85	if (r & (1 << ap->port_no))
a73984a0 JG	86	return ATA_CBL_PATA80;
a73984a0 JG	87	return ATA_CBL_PATA40;
669a5db4 JG	88	}
	89
	90	/**
05d1efff	91	* cmd64x_set_piomode - set PIO and MWDMA timing
669a5db4 JG	92	* @ap: ATA interface
669a5db4 JG	93	* @adev: ATA device
05d1efff	94	* @mode: mode
669a5db4	95	*
05d1efff	96	* Called to do the PIO and MWDMA mode setup.
669a5db4	97	*/
85cd7251	98
05d1efff	99	static void cmd64x_set_timing(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	100	{
	101	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	102	struct ata_timing t;
	103	const unsigned long T = 1000000 / 33;
	104	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
85cd7251	105
669a5db4	106	u8 reg;
85cd7251	107
669a5db4	108	/* Port layout is not logical so use a table */
85cd7251	109	const u8 arttim_port[2][2] = {
669a5db4 JG	110	{ ARTTIM0, ARTTIM1 },
	111	{ ARTTIM23, ARTTIM23 }
	112	};
	113	const u8 drwtim_port[2][2] = {
	114	{ DRWTIM0, DRWTIM1 },
	115	{ DRWTIM2, DRWTIM3 }
	116	};
85cd7251	117
669a5db4 JG	118	int arttim = arttim_port[ap->port_no][adev->devno];
669a5db4 JG	119	int drwtim = drwtim_port[ap->port_no][adev->devno];
85cd7251	120
05d1efff AC	121	/* ata_timing_compute is smart and will produce timings for MWDMA
	122	that don't violate the drives PIO capabilities. */
	123	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
669a5db4 JG	124	printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
	125	return;
	126	}
	127	if (ap->port_no) {
	128	/* Slave has shared address setup */
	129	struct ata_device *pair = ata_dev_pair(adev);
85cd7251	130
669a5db4 JG	131	if (pair) {
	132	struct ata_timing tp;
	133	ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
	134	ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
	135	}
	136	}
85cd7251	137
669a5db4 JG	138	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
	139	t.active, t.recover, t.setup);
	140	if (t.recover > 16) {
	141	t.active += t.recover - 16;
	142	t.recover = 16;
	143	}
	144	if (t.active > 16)
	145	t.active = 16;
85cd7251	146
669a5db4 JG	147	/* Now convert the clocks into values we can actually stuff into
669a5db4 JG	148	the chip */
85cd7251	149
669a5db4 JG	150	if (t.recover > 1)
	151	t.recover--;
	152	else
	153	t.recover = 15;
85cd7251	154
669a5db4 JG	155	if (t.setup > 4)
	156	t.setup = 0xC0;
	157	else
	158	t.setup = setup_data[t.setup];
85cd7251	159
669a5db4	160	t.active &= 0x0F; /* 0 = 16 */
85cd7251	161
669a5db4 JG	162	/* Load setup timing */
	163	pci_read_config_byte(pdev, arttim, &reg);
	164	reg &= 0x3F;
	165	reg \|= t.setup;
	166	pci_write_config_byte(pdev, arttim, reg);
85cd7251	167
669a5db4	168	/* Load active/recovery */
85cd7251	169	pci_write_config_byte(pdev, drwtim, (t.active << 4) \| t.recover);
669a5db4 JG	170	}
669a5db4 JG	171
05d1efff AC	172	/**
	173	* cmd64x_set_piomode - set initial PIO mode data
	174	* @ap: ATA interface
	175	* @adev: ATA device
	176	*
	177	* Used when configuring the devices ot set the PIO timings. All the
	178	* actual work is done by the PIO/MWDMA setting helper
	179	*/
	180
	181	static void cmd64x_set_piomode(struct ata_port ap, struct ata_device adev)
	182	{
	183	cmd64x_set_timing(ap, adev, adev->pio_mode);
	184	}
	185
669a5db4 JG	186	/**
	187	* cmd64x_set_dmamode - set initial DMA mode data
	188	* @ap: ATA interface
	189	* @adev: ATA device
	190	*
	191	* Called to do the DMA mode setup.
	192	*/
85cd7251	193
669a5db4 JG	194	static void cmd64x_set_dmamode(struct ata_port ap, struct ata_device adev)
	195	{
	196	static const u8 udma_data[] = {
6a40da02	197	0x30, 0x20, 0x10, 0x20, 0x10, 0x00
669a5db4	198	};
85cd7251	199
669a5db4 JG	200	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	201	u8 regU, regD;
	202
	203	int pciU = UDIDETCR0 + 8 * ap->port_no;
	204	int pciD = BMIDESR0 + 8 * ap->port_no;
	205	int shift = 2 * adev->devno;
85cd7251	206
669a5db4 JG	207	pci_read_config_byte(pdev, pciD, &regD);
	208	pci_read_config_byte(pdev, pciU, &regU);
	209
6a40da02 AC	210	/* DMA bits off */
	211	regD &= ~(0x20 << adev->devno);
	212	/* DMA control bits */
	213	regU &= ~(0x30 << shift);
	214	/* DMA timing bits */
	215	regU &= ~(0x05 << adev->devno);
85cd7251	216
6a40da02	217	if (adev->dma_mode >= XFER_UDMA_0) {
24b7ce98	218	/* Merge the timing value */
669a5db4	219	regU \|= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
6a40da02 AC	220	/* Merge the control bits */
	221	regU \|= 1 << adev->devno; /* UDMA on */
	222	if (adev->dma_mode > 2) /* 15nS timing */
	223	regU \|= 4 << adev->devno;
05d1efff AC	224	} else {
	225	regU &= ~ (1 << adev->devno); /* UDMA off */
	226	cmd64x_set_timing(ap, adev, adev->dma_mode);
	227	}
669a5db4 JG	228
	229	regD \|= 0x20 << adev->devno;
	230
	231	pci_write_config_byte(pdev, pciU, regU);
	232	pci_write_config_byte(pdev, pciD, regD);
	233	}
	234
	235	/**
	236	* cmd648_dma_stop - DMA stop callback
	237	* @qc: Command in progress
	238	*
	239	* DMA has completed.
	240	*/
	241
	242	static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
	243	{
	244	struct ata_port *ap = qc->ap;
	245	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	246	u8 dma_intr;
6a40da02 AC	247	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
6a40da02 AC	248	int dma_reg = ap->port_no ? ARTTIM2 : CFR;
85cd7251	249
669a5db4	250	ata_bmdma_stop(qc);
85cd7251	251
669a5db4 JG	252	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	253	pci_write_config_byte(pdev, dma_reg, dma_intr \| dma_mask);
	254	}
85cd7251	255
669a5db4 JG	256	/**
	257	* cmd646r1_dma_stop - DMA stop callback
	258	* @qc: Command in progress
	259	*
	260	* Stub for now while investigating the r1 quirk in the old driver.
	261	*/
	262
	263	static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
	264	{
	265	ata_bmdma_stop(qc);
	266	}
85cd7251	267
669a5db4	268	static struct scsi_host_template cmd64x_sht = {
68d1d07b	269	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	270	};
669a5db4 JG	271
029cfd6b TH	272	static const struct ata_port_operations cmd64x_base_ops = {
029cfd6b TH	273	.inherits = &ata_bmdma_port_ops,
669a5db4 JG	274	.set_piomode = cmd64x_set_piomode,
669a5db4 JG	275	.set_dmamode = cmd64x_set_dmamode,
85cd7251	276	};
669a5db4	277
029cfd6b TH	278	static struct ata_port_operations cmd64x_port_ops = {
029cfd6b TH	279	.inherits = &cmd64x_base_ops,
a73984a0	280	.cable_detect = ata_cable_40wire,
029cfd6b	281	};
669a5db4	282
029cfd6b TH	283	static struct ata_port_operations cmd646r1_port_ops = {
029cfd6b TH	284	.inherits = &cmd64x_base_ops,
669a5db4	285	.bmdma_stop = cmd646r1_bmdma_stop,
029cfd6b	286	.cable_detect = ata_cable_40wire,
85cd7251	287	};
669a5db4 JG	288
669a5db4 JG	289	static struct ata_port_operations cmd648_port_ops = {
029cfd6b	290	.inherits = &cmd64x_base_ops,
669a5db4	291	.bmdma_stop = cmd648_bmdma_stop,
029cfd6b	292	.cable_detect = cmd648_cable_detect,
85cd7251 JG	293	};
85cd7251 JG	294
669a5db4 JG	295	static int cmd64x_init_one(struct pci_dev pdev, const struct pci_device_id id)
	296	{
	297	u32 class_rev;
85cd7251	298
1626aeb8	299	static const struct ata_port_info cmd_info[6] = {
669a5db4	300	{ /* CMD 643 - no UDMA */
1d2808fd	301	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	302	.pio_mask = ATA_PIO4,
14bdef98 EIB	303	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	304	.port_ops = &cmd64x_port_ops
	305	},
	306	{ /* CMD 646 with broken UDMA */
1d2808fd	307	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	308	.pio_mask = ATA_PIO4,
14bdef98 EIB	309	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	310	.port_ops = &cmd64x_port_ops
	311	},
	312	{ /* CMD 646 with working UDMA */
1d2808fd	313	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	314	.pio_mask = ATA_PIO4,
14bdef98 EIB	315	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	316	.udma_mask = ATA_UDMA2,
669a5db4 JG	317	.port_ops = &cmd64x_port_ops
	318	},
	319	{ /* CMD 646 rev 1 */
1d2808fd	320	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	321	.pio_mask = ATA_PIO4,
14bdef98 EIB	322	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	323	.port_ops = &cmd646r1_port_ops
	324	},
	325	{ /* CMD 648 */
1d2808fd	326	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	327	.pio_mask = ATA_PIO4,
14bdef98 EIB	328	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	329	.udma_mask = ATA_UDMA4,
669a5db4 JG	330	.port_ops = &cmd648_port_ops
	331	},
	332	{ /* CMD 649 */
1d2808fd	333	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	334	.pio_mask = ATA_PIO4,
14bdef98 EIB	335	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	336	.udma_mask = ATA_UDMA5,
669a5db4 JG	337	.port_ops = &cmd648_port_ops
	338	}
	339	};
1626aeb8	340	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
669a5db4	341	u8 mrdmode;
f08048e9 TH	342	int rc;
	343
	344	rc = pcim_enable_device(pdev);
	345	if (rc)
	346	return rc;
85cd7251	347
669a5db4 JG	348	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
669a5db4 JG	349	class_rev &= 0xFF;
85cd7251	350
669a5db4	351	if (id->driver_data == 0) /* 643 */
9363c382	352	ata_pci_bmdma_clear_simplex(pdev);
85cd7251	353
669a5db4 JG	354	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
	355	/* Does UDMA work ? */
	356	if (class_rev > 4)
1626aeb8	357	ppi[0] = &cmd_info[2];
669a5db4 JG	358	/* Early rev with other problems ? */
669a5db4 JG	359	else if (class_rev == 1)
1626aeb8	360	ppi[0] = &cmd_info[3];
669a5db4 JG	361	}
	362
	363	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	364	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	365	mrdmode &= ~ 0x30; /* IRQ set up */
	366	mrdmode \|= 0x02; /* Memory read line enable */
	367	pci_write_config_byte(pdev, MRDMODE, mrdmode);
85cd7251	368
669a5db4	369	/* Force PIO 0 here.. */
85cd7251	370
669a5db4 JG	371	/* PPC specific fixup copied from old driver */
	372	#ifdef CONFIG_PPC
	373	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	374	#endif
85cd7251	375
9363c382	376	return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL);
669a5db4 JG	377	}
669a5db4 JG	378
438ac6d5	379	#ifdef CONFIG_PM
7f72a379 AC	380	static int cmd64x_reinit_one(struct pci_dev *pdev)
7f72a379 AC	381	{
f08048e9	382	struct ata_host *host = dev_get_drvdata(&pdev->dev);
7f72a379	383	u8 mrdmode;
f08048e9 TH	384	int rc;
	385
	386	rc = ata_pci_device_do_resume(pdev);
	387	if (rc)
	388	return rc;
	389
7f72a379 AC	390	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	391	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	392	mrdmode &= ~ 0x30; /* IRQ set up */
	393	mrdmode \|= 0x02; /* Memory read line enable */
	394	pci_write_config_byte(pdev, MRDMODE, mrdmode);
	395	#ifdef CONFIG_PPC
	396	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	397	#endif
f08048e9 TH	398	ata_host_resume(host);
f08048e9 TH	399	return 0;
7f72a379	400	}
438ac6d5	401	#endif
7f72a379	402
2d2744fc JG	403	static const struct pci_device_id cmd64x[] = {
	404	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	405	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	406	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	407	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
	408
	409	{ },
669a5db4 JG	410	};
	411
	412	static struct pci_driver cmd64x_pci_driver = {
2d2744fc	413	.name = DRV_NAME,
669a5db4 JG	414	.id_table = cmd64x,
669a5db4 JG	415	.probe = cmd64x_init_one,
7f72a379	416	.remove = ata_pci_remove_one,
438ac6d5	417	#ifdef CONFIG_PM
7f72a379 AC	418	.suspend = ata_pci_device_suspend,
7f72a379 AC	419	.resume = cmd64x_reinit_one,
438ac6d5	420	#endif
669a5db4 JG	421	};
	422
	423	static int __init cmd64x_init(void)
	424	{
	425	return pci_register_driver(&cmd64x_pci_driver);
	426	}
	427
669a5db4 JG	428	static void __exit cmd64x_exit(void)
	429	{
	430	pci_unregister_driver(&cmd64x_pci_driver);
	431	}
	432
669a5db4 JG	433	MODULE_AUTHOR("Alan Cox");
	434	MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
	435	MODULE_LICENSE("GPL");
	436	MODULE_DEVICE_TABLE(pci, cmd64x);
	437	MODULE_VERSION(DRV_VERSION);
	438
	439	module_init(cmd64x_init);
	440	module_exit(cmd64x_exit);