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USB: imx21-hcd: refactor hardware data memory management
[linux.git] / drivers / usb / host / imx21-hcd.c
CommitLineData
23d3e7a6
MF		 1/*
2 * USB Host Controller Driver for IMX21
3 *
4 * Copyright (C) 2006 Loping Dog Embedded Systems
5 * Copyright (C) 2009 Martin Fuzzey
6 * Originally written by Jay Monkman <[email protected]>
7 * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24
25 /*
26 * The i.MX21 USB hardware contains
27 * * 32 transfer descriptors (called ETDs)
28 * * 4Kb of Data memory
29 *
30 * The data memory is shared between the host and fuction controlers
31 * (but this driver only supports the host controler)
32 *
33 * So setting up a transfer involves:
34 * * Allocating a ETD
35 * * Fill in ETD with appropriate information
36 * * Allocating data memory (and putting the offset in the ETD)
37 * * Activate the ETD
38 * * Get interrupt when done.
39 *
40 * An ETD is assigned to each active endpoint.
41 *
42 * Low resource (ETD and Data memory) situations are handled differently for
43 * isochronous and non insosynchronous transactions :
44 *
45 * Non ISOC transfers are queued if either ETDs or Data memory are unavailable
46 *
47 * ISOC transfers use 2 ETDs per endpoint to achieve double buffering.
48 * They allocate both ETDs and Data memory during URB submission
49 * (and fail if unavailable).
50 */
51
52#include <linux/clk.h>
53#include <linux/io.h>
54#include <linux/kernel.h>
55#include <linux/list.h>
56#include <linux/platform_device.h>
5a0e3ad6 57#include <linux/slab.h>
23d3e7a6 58#include <linux/usb.h>
27729aad 59#include <linux/usb/hcd.h>
23d3e7a6 60
23d3e7a6
MF		 61#include "imx21-hcd.h"
62
63#ifdef DEBUG
64#define DEBUG_LOG_FRAME(imx21, etd, event) \
65 (etd)->event##_frame = readl((imx21)->regs + USBH_FRMNUB)
66#else
67#define DEBUG_LOG_FRAME(imx21, etd, event) do { } while (0)
68#endif
69
70static const char hcd_name[] = "imx21-hcd";
71
72static inline struct imx21 *hcd_to_imx21(struct usb_hcd *hcd)
73{
74 return (struct imx21 *)hcd->hcd_priv;
75}
76
77
78/* =========================================== */
79/* Hardware access helpers */
80/* =========================================== */
81
82static inline void set_register_bits(struct imx21 *imx21, u32 offset, u32 mask)
83{
84 void __iomem *reg = imx21->regs + offset;
85 writel(readl(reg) | mask, reg);
86}
87
88static inline void clear_register_bits(struct imx21 *imx21,
89 u32 offset, u32 mask)
90{
91 void __iomem *reg = imx21->regs + offset;
92 writel(readl(reg) & ~mask, reg);
93}
94
95static inline void clear_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
96{
97 void __iomem *reg = imx21->regs + offset;
98
99 if (readl(reg) & mask)
100 writel(mask, reg);
101}
102
103static inline void set_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
104{
105 void __iomem *reg = imx21->regs + offset;
106
107 if (!(readl(reg) & mask))
108 writel(mask, reg);
109}
110
111static void etd_writel(struct imx21 *imx21, int etd_num, int dword, u32 value)
112{
113 writel(value, imx21->regs + USB_ETD_DWORD(etd_num, dword));
114}
115
116static u32 etd_readl(struct imx21 *imx21, int etd_num, int dword)
117{
118 return readl(imx21->regs + USB_ETD_DWORD(etd_num, dword));
119}
120
121static inline int wrap_frame(int counter)
122{
123 return counter & 0xFFFF;
124}
125
126static inline int frame_after(int frame, int after)
127{
128 /* handle wrapping like jiffies time_afer */
129 return (s16)((s16)after - (s16)frame) < 0;
130}
131
132static int imx21_hc_get_frame(struct usb_hcd *hcd)
133{
134 struct imx21 *imx21 = hcd_to_imx21(hcd);
135
136 return wrap_frame(readl(imx21->regs + USBH_FRMNUB));
137}
138
139
140#include "imx21-dbg.c"
141
142/* =========================================== */
143/* ETD management */
144/* =========================================== */
145
146static int alloc_etd(struct imx21 *imx21)
147{
148 int i;
149 struct etd_priv *etd = imx21->etd;
150
151 for (i = 0; i < USB_NUM_ETD; i++, etd++) {
152 if (etd->alloc == 0) {
153 memset(etd, 0, sizeof(imx21->etd[0]));
154 etd->alloc = 1;
155 debug_etd_allocated(imx21);
156 return i;
157 }
158 }
159 return -1;
160}
161
162static void disactivate_etd(struct imx21 *imx21, int num)
163{
164 int etd_mask = (1 << num);
165 struct etd_priv *etd = &imx21->etd[num];
166
167 writel(etd_mask, imx21->regs + USBH_ETDENCLR);
168 clear_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
169 writel(etd_mask, imx21->regs + USB_ETDDMACHANLCLR);
170 clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
171
172 etd->active_count = 0;
173
174 DEBUG_LOG_FRAME(imx21, etd, disactivated);
175}
176
177static void reset_etd(struct imx21 *imx21, int num)
178{
179 struct etd_priv *etd = imx21->etd + num;
180 int i;
181
182 disactivate_etd(imx21, num);
183
184 for (i = 0; i < 4; i++)
185 etd_writel(imx21, num, i, 0);
186 etd->urb = NULL;
187 etd->ep = NULL;
188 etd->td = NULL;;
189}
190
191static void free_etd(struct imx21 *imx21, int num)
192{
193 if (num < 0)
194 return;
195
196 if (num >= USB_NUM_ETD) {
197 dev_err(imx21->dev, "BAD etd=%d!\n", num);
198 return;
199 }
200 if (imx21->etd[num].alloc == 0) {
201 dev_err(imx21->dev, "ETD %d already free!\n", num);
202 return;
203 }
204
205 debug_etd_freed(imx21);
206 reset_etd(imx21, num);
207 memset(&imx21->etd[num], 0, sizeof(imx21->etd[0]));
208}
209
210
211static void setup_etd_dword0(struct imx21 *imx21,
212 int etd_num, struct urb *urb, u8 dir, u16 maxpacket)
213{
214 etd_writel(imx21, etd_num, 0,
215 ((u32) usb_pipedevice(urb->pipe)) << DW0_ADDRESS |
216 ((u32) usb_pipeendpoint(urb->pipe) << DW0_ENDPNT) |
217 ((u32) dir << DW0_DIRECT) |
218 ((u32) ((urb->dev->speed == USB_SPEED_LOW) ?
219 1 : 0) << DW0_SPEED) |
220 ((u32) fmt_urb_to_etd[usb_pipetype(urb->pipe)] << DW0_FORMAT) |
221 ((u32) maxpacket << DW0_MAXPKTSIZ));
222}
223
224static void activate_etd(struct imx21 *imx21,
225 int etd_num, dma_addr_t dma, u8 dir)
226{
227 u32 etd_mask = 1 << etd_num;
228 struct etd_priv *etd = &imx21->etd[etd_num];
229
230 clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
231 set_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
232 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
233 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
234
235 if (dma) {
236 set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask);
237 clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask);
238 clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask);
239 writel(dma, imx21->regs + USB_ETDSMSA(etd_num));
240 set_register_bits(imx21, USB_ETDDMAEN, etd_mask);
241 } else {
242 if (dir != TD_DIR_IN) {
243 /* need to set for ZLP */
244 set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
245 set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
246 }
247 }
248
249 DEBUG_LOG_FRAME(imx21, etd, activated);
250
251#ifdef DEBUG
252 if (!etd->active_count) {
253 int i;
254 etd->activated_frame = readl(imx21->regs + USBH_FRMNUB);
255 etd->disactivated_frame = -1;
256 etd->last_int_frame = -1;
257 etd->last_req_frame = -1;
258
259 for (i = 0; i < 4; i++)
260 etd->submitted_dwords[i] = etd_readl(imx21, etd_num, i);
261 }
262#endif
263
264 etd->active_count = 1;
265 writel(etd_mask, imx21->regs + USBH_ETDENSET);
266}
267
268/* =========================================== */
269/* Data memory management */
270/* =========================================== */
271
272static int alloc_dmem(struct imx21 *imx21, unsigned int size,
273 struct usb_host_endpoint *ep)
274{
275 unsigned int offset = 0;
276 struct imx21_dmem_area *area;
277 struct imx21_dmem_area *tmp;
278
279 size += (~size + 1) & 0x3; /* Round to 4 byte multiple */
280
281 if (size > DMEM_SIZE) {
282 dev_err(imx21->dev, "size=%d > DMEM_SIZE(%d)\n",
283 size, DMEM_SIZE);
284 return -EINVAL;
285 }
286
287 list_for_each_entry(tmp, &imx21->dmem_list, list) {
288 if ((size + offset) < offset)
289 goto fail;
290 if ((size + offset) <= tmp->offset)
291 break;
292 offset = tmp->size + tmp->offset;
293 if ((offset + size) > DMEM_SIZE)
294 goto fail;
295 }
296
297 area = kmalloc(sizeof(struct imx21_dmem_area), GFP_ATOMIC);
298 if (area == NULL)
299 return -ENOMEM;
300
301 area->ep = ep;
302 area->offset = offset;
303 area->size = size;
304 list_add_tail(&area->list, &tmp->list);
305 debug_dmem_allocated(imx21, size);
306 return offset;
307
308fail:
309 return -ENOMEM;
310}
311
312/* Memory now available for a queued ETD - activate it */
313static void activate_queued_etd(struct imx21 *imx21,
314 struct etd_priv *etd, u32 dmem_offset)
315{
316 struct urb_priv *urb_priv = etd->urb->hcpriv;
317 int etd_num = etd - &imx21->etd[0];
318 u32 maxpacket = etd_readl(imx21, etd_num, 1) >> DW1_YBUFSRTAD;
319 u8 dir = (etd_readl(imx21, etd_num, 2) >> DW2_DIRPID) & 0x03;
320
321 dev_dbg(imx21->dev, "activating queued ETD %d now DMEM available\n",
322 etd_num);
323 etd_writel(imx21, etd_num, 1,
324 ((dmem_offset + maxpacket) << DW1_YBUFSRTAD) | dmem_offset);
325
b2a068d0 326 etd->dmem_offset = dmem_offset;
23d3e7a6
MF		 327 urb_priv->active = 1;
328 activate_etd(imx21, etd_num, etd->dma_handle, dir);
329}
330
b2a068d0 331static void free_dmem(struct imx21 *imx21, struct etd_priv *etd)
23d3e7a6
MF		 332{
333 struct imx21_dmem_area *area;
b2a068d0 334 struct etd_priv *tmp;
23d3e7a6 335 int found = 0;
b2a068d0 336 int offset;
23d3e7a6 337
b2a068d0
MF		 338 if (!etd->dmem_size)
339 return;
340 etd->dmem_size = 0;
341
342 offset = etd->dmem_offset;
23d3e7a6
MF		 343 list_for_each_entry(area, &imx21->dmem_list, list) {
344 if (area->offset == offset) {
345 debug_dmem_freed(imx21, area->size);
346 list_del(&area->list);
347 kfree(area);
348 found = 1;
349 break;
350 }
351 }
352
353 if (!found) {
354 dev_err(imx21->dev,
355 "Trying to free unallocated DMEM %d\n", offset);
356 return;
357 }
358
359 /* Try again to allocate memory for anything we've queued */
360 list_for_each_entry_safe(etd, tmp, &imx21->queue_for_dmem, queue) {
361 offset = alloc_dmem(imx21, etd->dmem_size, etd->ep);
362 if (offset >= 0) {
363 list_del(&etd->queue);
364 activate_queued_etd(imx21, etd, (u32)offset);
365 }
366 }
367}
368
369static void free_epdmem(struct imx21 *imx21, struct usb_host_endpoint *ep)
370{
371 struct imx21_dmem_area *area, *tmp;
372
373 list_for_each_entry_safe(area, tmp, &imx21->dmem_list, list) {
374 if (area->ep == ep) {
375 dev_err(imx21->dev,
376 "Active DMEM %d for disabled ep=%p\n",
377 area->offset, ep);
378 list_del(&area->list);
379 kfree(area);
380 }
381 }
382}
383
384
385/* =========================================== */
386/* End handling */
387/* =========================================== */
388static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb);
389
390/* Endpoint now idle - release it's ETD(s) or asssign to queued request */
391static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv)
392{
393 int etd_num;
394 int i;
395
396 for (i = 0; i < NUM_ISO_ETDS; i++) {
397 etd_num = ep_priv->etd[i];
398 if (etd_num < 0)
399 continue;
400
401 ep_priv->etd[i] = -1;
402 if (list_empty(&imx21->queue_for_etd)) {
403 free_etd(imx21, etd_num);
404 continue;
405 }
406
407 dev_dbg(imx21->dev,
408 "assigning idle etd %d for queued request\n", etd_num);
409 ep_priv = list_first_entry(&imx21->queue_for_etd,
410 struct ep_priv, queue);
411 list_del(&ep_priv->queue);
412 reset_etd(imx21, etd_num);
413 ep_priv->waiting_etd = 0;
414 ep_priv->etd[i] = etd_num;
415
416 if (list_empty(&ep_priv->ep->urb_list)) {
417 dev_err(imx21->dev, "No urb for queued ep!\n");
418 continue;
419 }
420 schedule_nonisoc_etd(imx21, list_first_entry(
421 &ep_priv->ep->urb_list, struct urb, urb_list));
422 }
423}
424
425static void urb_done(struct usb_hcd *hcd, struct urb *urb, int status)
426__releases(imx21->lock)
427__acquires(imx21->lock)
428{
429 struct imx21 *imx21 = hcd_to_imx21(hcd);
430 struct ep_priv *ep_priv = urb->ep->hcpriv;
431 struct urb_priv *urb_priv = urb->hcpriv;
432
433 debug_urb_completed(imx21, urb, status);
434 dev_vdbg(imx21->dev, "urb %p done %d\n", urb, status);
435
436 kfree(urb_priv->isoc_td);
437 kfree(urb->hcpriv);
438 urb->hcpriv = NULL;
439 usb_hcd_unlink_urb_from_ep(hcd, urb);
440 spin_unlock(&imx21->lock);
441 usb_hcd_giveback_urb(hcd, urb, status);
442 spin_lock(&imx21->lock);
443 if (list_empty(&ep_priv->ep->urb_list))
444 ep_idle(imx21, ep_priv);
445}
446
447/* =========================================== */
448/* ISOC Handling ... */
449/* =========================================== */
450
451static void schedule_isoc_etds(struct usb_hcd *hcd,
452 struct usb_host_endpoint *ep)
453{
454 struct imx21 *imx21 = hcd_to_imx21(hcd);
455 struct ep_priv *ep_priv = ep->hcpriv;
456 struct etd_priv *etd;
457 struct urb_priv *urb_priv;
458 struct td *td;
459 int etd_num;
460 int i;
461 int cur_frame;
462 u8 dir;
463
464 for (i = 0; i < NUM_ISO_ETDS; i++) {
465too_late:
466 if (list_empty(&ep_priv->td_list))
467 break;
468
469 etd_num = ep_priv->etd[i];
470 if (etd_num < 0)
471 break;
472
473 etd = &imx21->etd[etd_num];
474 if (etd->urb)
475 continue;
476
477 td = list_entry(ep_priv->td_list.next, struct td, list);
478 list_del(&td->list);
479 urb_priv = td->urb->hcpriv;
480
481 cur_frame = imx21_hc_get_frame(hcd);
482 if (frame_after(cur_frame, td->frame)) {
483 dev_dbg(imx21->dev, "isoc too late frame %d > %d\n",
484 cur_frame, td->frame);
485 urb_priv->isoc_status = -EXDEV;
486 td->urb->iso_frame_desc[
487 td->isoc_index].actual_length = 0;
488 td->urb->iso_frame_desc[td->isoc_index].status = -EXDEV;
489 if (--urb_priv->isoc_remaining == 0)
490 urb_done(hcd, td->urb, urb_priv->isoc_status);
491 goto too_late;
492 }
493
494 urb_priv->active = 1;
495 etd->td = td;
496 etd->ep = td->ep;
497 etd->urb = td->urb;
498 etd->len = td->len;
499
500 debug_isoc_submitted(imx21, cur_frame, td);
501
502 dir = usb_pipeout(td->urb->pipe) ? TD_DIR_OUT : TD_DIR_IN;
503 setup_etd_dword0(imx21, etd_num, td->urb, dir, etd->dmem_size);
504 etd_writel(imx21, etd_num, 1, etd->dmem_offset);
505 etd_writel(imx21, etd_num, 2,
506 (TD_NOTACCESSED << DW2_COMPCODE) |
507 ((td->frame & 0xFFFF) << DW2_STARTFRM));
508 etd_writel(imx21, etd_num, 3,
509 (TD_NOTACCESSED << DW3_COMPCODE0) |
510 (td->len << DW3_PKTLEN0));
511
512 activate_etd(imx21, etd_num, td->data, dir);
513 }
514}
515
516static void isoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num)
517{
518 struct imx21 *imx21 = hcd_to_imx21(hcd);
519 int etd_mask = 1 << etd_num;
520 struct urb_priv *urb_priv = urb->hcpriv;
521 struct etd_priv *etd = imx21->etd + etd_num;
522 struct td *td = etd->td;
523 struct usb_host_endpoint *ep = etd->ep;
524 int isoc_index = td->isoc_index;
525 unsigned int pipe = urb->pipe;
526 int dir_in = usb_pipein(pipe);
527 int cc;
528 int bytes_xfrd;
529
530 disactivate_etd(imx21, etd_num);
531
532 cc = (etd_readl(imx21, etd_num, 3) >> DW3_COMPCODE0) & 0xf;
533 bytes_xfrd = etd_readl(imx21, etd_num, 3) & 0x3ff;
534
535 /* Input doesn't always fill the buffer, don't generate an error
536 * when this happens.
537 */
538 if (dir_in && (cc == TD_DATAUNDERRUN))
539 cc = TD_CC_NOERROR;
540
541 if (cc == TD_NOTACCESSED)
542 bytes_xfrd = 0;
543
544 debug_isoc_completed(imx21,
545 imx21_hc_get_frame(hcd), td, cc, bytes_xfrd);
546 if (cc) {
547 urb_priv->isoc_status = -EXDEV;
548 dev_dbg(imx21->dev,
549 "bad iso cc=0x%X frame=%d sched frame=%d "
550 "cnt=%d len=%d urb=%p etd=%d index=%d\n",
551 cc, imx21_hc_get_frame(hcd), td->frame,
552 bytes_xfrd, td->len, urb, etd_num, isoc_index);
553 }
554
555 if (dir_in)
556 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
557
558 urb->actual_length += bytes_xfrd;
559 urb->iso_frame_desc[isoc_index].actual_length = bytes_xfrd;
560 urb->iso_frame_desc[isoc_index].status = cc_to_error[cc];
561
562 etd->td = NULL;
563 etd->urb = NULL;
564 etd->ep = NULL;
565
566 if (--urb_priv->isoc_remaining == 0)
567 urb_done(hcd, urb, urb_priv->isoc_status);
568
569 schedule_isoc_etds(hcd, ep);
570}
571
572static struct ep_priv *alloc_isoc_ep(
573 struct imx21 *imx21, struct usb_host_endpoint *ep)
574{
575 struct ep_priv *ep_priv;
576 int i;
577
578 ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
579 if (ep_priv == NULL)
580 return NULL;
581
582 /* Allocate the ETDs */
583 for (i = 0; i < NUM_ISO_ETDS; i++) {
584 ep_priv->etd[i] = alloc_etd(imx21);
585 if (ep_priv->etd[i] < 0) {
586 int j;
587 dev_err(imx21->dev, "isoc: Couldn't allocate etd\n");
588 for (j = 0; j < i; j++)
589 free_etd(imx21, ep_priv->etd[j]);
590 goto alloc_etd_failed;
591 }
592 imx21->etd[ep_priv->etd[i]].ep = ep;
593 }
594
595 INIT_LIST_HEAD(&ep_priv->td_list);
596 ep_priv->ep = ep;
597 ep->hcpriv = ep_priv;
598 return ep_priv;
599
600alloc_etd_failed:
601 kfree(ep_priv);
602 return NULL;
603}
604
605static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd,
606 struct usb_host_endpoint *ep,
607 struct urb *urb, gfp_t mem_flags)
608{
609 struct imx21 *imx21 = hcd_to_imx21(hcd);
610 struct urb_priv *urb_priv;
611 unsigned long flags;
612 struct ep_priv *ep_priv;
613 struct td *td = NULL;
614 int i;
615 int ret;
616 int cur_frame;
617 u16 maxpacket;
618
619 urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
620 if (urb_priv == NULL)
621 return -ENOMEM;
622
623 urb_priv->isoc_td = kzalloc(
624 sizeof(struct td) * urb->number_of_packets, mem_flags);
625 if (urb_priv->isoc_td == NULL) {
626 ret = -ENOMEM;
627 goto alloc_td_failed;
628 }
629
630 spin_lock_irqsave(&imx21->lock, flags);
631
632 if (ep->hcpriv == NULL) {
633 ep_priv = alloc_isoc_ep(imx21, ep);
634 if (ep_priv == NULL) {
635 ret = -ENOMEM;
636 goto alloc_ep_failed;
637 }
638 } else {
639 ep_priv = ep->hcpriv;
640 }
641
642 ret = usb_hcd_link_urb_to_ep(hcd, urb);
643 if (ret)
644 goto link_failed;
645
646 urb->status = -EINPROGRESS;
647 urb->actual_length = 0;
648 urb->error_count = 0;
649 urb->hcpriv = urb_priv;
650 urb_priv->ep = ep;
651
652 /* allocate data memory for largest packets if not already done */
653 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
654 for (i = 0; i < NUM_ISO_ETDS; i++) {
655 struct etd_priv *etd = &imx21->etd[ep_priv->etd[i]];
656
657 if (etd->dmem_size > 0 && etd->dmem_size < maxpacket) {
658 /* not sure if this can really occur.... */
659 dev_err(imx21->dev, "increasing isoc buffer %d->%d\n",
660 etd->dmem_size, maxpacket);
661 ret = -EMSGSIZE;
662 goto alloc_dmem_failed;
663 }
664
665 if (etd->dmem_size == 0) {
666 etd->dmem_offset = alloc_dmem(imx21, maxpacket, ep);
667 if (etd->dmem_offset < 0) {
668 dev_dbg(imx21->dev, "failed alloc isoc dmem\n");
669 ret = -EAGAIN;
670 goto alloc_dmem_failed;
671 }
672 etd->dmem_size = maxpacket;
673 }
674 }
675
676 /* calculate frame */
677 cur_frame = imx21_hc_get_frame(hcd);
678 if (urb->transfer_flags & URB_ISO_ASAP) {
679 if (list_empty(&ep_priv->td_list))
680 urb->start_frame = cur_frame + 5;
681 else
682 urb->start_frame = list_entry(
683 ep_priv->td_list.prev,
684 struct td, list)->frame + urb->interval;
685 }
686 urb->start_frame = wrap_frame(urb->start_frame);
687 if (frame_after(cur_frame, urb->start_frame)) {
688 dev_dbg(imx21->dev,
689 "enqueue: adjusting iso start %d (cur=%d) asap=%d\n",
690 urb->start_frame, cur_frame,
691 (urb->transfer_flags & URB_ISO_ASAP) != 0);
692 urb->start_frame = wrap_frame(cur_frame + 1);
693 }
694
695 /* set up transfers */
696 td = urb_priv->isoc_td;
697 for (i = 0; i < urb->number_of_packets; i++, td++) {
698 td->ep = ep;
699 td->urb = urb;
700 td->len = urb->iso_frame_desc[i].length;
701 td->isoc_index = i;
702 td->frame = wrap_frame(urb->start_frame + urb->interval * i);
703 td->data = urb->transfer_dma + urb->iso_frame_desc[i].offset;
704 list_add_tail(&td->list, &ep_priv->td_list);
705 }
706
707 urb_priv->isoc_remaining = urb->number_of_packets;
708 dev_vdbg(imx21->dev, "setup %d packets for iso frame %d->%d\n",
709 urb->number_of_packets, urb->start_frame, td->frame);
710
711 debug_urb_submitted(imx21, urb);
712 schedule_isoc_etds(hcd, ep);
713
714 spin_unlock_irqrestore(&imx21->lock, flags);
715 return 0;
716
717alloc_dmem_failed:
718 usb_hcd_unlink_urb_from_ep(hcd, urb);
719
720link_failed:
721alloc_ep_failed:
722 spin_unlock_irqrestore(&imx21->lock, flags);
723 kfree(urb_priv->isoc_td);
724
725alloc_td_failed:
726 kfree(urb_priv);
727 return ret;
728}
729
730static void dequeue_isoc_urb(struct imx21 *imx21,
731 struct urb *urb, struct ep_priv *ep_priv)
732{
733 struct urb_priv *urb_priv = urb->hcpriv;
734 struct td *td, *tmp;
735 int i;
736
737 if (urb_priv->active) {
738 for (i = 0; i < NUM_ISO_ETDS; i++) {
739 int etd_num = ep_priv->etd[i];
740 if (etd_num != -1 && imx21->etd[etd_num].urb == urb) {
741 struct etd_priv *etd = imx21->etd + etd_num;
742
743 reset_etd(imx21, etd_num);
b2a068d0 744 free_dmem(imx21, etd);
23d3e7a6
MF		 745 }
746 }
747 }
748
749 list_for_each_entry_safe(td, tmp, &ep_priv->td_list, list) {
750 if (td->urb == urb) {
751 dev_vdbg(imx21->dev, "removing td %p\n", td);
752 list_del(&td->list);
753 }
754 }
755}
756
757/* =========================================== */
758/* NON ISOC Handling ... */
759/* =========================================== */
760
761static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb)
762{
763 unsigned int pipe = urb->pipe;
764 struct urb_priv *urb_priv = urb->hcpriv;
765 struct ep_priv *ep_priv = urb_priv->ep->hcpriv;
766 int state = urb_priv->state;
767 int etd_num = ep_priv->etd[0];
768 struct etd_priv *etd;
23d3e7a6
MF		 769 u32 count;
770 u16 etd_buf_size;
771 u16 maxpacket;
772 u8 dir;
773 u8 bufround;
774 u8 datatoggle;
775 u8 interval = 0;
776 u8 relpolpos = 0;
777
778 if (etd_num < 0) {
779 dev_err(imx21->dev, "No valid ETD\n");
780 return;
781 }
782 if (readl(imx21->regs + USBH_ETDENSET) & (1 << etd_num))
783 dev_err(imx21->dev, "submitting to active ETD %d\n", etd_num);
784
785 etd = &imx21->etd[etd_num];
786 maxpacket = usb_maxpacket(urb->dev, pipe, usb_pipeout(pipe));
787 if (!maxpacket)
788 maxpacket = 8;
789
790 if (usb_pipecontrol(pipe) && (state != US_CTRL_DATA)) {
791 if (state == US_CTRL_SETUP) {
792 dir = TD_DIR_SETUP;
793 etd->dma_handle = urb->setup_dma;
794 bufround = 0;
795 count = 8;
796 datatoggle = TD_TOGGLE_DATA0;
797 } else { /* US_CTRL_ACK */
798 dir = usb_pipeout(pipe) ? TD_DIR_IN : TD_DIR_OUT;
799 etd->dma_handle = urb->transfer_dma;
800 bufround = 0;
801 count = 0;
802 datatoggle = TD_TOGGLE_DATA1;
803 }
804 } else {
805 dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN;
806 bufround = (dir == TD_DIR_IN) ? 1 : 0;
807 etd->dma_handle = urb->transfer_dma;
808 if (usb_pipebulk(pipe) && (state == US_BULK0))
809 count = 0;
810 else
811 count = urb->transfer_buffer_length;
812
813 if (usb_pipecontrol(pipe)) {
814 datatoggle = TD_TOGGLE_DATA1;
815 } else {
816 if (usb_gettoggle(
817 urb->dev,
818 usb_pipeendpoint(urb->pipe),
819 usb_pipeout(urb->pipe)))
820 datatoggle = TD_TOGGLE_DATA1;
821 else
822 datatoggle = TD_TOGGLE_DATA0;
823 }
824 }
825
826 etd->urb = urb;
827 etd->ep = urb_priv->ep;
828 etd->len = count;
829
830 if (usb_pipeint(pipe)) {
831 interval = urb->interval;
832 relpolpos = (readl(imx21->regs + USBH_FRMNUB) + 1) & 0xff;
833 }
834
835 /* Write ETD to device memory */
836 setup_etd_dword0(imx21, etd_num, urb, dir, maxpacket);
837
838 etd_writel(imx21, etd_num, 2,
839 (u32) interval << DW2_POLINTERV |
840 ((u32) relpolpos << DW2_RELPOLPOS) |
841 ((u32) dir << DW2_DIRPID) |
842 ((u32) bufround << DW2_BUFROUND) |
843 ((u32) datatoggle << DW2_DATATOG) |
844 ((u32) TD_NOTACCESSED << DW2_COMPCODE));
845
846 /* DMA will always transfer buffer size even if TOBYCNT in DWORD3
847 is smaller. Make sure we don't overrun the buffer!
848 */
849 if (count && count < maxpacket)
850 etd_buf_size = count;
851 else
852 etd_buf_size = maxpacket;
853
854 etd_writel(imx21, etd_num, 3,
855 ((u32) (etd_buf_size - 1) << DW3_BUFSIZE) | (u32) count);
856
857 if (!count)
858 etd->dma_handle = 0;
859
860 /* allocate x and y buffer space at once */
861 etd->dmem_size = (count > maxpacket) ? maxpacket * 2 : maxpacket;
b2a068d0
MF		 862 etd->dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep);
863 if (etd->dmem_offset < 0) {
23d3e7a6
MF		 864 /* Setup everything we can in HW and update when we get DMEM */
865 etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16);
866
867 dev_dbg(imx21->dev, "Queuing etd %d for DMEM\n", etd_num);
868 debug_urb_queued_for_dmem(imx21, urb);
869 list_add_tail(&etd->queue, &imx21->queue_for_dmem);
870 return;
871 }
872
873 etd_writel(imx21, etd_num, 1,
b2a068d0
MF		 874 (((u32) etd->dmem_offset + (u32) maxpacket) << DW1_YBUFSRTAD) |
875 (u32) etd->dmem_offset);
23d3e7a6
MF		 876
877 urb_priv->active = 1;
878
879 /* enable the ETD to kick off transfer */
880 dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n",
881 etd_num, count, dir != TD_DIR_IN ? "out" : "in");
882 activate_etd(imx21, etd_num, etd->dma_handle, dir);
883
884}
885
886static void nonisoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num)
887{
888 struct imx21 *imx21 = hcd_to_imx21(hcd);
889 struct etd_priv *etd = &imx21->etd[etd_num];
890 u32 etd_mask = 1 << etd_num;
891 struct urb_priv *urb_priv = urb->hcpriv;
892 int dir;
23d3e7a6
MF		 893 int cc;
894 u32 bytes_xfrd;
895 int etd_done;
896
897 disactivate_etd(imx21, etd_num);
898
899 dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3;
23d3e7a6
MF		 900 cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf;
901 bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff);
902
903 /* save toggle carry */
904 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
905 usb_pipeout(urb->pipe),
906 (etd_readl(imx21, etd_num, 0) >> DW0_TOGCRY) & 0x1);
907
908 if (dir == TD_DIR_IN) {
909 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
910 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
911 }
b2a068d0 912 free_dmem(imx21, etd);
23d3e7a6
MF		 913
914 urb->error_count = 0;
915 if (!(urb->transfer_flags & URB_SHORT_NOT_OK)
916 && (cc == TD_DATAUNDERRUN))
917 cc = TD_CC_NOERROR;
918
919 if (cc != 0)
920 dev_vdbg(imx21->dev, "cc is 0x%x\n", cc);
921
922 etd_done = (cc_to_error[cc] != 0); /* stop if error */
923
924 switch (usb_pipetype(urb->pipe)) {
925 case PIPE_CONTROL:
926 switch (urb_priv->state) {
927 case US_CTRL_SETUP:
928 if (urb->transfer_buffer_length > 0)
929 urb_priv->state = US_CTRL_DATA;
930 else
931 urb_priv->state = US_CTRL_ACK;
932 break;
933 case US_CTRL_DATA:
934 urb->actual_length += bytes_xfrd;
935 urb_priv->state = US_CTRL_ACK;
936 break;
937 case US_CTRL_ACK:
938 etd_done = 1;
939 break;
940 default:
941 dev_err(imx21->dev,
942 "Invalid pipe state %d\n", urb_priv->state);
943 etd_done = 1;
944 break;
945 }
946 break;
947
948 case PIPE_BULK:
949 urb->actual_length += bytes_xfrd;
950 if ((urb_priv->state == US_BULK)
951 && (urb->transfer_flags & URB_ZERO_PACKET)
952 && urb->transfer_buffer_length > 0
953 && ((urb->transfer_buffer_length %
954 usb_maxpacket(urb->dev, urb->pipe,
955 usb_pipeout(urb->pipe))) == 0)) {
956 /* need a 0-packet */
957 urb_priv->state = US_BULK0;
958 } else {
959 etd_done = 1;
960 }
961 break;
962
963 case PIPE_INTERRUPT:
964 urb->actual_length += bytes_xfrd;
965 etd_done = 1;
966 break;
967 }
968
969 if (!etd_done) {
970 dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state);
971 schedule_nonisoc_etd(imx21, urb);
972 } else {
973 struct usb_host_endpoint *ep = urb->ep;
974
975 urb_done(hcd, urb, cc_to_error[cc]);
976 etd->urb = NULL;
977
978 if (!list_empty(&ep->urb_list)) {
979 urb = list_first_entry(&ep->urb_list,
980 struct urb, urb_list);
981 dev_vdbg(imx21->dev, "next URB %p\n", urb);
982 schedule_nonisoc_etd(imx21, urb);
983 }
984 }
985}
986
987static struct ep_priv *alloc_ep(void)
988{
989 int i;
990 struct ep_priv *ep_priv;
991
992 ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
993 if (!ep_priv)
994 return NULL;
995
996 for (i = 0; i < NUM_ISO_ETDS; ++i)
997 ep_priv->etd[i] = -1;
998
999 return ep_priv;
1000}
1001
1002static int imx21_hc_urb_enqueue(struct usb_hcd *hcd,
1003 struct urb *urb, gfp_t mem_flags)
1004{
1005 struct imx21 *imx21 = hcd_to_imx21(hcd);
1006 struct usb_host_endpoint *ep = urb->ep;
1007 struct urb_priv *urb_priv;
1008 struct ep_priv *ep_priv;
1009 struct etd_priv *etd;
1010 int ret;
1011 unsigned long flags;
23d3e7a6
MF		 1012
1013 dev_vdbg(imx21->dev,
1014 "enqueue urb=%p ep=%p len=%d "
1015 "buffer=%p dma=%08X setupBuf=%p setupDma=%08X\n",
1016 urb, ep,
1017 urb->transfer_buffer_length,
1018 urb->transfer_buffer, urb->transfer_dma,
1019 urb->setup_packet, urb->setup_dma);
1020
1021 if (usb_pipeisoc(urb->pipe))
1022 return imx21_hc_urb_enqueue_isoc(hcd, ep, urb, mem_flags);
1023
1024 urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
1025 if (!urb_priv)
1026 return -ENOMEM;
1027
1028 spin_lock_irqsave(&imx21->lock, flags);
1029
1030 ep_priv = ep->hcpriv;
1031 if (ep_priv == NULL) {
1032 ep_priv = alloc_ep();
1033 if (!ep_priv) {
1034 ret = -ENOMEM;
1035 goto failed_alloc_ep;
1036 }
1037 ep->hcpriv = ep_priv;
1038 ep_priv->ep = ep;
23d3e7a6
MF		 1039 }
1040
1041 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1042 if (ret)
1043 goto failed_link;
1044
1045 urb->status = -EINPROGRESS;
1046 urb->actual_length = 0;
1047 urb->error_count = 0;
1048 urb->hcpriv = urb_priv;
1049 urb_priv->ep = ep;
1050
1051 switch (usb_pipetype(urb->pipe)) {
1052 case PIPE_CONTROL:
1053 urb_priv->state = US_CTRL_SETUP;
1054 break;
1055 case PIPE_BULK:
1056 urb_priv->state = US_BULK;
1057 break;
1058 }
1059
1060 debug_urb_submitted(imx21, urb);
1061 if (ep_priv->etd[0] < 0) {
1062 if (ep_priv->waiting_etd) {
1063 dev_dbg(imx21->dev,
1064 "no ETD available already queued %p\n",
1065 ep_priv);
1066 debug_urb_queued_for_etd(imx21, urb);
1067 goto out;
1068 }
1069 ep_priv->etd[0] = alloc_etd(imx21);
1070 if (ep_priv->etd[0] < 0) {
1071 dev_dbg(imx21->dev,
1072 "no ETD available queueing %p\n", ep_priv);
1073 debug_urb_queued_for_etd(imx21, urb);
1074 list_add_tail(&ep_priv->queue, &imx21->queue_for_etd);
1075 ep_priv->waiting_etd = 1;
1076 goto out;
1077 }
1078 }
1079
1080 /* Schedule if no URB already active for this endpoint */
1081 etd = &imx21->etd[ep_priv->etd[0]];
1082 if (etd->urb == NULL) {
1083 DEBUG_LOG_FRAME(imx21, etd, last_req);
1084 schedule_nonisoc_etd(imx21, urb);
1085 }
1086
1087out:
1088 spin_unlock_irqrestore(&imx21->lock, flags);
1089 return 0;
1090
1091failed_link:
1092failed_alloc_ep:
1093 spin_unlock_irqrestore(&imx21->lock, flags);
1094 kfree(urb_priv);
1095 return ret;
1096}
1097
1098static int imx21_hc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1099 int status)
1100{
1101 struct imx21 *imx21 = hcd_to_imx21(hcd);
1102 unsigned long flags;
1103 struct usb_host_endpoint *ep;
1104 struct ep_priv *ep_priv;
1105 struct urb_priv *urb_priv = urb->hcpriv;
1106 int ret = -EINVAL;
1107
1108 dev_vdbg(imx21->dev, "dequeue urb=%p iso=%d status=%d\n",
1109 urb, usb_pipeisoc(urb->pipe), status);
1110
1111 spin_lock_irqsave(&imx21->lock, flags);
1112
1113 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1114 if (ret)
1115 goto fail;
1116 ep = urb_priv->ep;
1117 ep_priv = ep->hcpriv;
1118
1119 debug_urb_unlinked(imx21, urb);
1120
1121 if (usb_pipeisoc(urb->pipe)) {
1122 dequeue_isoc_urb(imx21, urb, ep_priv);
1123 schedule_isoc_etds(hcd, ep);
1124 } else if (urb_priv->active) {
1125 int etd_num = ep_priv->etd[0];
1126 if (etd_num != -1) {
1127 disactivate_etd(imx21, etd_num);
b2a068d0 1128 free_dmem(imx21, &imx21->etd[etd_num]);
23d3e7a6
MF		 1129 imx21->etd[etd_num].urb = NULL;
1130 }
1131 }
1132
1133 urb_done(hcd, urb, status);
1134
1135 spin_unlock_irqrestore(&imx21->lock, flags);
1136 return 0;
1137
1138fail:
1139 spin_unlock_irqrestore(&imx21->lock, flags);
1140 return ret;
1141}
1142
1143/* =========================================== */
1144/* Interrupt dispatch */
1145/* =========================================== */
1146
1147static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof)
1148{
1149 int etd_num;
1150 int enable_sof_int = 0;
1151 unsigned long flags;
1152
1153 spin_lock_irqsave(&imx21->lock, flags);
1154
1155 for (etd_num = 0; etd_num < USB_NUM_ETD; etd_num++) {
1156 u32 etd_mask = 1 << etd_num;
1157 u32 enabled = readl(imx21->regs + USBH_ETDENSET) & etd_mask;
1158 u32 done = readl(imx21->regs + USBH_ETDDONESTAT) & etd_mask;
1159 struct etd_priv *etd = &imx21->etd[etd_num];
1160
1161
1162 if (done) {
1163 DEBUG_LOG_FRAME(imx21, etd, last_int);
1164 } else {
1165/*
1166 * Kludge warning!
1167 *
1168 * When multiple transfers are using the bus we sometimes get into a state
1169 * where the transfer has completed (the CC field of the ETD is != 0x0F),
1170 * the ETD has self disabled but the ETDDONESTAT flag is not set
1171 * (and hence no interrupt occurs).
1172 * This causes the transfer in question to hang.
1173 * The kludge below checks for this condition at each SOF and processes any
1174 * blocked ETDs (after an arbitary 10 frame wait)
1175 *
1176 * With a single active transfer the usbtest test suite will run for days
1177 * without the kludge.
1178 * With other bus activity (eg mass storage) even just test1 will hang without
1179 * the kludge.
1180 */
1181 u32 dword0;
1182 int cc;
1183
1184 if (etd->active_count && !enabled) /* suspicious... */
1185 enable_sof_int = 1;
1186
1187 if (!sof || enabled || !etd->active_count)
1188 continue;
1189
1190 cc = etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE;
1191 if (cc == TD_NOTACCESSED)
1192 continue;
1193
1194 if (++etd->active_count < 10)
1195 continue;
1196
1197 dword0 = etd_readl(imx21, etd_num, 0);
1198 dev_dbg(imx21->dev,
1199 "unblock ETD %d dev=0x%X ep=0x%X cc=0x%02X!\n",
1200 etd_num, dword0 & 0x7F,
1201 (dword0 >> DW0_ENDPNT) & 0x0F,
1202 cc);
1203
1204#ifdef DEBUG
1205 dev_dbg(imx21->dev,
1206 "frame: act=%d disact=%d"
1207 " int=%d req=%d cur=%d\n",
1208 etd->activated_frame,
1209 etd->disactivated_frame,
1210 etd->last_int_frame,
1211 etd->last_req_frame,
1212 readl(imx21->regs + USBH_FRMNUB));
1213 imx21->debug_unblocks++;
1214#endif
1215 etd->active_count = 0;
1216/* End of kludge */
1217 }
1218
1219 if (etd->ep == NULL || etd->urb == NULL) {
1220 dev_dbg(imx21->dev,
1221 "Interrupt for unexpected etd %d"
1222 " ep=%p urb=%p\n",
1223 etd_num, etd->ep, etd->urb);
1224 disactivate_etd(imx21, etd_num);
1225 continue;
1226 }
1227
1228 if (usb_pipeisoc(etd->urb->pipe))
1229 isoc_etd_done(hcd, etd->urb, etd_num);
1230 else
1231 nonisoc_etd_done(hcd, etd->urb, etd_num);
1232 }
1233
1234 /* only enable SOF interrupt if it may be needed for the kludge */
1235 if (enable_sof_int)
1236 set_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
1237 else
1238 clear_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
1239
1240
1241 spin_unlock_irqrestore(&imx21->lock, flags);
1242}
1243
1244static irqreturn_t imx21_irq(struct usb_hcd *hcd)
1245{
1246 struct imx21 *imx21 = hcd_to_imx21(hcd);
1247 u32 ints = readl(imx21->regs + USBH_SYSISR);
1248
1249 if (ints & USBH_SYSIEN_HERRINT)
1250 dev_dbg(imx21->dev, "Scheduling error\n");
1251
1252 if (ints & USBH_SYSIEN_SORINT)
1253 dev_dbg(imx21->dev, "Scheduling overrun\n");
1254
1255 if (ints & (USBH_SYSISR_DONEINT | USBH_SYSISR_SOFINT))
1256 process_etds(hcd, imx21, ints & USBH_SYSISR_SOFINT);
1257
1258 writel(ints, imx21->regs + USBH_SYSISR);
1259 return IRQ_HANDLED;
1260}
1261
1262static void imx21_hc_endpoint_disable(struct usb_hcd *hcd,
1263 struct usb_host_endpoint *ep)
1264{
1265 struct imx21 *imx21 = hcd_to_imx21(hcd);
1266 unsigned long flags;
1267 struct ep_priv *ep_priv;
1268 int i;
1269
1270 if (ep == NULL)
1271 return;
1272
1273 spin_lock_irqsave(&imx21->lock, flags);
1274 ep_priv = ep->hcpriv;
1275 dev_vdbg(imx21->dev, "disable ep=%p, ep->hcpriv=%p\n", ep, ep_priv);
1276
1277 if (!list_empty(&ep->urb_list))
1278 dev_dbg(imx21->dev, "ep's URB list is not empty\n");
1279
1280 if (ep_priv != NULL) {
1281 for (i = 0; i < NUM_ISO_ETDS; i++) {
1282 if (ep_priv->etd[i] > -1)
1283 dev_dbg(imx21->dev, "free etd %d for disable\n",
1284 ep_priv->etd[i]);
1285
1286 free_etd(imx21, ep_priv->etd[i]);
1287 }
1288 kfree(ep_priv);
1289 ep->hcpriv = NULL;
1290 }
1291
1292 for (i = 0; i < USB_NUM_ETD; i++) {
1293 if (imx21->etd[i].alloc && imx21->etd[i].ep == ep) {
1294 dev_err(imx21->dev,
1295 "Active etd %d for disabled ep=%p!\n", i, ep);
1296 free_etd(imx21, i);
1297 }
1298 }
1299 free_epdmem(imx21, ep);
1300 spin_unlock_irqrestore(&imx21->lock, flags);
1301}
1302
1303/* =========================================== */
1304/* Hub handling */
1305/* =========================================== */
1306
1307static int get_hub_descriptor(struct usb_hcd *hcd,
1308 struct usb_hub_descriptor *desc)
1309{
1310 struct imx21 *imx21 = hcd_to_imx21(hcd);
1311 desc->bDescriptorType = 0x29; /* HUB descriptor */
1312 desc->bHubContrCurrent = 0;
1313
1314 desc->bNbrPorts = readl(imx21->regs + USBH_ROOTHUBA)
1315 & USBH_ROOTHUBA_NDNSTMPRT_MASK;
1316 desc->bDescLength = 9;
1317 desc->bPwrOn2PwrGood = 0;
1318 desc->wHubCharacteristics = (__force __u16) cpu_to_le16(
1319 0x0002 | /* No power switching */
1320 0x0010 | /* No over current protection */
1321 0);
1322
1323 desc->bitmap[0] = 1 << 1;
1324 desc->bitmap[1] = ~0;
1325 return 0;
1326}
1327
1328static int imx21_hc_hub_status_data(struct usb_hcd *hcd, char *buf)
1329{
1330 struct imx21 *imx21 = hcd_to_imx21(hcd);
1331 int ports;
1332 int changed = 0;
1333 int i;
1334 unsigned long flags;
1335
1336 spin_lock_irqsave(&imx21->lock, flags);
1337 ports = readl(imx21->regs + USBH_ROOTHUBA)
1338 & USBH_ROOTHUBA_NDNSTMPRT_MASK;
1339 if (ports > 7) {
1340 ports = 7;
1341 dev_err(imx21->dev, "ports %d > 7\n", ports);
1342 }
1343 for (i = 0; i < ports; i++) {
1344 if (readl(imx21->regs + USBH_PORTSTAT(i)) &
1345 (USBH_PORTSTAT_CONNECTSC |
1346 USBH_PORTSTAT_PRTENBLSC |
1347 USBH_PORTSTAT_PRTSTATSC |
1348 USBH_PORTSTAT_OVRCURIC |
1349 USBH_PORTSTAT_PRTRSTSC)) {
1350
1351 changed = 1;
1352 buf[0] |= 1 << (i + 1);
1353 }
1354 }
1355 spin_unlock_irqrestore(&imx21->lock, flags);
1356
1357 if (changed)
1358 dev_info(imx21->dev, "Hub status changed\n");
1359 return changed;
1360}
1361
1362static int imx21_hc_hub_control(struct usb_hcd *hcd,
1363 u16 typeReq,
1364 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1365{
1366 struct imx21 *imx21 = hcd_to_imx21(hcd);
1367 int rc = 0;
1368 u32 status_write = 0;
1369
1370 switch (typeReq) {
1371 case ClearHubFeature:
1372 dev_dbg(imx21->dev, "ClearHubFeature\n");
1373 switch (wValue) {
1374 case C_HUB_OVER_CURRENT:
1375 dev_dbg(imx21->dev, " OVER_CURRENT\n");
1376 break;
1377 case C_HUB_LOCAL_POWER:
1378 dev_dbg(imx21->dev, " LOCAL_POWER\n");
1379 break;
1380 default:
1381 dev_dbg(imx21->dev, " unknown\n");
1382 rc = -EINVAL;
1383 break;
1384 }
1385 break;
1386
1387 case ClearPortFeature:
1388 dev_dbg(imx21->dev, "ClearPortFeature\n");
1389 switch (wValue) {
1390 case USB_PORT_FEAT_ENABLE:
1391 dev_dbg(imx21->dev, " ENABLE\n");
1392 status_write = USBH_PORTSTAT_CURCONST;
1393 break;
1394 case USB_PORT_FEAT_SUSPEND:
1395 dev_dbg(imx21->dev, " SUSPEND\n");
1396 status_write = USBH_PORTSTAT_PRTOVRCURI;
1397 break;
1398 case USB_PORT_FEAT_POWER:
1399 dev_dbg(imx21->dev, " POWER\n");
1400 status_write = USBH_PORTSTAT_LSDEVCON;
1401 break;
1402 case USB_PORT_FEAT_C_ENABLE:
1403 dev_dbg(imx21->dev, " C_ENABLE\n");
1404 status_write = USBH_PORTSTAT_PRTENBLSC;
1405 break;
1406 case USB_PORT_FEAT_C_SUSPEND:
1407 dev_dbg(imx21->dev, " C_SUSPEND\n");
1408 status_write = USBH_PORTSTAT_PRTSTATSC;
1409 break;
1410 case USB_PORT_FEAT_C_CONNECTION:
1411 dev_dbg(imx21->dev, " C_CONNECTION\n");
1412 status_write = USBH_PORTSTAT_CONNECTSC;
1413 break;
1414 case USB_PORT_FEAT_C_OVER_CURRENT:
1415 dev_dbg(imx21->dev, " C_OVER_CURRENT\n");
1416 status_write = USBH_PORTSTAT_OVRCURIC;
1417 break;
1418 case USB_PORT_FEAT_C_RESET:
1419 dev_dbg(imx21->dev, " C_RESET\n");
1420 status_write = USBH_PORTSTAT_PRTRSTSC;
1421 break;
1422 default:
1423 dev_dbg(imx21->dev, " unknown\n");
1424 rc = -EINVAL;
1425 break;
1426 }
1427
1428 break;
1429
1430 case GetHubDescriptor:
1431 dev_dbg(imx21->dev, "GetHubDescriptor\n");
1432 rc = get_hub_descriptor(hcd, (void *)buf);
1433 break;
1434
1435 case GetHubStatus:
1436 dev_dbg(imx21->dev, " GetHubStatus\n");
1437 *(__le32 *) buf = 0;
1438 break;
1439
1440 case GetPortStatus:
1441 dev_dbg(imx21->dev, "GetPortStatus: port: %d, 0x%x\n",
1442 wIndex, USBH_PORTSTAT(wIndex - 1));
1443 *(__le32 *) buf = readl(imx21->regs +
1444 USBH_PORTSTAT(wIndex - 1));
1445 break;
1446
1447 case SetHubFeature:
1448 dev_dbg(imx21->dev, "SetHubFeature\n");
1449 switch (wValue) {
1450 case C_HUB_OVER_CURRENT:
1451 dev_dbg(imx21->dev, " OVER_CURRENT\n");
1452 break;
1453
1454 case C_HUB_LOCAL_POWER:
1455 dev_dbg(imx21->dev, " LOCAL_POWER\n");
1456 break;
1457 default:
1458 dev_dbg(imx21->dev, " unknown\n");
1459 rc = -EINVAL;
1460 break;
1461 }
1462
1463 break;
1464
1465 case SetPortFeature:
1466 dev_dbg(imx21->dev, "SetPortFeature\n");
1467 switch (wValue) {
1468 case USB_PORT_FEAT_SUSPEND:
1469 dev_dbg(imx21->dev, " SUSPEND\n");
1470 status_write = USBH_PORTSTAT_PRTSUSPST;
1471 break;
1472 case USB_PORT_FEAT_POWER:
1473 dev_dbg(imx21->dev, " POWER\n");
1474 status_write = USBH_PORTSTAT_PRTPWRST;
1475 break;
1476 case USB_PORT_FEAT_RESET:
1477 dev_dbg(imx21->dev, " RESET\n");
1478 status_write = USBH_PORTSTAT_PRTRSTST;
1479 break;
1480 default:
1481 dev_dbg(imx21->dev, " unknown\n");
1482 rc = -EINVAL;
1483 break;
1484 }
1485 break;
1486
1487 default:
1488 dev_dbg(imx21->dev, " unknown\n");
1489 rc = -EINVAL;
1490 break;
1491 }
1492
1493 if (status_write)
1494 writel(status_write, imx21->regs + USBH_PORTSTAT(wIndex - 1));
1495 return rc;
1496}
1497
1498/* =========================================== */
1499/* Host controller management */
1500/* =========================================== */
1501
1502static int imx21_hc_reset(struct usb_hcd *hcd)
1503{
1504 struct imx21 *imx21 = hcd_to_imx21(hcd);
1505 unsigned long timeout;
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&imx21->lock, flags);
1509
1510 /* Reset the Host controler modules */
1511 writel(USBOTG_RST_RSTCTRL | USBOTG_RST_RSTRH |
1512 USBOTG_RST_RSTHSIE | USBOTG_RST_RSTHC,
1513 imx21->regs + USBOTG_RST_CTRL);
1514
1515 /* Wait for reset to finish */
1516 timeout = jiffies + HZ;
1517 while (readl(imx21->regs + USBOTG_RST_CTRL) != 0) {
1518 if (time_after(jiffies, timeout)) {
1519 spin_unlock_irqrestore(&imx21->lock, flags);
1520 dev_err(imx21->dev, "timeout waiting for reset\n");
1521 return -ETIMEDOUT;
1522 }
1523 spin_unlock_irq(&imx21->lock);
9a4b7c3b 1524 schedule_timeout_uninterruptible(1);
23d3e7a6
MF		 1525 spin_lock_irq(&imx21->lock);
1526 }
1527 spin_unlock_irqrestore(&imx21->lock, flags);
1528 return 0;
1529}
1530
1531static int __devinit imx21_hc_start(struct usb_hcd *hcd)
1532{
1533 struct imx21 *imx21 = hcd_to_imx21(hcd);
1534 unsigned long flags;
1535 int i, j;
1536 u32 hw_mode = USBOTG_HWMODE_CRECFG_HOST;
1537 u32 usb_control = 0;
1538
1539 hw_mode |= ((imx21->pdata->host_xcvr << USBOTG_HWMODE_HOSTXCVR_SHIFT) &
1540 USBOTG_HWMODE_HOSTXCVR_MASK);
1541 hw_mode |= ((imx21->pdata->otg_xcvr << USBOTG_HWMODE_OTGXCVR_SHIFT) &
1542 USBOTG_HWMODE_OTGXCVR_MASK);
1543
1544 if (imx21->pdata->host1_txenoe)
1545 usb_control |= USBCTRL_HOST1_TXEN_OE;
1546
1547 if (!imx21->pdata->host1_xcverless)
1548 usb_control |= USBCTRL_HOST1_BYP_TLL;
1549
1550 if (imx21->pdata->otg_ext_xcvr)
1551 usb_control |= USBCTRL_OTC_RCV_RXDP;
1552
1553
1554 spin_lock_irqsave(&imx21->lock, flags);
1555
1556 writel((USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN),
1557 imx21->regs + USBOTG_CLK_CTRL);
1558 writel(hw_mode, imx21->regs + USBOTG_HWMODE);
1559 writel(usb_control, imx21->regs + USBCTRL);
1560 writel(USB_MISCCONTROL_SKPRTRY | USB_MISCCONTROL_ARBMODE,
1561 imx21->regs + USB_MISCCONTROL);
1562
1563 /* Clear the ETDs */
1564 for (i = 0; i < USB_NUM_ETD; i++)
1565 for (j = 0; j < 4; j++)
1566 etd_writel(imx21, i, j, 0);
1567
1568 /* Take the HC out of reset */
1569 writel(USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL | USBH_HOST_CTRL_CTLBLKSR_1,
1570 imx21->regs + USBH_HOST_CTRL);
1571
1572 /* Enable ports */
1573 if (imx21->pdata->enable_otg_host)
1574 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1575 imx21->regs + USBH_PORTSTAT(0));
1576
1577 if (imx21->pdata->enable_host1)
1578 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1579 imx21->regs + USBH_PORTSTAT(1));
1580
1581 if (imx21->pdata->enable_host2)
1582 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1583 imx21->regs + USBH_PORTSTAT(2));
1584
1585
1586 hcd->state = HC_STATE_RUNNING;
1587
1588 /* Enable host controller interrupts */
1589 set_register_bits(imx21, USBH_SYSIEN,
1590 USBH_SYSIEN_HERRINT |
1591 USBH_SYSIEN_DONEINT | USBH_SYSIEN_SORINT);
1592 set_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
1593
1594 spin_unlock_irqrestore(&imx21->lock, flags);
1595
1596 return 0;
1597}
1598
1599static void imx21_hc_stop(struct usb_hcd *hcd)
1600{
1601 struct imx21 *imx21 = hcd_to_imx21(hcd);
1602 unsigned long flags;
1603
1604 spin_lock_irqsave(&imx21->lock, flags);
1605
1606 writel(0, imx21->regs + USBH_SYSIEN);
1607 clear_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
1608 clear_register_bits(imx21, USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN,
1609 USBOTG_CLK_CTRL);
1610 spin_unlock_irqrestore(&imx21->lock, flags);
1611}
1612
1613/* =========================================== */
1614/* Driver glue */
1615/* =========================================== */
1616
1617static struct hc_driver imx21_hc_driver = {
1618 .description = hcd_name,
1619 .product_desc = "IMX21 USB Host Controller",
1620 .hcd_priv_size = sizeof(struct imx21),
1621
1622 .flags = HCD_USB11,
1623 .irq = imx21_irq,
1624
1625 .reset = imx21_hc_reset,
1626 .start = imx21_hc_start,
1627 .stop = imx21_hc_stop,
1628
1629 /* I/O requests */
1630 .urb_enqueue = imx21_hc_urb_enqueue,
1631 .urb_dequeue = imx21_hc_urb_dequeue,
1632 .endpoint_disable = imx21_hc_endpoint_disable,
1633
1634 /* scheduling support */
1635 .get_frame_number = imx21_hc_get_frame,
1636
1637 /* Root hub support */
1638 .hub_status_data = imx21_hc_hub_status_data,
1639 .hub_control = imx21_hc_hub_control,
1640
1641};
1642
1643static struct mx21_usbh_platform_data default_pdata = {
1644 .host_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
1645 .otg_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
1646 .enable_host1 = 1,
1647 .enable_host2 = 1,
1648 .enable_otg_host = 1,
1649
1650};
1651
1652static int imx21_remove(struct platform_device *pdev)
1653{
1654 struct usb_hcd *hcd = platform_get_drvdata(pdev);
1655 struct imx21 *imx21 = hcd_to_imx21(hcd);
1656 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1657
1658 remove_debug_files(imx21);
1659 usb_remove_hcd(hcd);
1660
1661 if (res != NULL) {
1662 clk_disable(imx21->clk);
1663 clk_put(imx21->clk);
1664 iounmap(imx21->regs);
1665 release_mem_region(res->start, resource_size(res));
1666 }
1667
1668 kfree(hcd);
1669 return 0;
1670}
1671
1672
1673static int imx21_probe(struct platform_device *pdev)
1674{
1675 struct usb_hcd *hcd;
1676 struct imx21 *imx21;
1677 struct resource *res;
1678 int ret;
1679 int irq;
1680
1681 printk(KERN_INFO "%s\n", imx21_hc_driver.product_desc);
1682
1683 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1684 if (!res)
1685 return -ENODEV;
1686 irq = platform_get_irq(pdev, 0);
1687 if (irq < 0)
1688 return -ENXIO;
1689
1690 hcd = usb_create_hcd(&imx21_hc_driver,
1691 &pdev->dev, dev_name(&pdev->dev));
1692 if (hcd == NULL) {
1693 dev_err(&pdev->dev, "Cannot create hcd (%s)\n",
1694 dev_name(&pdev->dev));
1695 return -ENOMEM;
1696 }
1697
1698 imx21 = hcd_to_imx21(hcd);
1699 imx21->dev = &pdev->dev;
1700 imx21->pdata = pdev->dev.platform_data;
1701 if (!imx21->pdata)
1702 imx21->pdata = &default_pdata;
1703
1704 spin_lock_init(&imx21->lock);
1705 INIT_LIST_HEAD(&imx21->dmem_list);
1706 INIT_LIST_HEAD(&imx21->queue_for_etd);
1707 INIT_LIST_HEAD(&imx21->queue_for_dmem);
1708 create_debug_files(imx21);
1709
1710 res = request_mem_region(res->start, resource_size(res), hcd_name);
1711 if (!res) {
1712 ret = -EBUSY;
1713 goto failed_request_mem;
1714 }
1715
1716 imx21->regs = ioremap(res->start, resource_size(res));
1717 if (imx21->regs == NULL) {
1718 dev_err(imx21->dev, "Cannot map registers\n");
1719 ret = -ENOMEM;
1720 goto failed_ioremap;
1721 }
1722
1723 /* Enable clocks source */
1724 imx21->clk = clk_get(imx21->dev, NULL);
1725 if (IS_ERR(imx21->clk)) {
1726 dev_err(imx21->dev, "no clock found\n");
1727 ret = PTR_ERR(imx21->clk);
1728 goto failed_clock_get;
1729 }
1730
1731 ret = clk_set_rate(imx21->clk, clk_round_rate(imx21->clk, 48000000));
1732 if (ret)
1733 goto failed_clock_set;
1734 ret = clk_enable(imx21->clk);
1735 if (ret)
1736 goto failed_clock_enable;
1737
1738 dev_info(imx21->dev, "Hardware HC revision: 0x%02X\n",
1739 (readl(imx21->regs + USBOTG_HWMODE) >> 16) & 0xFF);
1740
1741 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED);
1742 if (ret != 0) {
1743 dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret);
1744 goto failed_add_hcd;
1745 }
1746
1747 return 0;
1748
1749failed_add_hcd:
1750 clk_disable(imx21->clk);
1751failed_clock_enable:
1752failed_clock_set:
1753 clk_put(imx21->clk);
1754failed_clock_get:
1755 iounmap(imx21->regs);
1756failed_ioremap:
1757 release_mem_region(res->start, res->end - res->start);
1758failed_request_mem:
1759 remove_debug_files(imx21);
1760 usb_put_hcd(hcd);
1761 return ret;
1762}
1763
1764static struct platform_driver imx21_hcd_driver = {
1765 .driver = {
1766 .name = (char *)hcd_name,
1767 },
1768 .probe = imx21_probe,
1769 .remove = imx21_remove,
1770 .suspend = NULL,
1771 .resume = NULL,
1772};
1773
1774static int __init imx21_hcd_init(void)
1775{
1776 return platform_driver_register(&imx21_hcd_driver);
1777}
1778
1779static void __exit imx21_hcd_cleanup(void)
1780{
1781 platform_driver_unregister(&imx21_hcd_driver);
1782}
1783
1784module_init(imx21_hcd_init);
1785module_exit(imx21_hcd_cleanup);
1786
1787MODULE_DESCRIPTION("i.MX21 USB Host controller");
1788MODULE_AUTHOR("Martin Fuzzey");
1789MODULE_LICENSE("GPL");
1790MODULE_ALIAS("platform:imx21-hcd");
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