[linux.git] / drivers / dma / dw / regs.h

/*
 * Driver for the Synopsys DesignWare AHB DMA Controller
 *
 * Copyright (C) 2005-2007 Atmel Corporation
 * Copyright (C) 2010-2011 ST Microelectronics
 * Copyright (C) 2016 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/dmaengine.h>

#include <linux/io-64-nonatomic-hi-lo.h>

#include "internal.h"

#define DW_DMA_MAX_NR_REQUESTS	16

/* flow controller */
enum dw_dma_fc {
	DW_DMA_FC_D_M2M,
	DW_DMA_FC_D_M2P,
	DW_DMA_FC_D_P2M,
	DW_DMA_FC_D_P2P,
	DW_DMA_FC_P_P2M,
	DW_DMA_FC_SP_P2P,
	DW_DMA_FC_P_M2P,
	DW_DMA_FC_DP_P2P,
};

/*
 * Redefine this macro to handle differences between 32- and 64-bit
 * addressing, big vs. little endian, etc.
 */
#define DW_REG(name)		u32 name; u32 __pad_##name

/* Hardware register definitions. */
struct dw_dma_chan_regs {
	DW_REG(SAR);		/* Source Address Register */
	DW_REG(DAR);		/* Destination Address Register */
	DW_REG(LLP);		/* Linked List Pointer */
	u32	CTL_LO;		/* Control Register Low */
	u32	CTL_HI;		/* Control Register High */
	DW_REG(SSTAT);
	DW_REG(DSTAT);
	DW_REG(SSTATAR);
	DW_REG(DSTATAR);
	u32	CFG_LO;		/* Configuration Register Low */
	u32	CFG_HI;		/* Configuration Register High */
	DW_REG(SGR);
	DW_REG(DSR);
};

struct dw_dma_irq_regs {
	DW_REG(XFER);
	DW_REG(BLOCK);
	DW_REG(SRC_TRAN);
	DW_REG(DST_TRAN);
	DW_REG(ERROR);
};

struct dw_dma_regs {
	/* per-channel registers */
	struct dw_dma_chan_regs	CHAN[DW_DMA_MAX_NR_CHANNELS];

	/* irq handling */
	struct dw_dma_irq_regs	RAW;		/* r */
	struct dw_dma_irq_regs	STATUS;		/* r (raw & mask) */
	struct dw_dma_irq_regs	MASK;		/* rw (set = irq enabled) */
	struct dw_dma_irq_regs	CLEAR;		/* w (ack, affects "raw") */

	DW_REG(STATUS_INT);			/* r */

	/* software handshaking */
	DW_REG(REQ_SRC);
	DW_REG(REQ_DST);
	DW_REG(SGL_REQ_SRC);
	DW_REG(SGL_REQ_DST);
	DW_REG(LAST_SRC);
	DW_REG(LAST_DST);

	/* miscellaneous */
	DW_REG(CFG);
	DW_REG(CH_EN);
	DW_REG(ID);
	DW_REG(TEST);

	/* iDMA 32-bit support */
	DW_REG(CLASS_PRIORITY0);
	DW_REG(CLASS_PRIORITY1);

	/* optional encoded params, 0x3c8..0x3f7 */
	u32	__reserved;

	/* per-channel configuration registers */
	u32	DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
	u32	MULTI_BLK_TYPE;
	u32	MAX_BLK_SIZE;

	/* top-level parameters */
	u32	DW_PARAMS;

	/* component ID */
	u32	COMP_TYPE;
	u32	COMP_VERSION;

	/* iDMA 32-bit support */
	DW_REG(FIFO_PARTITION0);
	DW_REG(FIFO_PARTITION1);

	DW_REG(SAI_ERR);
	DW_REG(GLOBAL_CFG);
};

/* Bitfields in DW_PARAMS */
#define DW_PARAMS_NR_CHAN	8		/* number of channels */
#define DW_PARAMS_NR_MASTER	11		/* number of AHB masters */
#define DW_PARAMS_DATA_WIDTH(n)	(15 + 2 * (n))
#define DW_PARAMS_DATA_WIDTH1	15		/* master 1 data width */
#define DW_PARAMS_DATA_WIDTH2	17		/* master 2 data width */
#define DW_PARAMS_DATA_WIDTH3	19		/* master 3 data width */
#define DW_PARAMS_DATA_WIDTH4	21		/* master 4 data width */
#define DW_PARAMS_EN		28		/* encoded parameters */

/* Bitfields in DWC_PARAMS */
#define DWC_PARAMS_MBLK_EN	11		/* multi block transfer */

/* bursts size */
enum dw_dma_msize {
	DW_DMA_MSIZE_1,
	DW_DMA_MSIZE_4,
	DW_DMA_MSIZE_8,
	DW_DMA_MSIZE_16,
	DW_DMA_MSIZE_32,
	DW_DMA_MSIZE_64,
	DW_DMA_MSIZE_128,
	DW_DMA_MSIZE_256,
};

/* Bitfields in LLP */
#define DWC_LLP_LMS(x)		((x) & 3)	/* list master select */
#define DWC_LLP_LOC(x)		((x) & ~3)	/* next lli */

/* Bitfields in CTL_LO */
#define DWC_CTLL_INT_EN		(1 << 0)	/* irqs enabled? */
#define DWC_CTLL_DST_WIDTH(n)	((n)<<1)	/* bytes per element */
#define DWC_CTLL_SRC_WIDTH(n)	((n)<<4)
#define DWC_CTLL_DST_INC	(0<<7)		/* DAR update/not */
#define DWC_CTLL_DST_DEC	(1<<7)
#define DWC_CTLL_DST_FIX	(2<<7)
#define DWC_CTLL_SRC_INC	(0<<9)		/* SAR update/not */
#define DWC_CTLL_SRC_DEC	(1<<9)
#define DWC_CTLL_SRC_FIX	(2<<9)
#define DWC_CTLL_DST_MSIZE(n)	((n)<<11)	/* burst, #elements */
#define DWC_CTLL_SRC_MSIZE(n)	((n)<<14)
#define DWC_CTLL_S_GATH_EN	(1 << 17)	/* src gather, !FIX */
#define DWC_CTLL_D_SCAT_EN	(1 << 18)	/* dst scatter, !FIX */
#define DWC_CTLL_FC(n)		((n) << 20)
#define DWC_CTLL_FC_M2M		(0 << 20)	/* mem-to-mem */
#define DWC_CTLL_FC_M2P		(1 << 20)	/* mem-to-periph */
#define DWC_CTLL_FC_P2M		(2 << 20)	/* periph-to-mem */
#define DWC_CTLL_FC_P2P		(3 << 20)	/* periph-to-periph */
/* plus 4 transfer types for peripheral-as-flow-controller */
#define DWC_CTLL_DMS(n)		((n)<<23)	/* dst master select */
#define DWC_CTLL_SMS(n)		((n)<<25)	/* src master select */
#define DWC_CTLL_LLP_D_EN	(1 << 27)	/* dest block chain */
#define DWC_CTLL_LLP_S_EN	(1 << 28)	/* src block chain */

/* Bitfields in CTL_HI */
#define DWC_CTLH_BLOCK_TS_MASK	GENMASK(11, 0)
#define DWC_CTLH_BLOCK_TS(x)	((x) & DWC_CTLH_BLOCK_TS_MASK)
#define DWC_CTLH_DONE		(1 << 12)

/* Bitfields in CFG_LO */
#define DWC_CFGL_CH_PRIOR_MASK	(0x7 << 5)	/* priority mask */
#define DWC_CFGL_CH_PRIOR(x)	((x) << 5)	/* priority */
#define DWC_CFGL_CH_SUSP	(1 << 8)	/* pause xfer */
#define DWC_CFGL_FIFO_EMPTY	(1 << 9)	/* pause xfer */
#define DWC_CFGL_HS_DST		(1 << 10)	/* handshake w/dst */
#define DWC_CFGL_HS_SRC		(1 << 11)	/* handshake w/src */
#define DWC_CFGL_LOCK_CH_XFER	(0 << 12)	/* scope of LOCK_CH */
#define DWC_CFGL_LOCK_CH_BLOCK	(1 << 12)
#define DWC_CFGL_LOCK_CH_XACT	(2 << 12)
#define DWC_CFGL_LOCK_BUS_XFER	(0 << 14)	/* scope of LOCK_BUS */
#define DWC_CFGL_LOCK_BUS_BLOCK	(1 << 14)
#define DWC_CFGL_LOCK_BUS_XACT	(2 << 14)
#define DWC_CFGL_LOCK_CH	(1 << 15)	/* channel lockout */
#define DWC_CFGL_LOCK_BUS	(1 << 16)	/* busmaster lockout */
#define DWC_CFGL_HS_DST_POL	(1 << 18)	/* dst handshake active low */
#define DWC_CFGL_HS_SRC_POL	(1 << 19)	/* src handshake active low */
#define DWC_CFGL_MAX_BURST(x)	((x) << 20)
#define DWC_CFGL_RELOAD_SAR	(1 << 30)
#define DWC_CFGL_RELOAD_DAR	(1 << 31)

/* Bitfields in CFG_HI */
#define DWC_CFGH_FCMODE		(1 << 0)
#define DWC_CFGH_FIFO_MODE	(1 << 1)
#define DWC_CFGH_PROTCTL(x)	((x) << 2)
#define DWC_CFGH_DS_UPD_EN	(1 << 5)
#define DWC_CFGH_SS_UPD_EN	(1 << 6)
#define DWC_CFGH_SRC_PER(x)	((x) << 7)
#define DWC_CFGH_DST_PER(x)	((x) << 11)

/* Bitfields in SGR */
#define DWC_SGR_SGI(x)		((x) << 0)
#define DWC_SGR_SGC(x)		((x) << 20)

/* Bitfields in DSR */
#define DWC_DSR_DSI(x)		((x) << 0)
#define DWC_DSR_DSC(x)		((x) << 20)

/* Bitfields in CFG */
#define DW_CFG_DMA_EN		(1 << 0)

/* iDMA 32-bit support */

/* Bitfields in CTL_HI */
#define IDMA32C_CTLH_BLOCK_TS_MASK	GENMASK(16, 0)
#define IDMA32C_CTLH_BLOCK_TS(x)	((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
#define IDMA32C_CTLH_DONE		(1 << 17)

/* Bitfields in CFG_LO */
#define IDMA32C_CFGL_DST_BURST_ALIGN	(1 << 0)	/* dst burst align */
#define IDMA32C_CFGL_SRC_BURST_ALIGN	(1 << 1)	/* src burst align */
#define IDMA32C_CFGL_CH_DRAIN		(1 << 10)	/* drain FIFO */
#define IDMA32C_CFGL_DST_OPT_BL		(1 << 20)	/* optimize dst burst length */
#define IDMA32C_CFGL_SRC_OPT_BL		(1 << 21)	/* optimize src burst length */

/* Bitfields in CFG_HI */
#define IDMA32C_CFGH_SRC_PER(x)		((x) << 0)
#define IDMA32C_CFGH_DST_PER(x)		((x) << 4)
#define IDMA32C_CFGH_RD_ISSUE_THD(x)	((x) << 8)
#define IDMA32C_CFGH_RW_ISSUE_THD(x)	((x) << 18)
#define IDMA32C_CFGH_SRC_PER_EXT(x)	((x) << 28)	/* src peripheral extension */
#define IDMA32C_CFGH_DST_PER_EXT(x)	((x) << 30)	/* dst peripheral extension */

/* Bitfields in FIFO_PARTITION */
#define IDMA32C_FP_PSIZE_CH0(x)		((x) << 0)
#define IDMA32C_FP_PSIZE_CH1(x)		((x) << 13)
#define IDMA32C_FP_UPDATE		(1 << 26)

enum dw_dmac_flags {
	DW_DMA_IS_CYCLIC = 0,
	DW_DMA_IS_SOFT_LLP = 1,
	DW_DMA_IS_PAUSED = 2,
	DW_DMA_IS_INITIALIZED = 3,
};

struct dw_dma_chan {
	struct dma_chan			chan;
	void __iomem			*ch_regs;
	u8				mask;
	u8				priority;
	enum dma_transfer_direction	direction;

	/* software emulation of the LLP transfers */
	struct list_head	*tx_node_active;

	spinlock_t		lock;

	/* these other elements are all protected by lock */
	unsigned long		flags;
	struct list_head	active_list;
	struct list_head	queue;

	unsigned int		descs_allocated;

	/* hardware configuration */
	unsigned int		block_size;
	bool			nollp;

	/* custom slave configuration */
	struct dw_dma_slave	dws;

	/* configuration passed via .device_config */
	struct dma_slave_config dma_sconfig;
};

static inline struct dw_dma_chan_regs __iomem *
__dwc_regs(struct dw_dma_chan *dwc)
{
	return dwc->ch_regs;
}

#define channel_readl(dwc, name) \
	readl(&(__dwc_regs(dwc)->name))
#define channel_writel(dwc, name, val) \
	writel((val), &(__dwc_regs(dwc)->name))

static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct dw_dma_chan, chan);
}

struct dw_dma {
	struct dma_device	dma;
	char			name[20];
	void __iomem		*regs;
	struct dma_pool		*desc_pool;
	struct tasklet_struct	tasklet;

	/* channels */
	struct dw_dma_chan	*chan;
	u8			all_chan_mask;
	u8			in_use;

	/* platform data */
	struct dw_dma_platform_data	*pdata;
};

static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
{
	return dw->regs;
}

#define dma_readl(dw, name) \
	readl(&(__dw_regs(dw)->name))
#define dma_writel(dw, name, val) \
	writel((val), &(__dw_regs(dw)->name))

#define idma32_readq(dw, name)				\
	hi_lo_readq(&(__dw_regs(dw)->name))
#define idma32_writeq(dw, name, val)			\
	hi_lo_writeq((val), &(__dw_regs(dw)->name))

#define channel_set_bit(dw, reg, mask) \
	dma_writel(dw, reg, ((mask) << 8) | (mask))
#define channel_clear_bit(dw, reg, mask) \
	dma_writel(dw, reg, ((mask) << 8) | 0)

static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
{
	return container_of(ddev, struct dw_dma, dma);
}

/* LLI == Linked List Item; a.k.a. DMA block descriptor */
struct dw_lli {
	/* values that are not changed by hardware */
	__le32		sar;
	__le32		dar;
	__le32		llp;		/* chain to next lli */
	__le32		ctllo;
	/* values that may get written back: */
	__le32		ctlhi;
	/* sstat and dstat can snapshot peripheral register state.
	 * silicon config may discard either or both...
	 */
	__le32		sstat;
	__le32		dstat;
};

struct dw_desc {
	/* FIRST values the hardware uses */
	struct dw_lli			lli;

#define lli_set(d, reg, v)		((d)->lli.reg |= cpu_to_le32(v))
#define lli_clear(d, reg, v)		((d)->lli.reg &= ~cpu_to_le32(v))
#define lli_read(d, reg)		le32_to_cpu((d)->lli.reg)
#define lli_write(d, reg, v)		((d)->lli.reg = cpu_to_le32(v))

	/* THEN values for driver housekeeping */
	struct list_head		desc_node;
	struct list_head		tx_list;
	struct dma_async_tx_descriptor	txd;
	size_t				len;
	size_t				total_len;
	u32				residue;
};

#define to_dw_desc(h)	list_entry(h, struct dw_desc, desc_node)

static inline struct dw_desc *
txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
{
	return container_of(txd, struct dw_desc, txd);
}
Commit	Line	Data
3bfb1d20 HS	1	/*
	2	* Driver for the Synopsys DesignWare AHB DMA Controller
	3	*
	4	* Copyright (C) 2005-2007 Atmel Corporation
aecb7b64	5	* Copyright (C) 2010-2011 ST Microelectronics
a9f4d1b8	6	* Copyright (C) 2016 Intel Corporation
3bfb1d20 HS	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
2d248812	13	#include <linux/bitops.h>
9cade1a4	14	#include <linux/interrupt.h>
0fdb567f	15	#include <linux/dmaengine.h>
3bfb1d20	16
a9f4d1b8 AS	17	#include <linux/io-64-nonatomic-hi-lo.h>
a9f4d1b8 AS	18
bd2c6636 EP	19	#include "internal.h"
bd2c6636 EP	20
f9c6a655	21	#define DW_DMA_MAX_NR_REQUESTS 16
3bfb1d20	22
a1c46016 VK	23	/* flow controller */
	24	enum dw_dma_fc {
	25	DW_DMA_FC_D_M2M,
	26	DW_DMA_FC_D_M2P,
	27	DW_DMA_FC_D_P2M,
	28	DW_DMA_FC_D_P2P,
	29	DW_DMA_FC_P_P2M,
	30	DW_DMA_FC_SP_P2P,
	31	DW_DMA_FC_P_M2P,
	32	DW_DMA_FC_DP_P2P,
	33	};
	34
3bfb1d20 HS	35	/*
	36	* Redefine this macro to handle differences between 32- and 64-bit
	37	* addressing, big vs. little endian, etc.
	38	*/
	39	#define DW_REG(name) u32 name; u32 __pad_##name
	40
	41	/* Hardware register definitions. */
	42	struct dw_dma_chan_regs {
	43	DW_REG(SAR); /* Source Address Register */
	44	DW_REG(DAR); /* Destination Address Register */
	45	DW_REG(LLP); /* Linked List Pointer */
	46	u32 CTL_LO; /* Control Register Low */
	47	u32 CTL_HI; /* Control Register High */
	48	DW_REG(SSTAT);
	49	DW_REG(DSTAT);
	50	DW_REG(SSTATAR);
	51	DW_REG(DSTATAR);
	52	u32 CFG_LO; /* Configuration Register Low */
	53	u32 CFG_HI; /* Configuration Register High */
	54	DW_REG(SGR);
	55	DW_REG(DSR);
	56	};
	57
	58	struct dw_dma_irq_regs {
	59	DW_REG(XFER);
	60	DW_REG(BLOCK);
	61	DW_REG(SRC_TRAN);
	62	DW_REG(DST_TRAN);
	63	DW_REG(ERROR);
	64	};
	65
	66	struct dw_dma_regs {
	67	/* per-channel registers */
	68	struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
	69
	70	/* irq handling */
	71	struct dw_dma_irq_regs RAW; /* r */
	72	struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
	73	struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
	74	struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
	75
	76	DW_REG(STATUS_INT); /* r */
	77
	78	/* software handshaking */
	79	DW_REG(REQ_SRC);
	80	DW_REG(REQ_DST);
	81	DW_REG(SGL_REQ_SRC);
	82	DW_REG(SGL_REQ_DST);
	83	DW_REG(LAST_SRC);
	84	DW_REG(LAST_DST);
	85
	86	/* miscellaneous */
	87	DW_REG(CFG);
	88	DW_REG(CH_EN);
	89	DW_REG(ID);
	90	DW_REG(TEST);
	91
a9f4d1b8 AS	92	/* iDMA 32-bit support */
	93	DW_REG(CLASS_PRIORITY0);
	94	DW_REG(CLASS_PRIORITY1);
2a9fe9ae	95
745664eb	96	/* optional encoded params, 0x3c8..0x3f7 */
2a9fe9ae AS	97	u32 __reserved;
	98
	99	/* per-channel configuration registers */
	100	u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
	101	u32 MULTI_BLK_TYPE;
	102	u32 MAX_BLK_SIZE;
	103
	104	/* top-level parameters */
	105	u32 DW_PARAMS;
a9f4d1b8 AS	106
	107	/* component ID */
	108	u32 COMP_TYPE;
	109	u32 COMP_VERSION;
	110
	111	/* iDMA 32-bit support */
	112	DW_REG(FIFO_PARTITION0);
	113	DW_REG(FIFO_PARTITION1);
	114
	115	DW_REG(SAI_ERR);
	116	DW_REG(GLOBAL_CFG);
3bfb1d20 HS	117	};
3bfb1d20 HS	118
2a9fe9ae AS	119	/* Bitfields in DW_PARAMS */
	120	#define DW_PARAMS_NR_CHAN 8 /* number of channels */
	121	#define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
	122	#define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
	123	#define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */
	124	#define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */
	125	#define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */
	126	#define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */
	127	#define DW_PARAMS_EN 28 /* encoded parameters */
	128
	129	/* Bitfields in DWC_PARAMS */
	130	#define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
	131
46e8c83c AS	132	/* bursts size */
	133	enum dw_dma_msize {
	134	DW_DMA_MSIZE_1,
	135	DW_DMA_MSIZE_4,
	136	DW_DMA_MSIZE_8,
	137	DW_DMA_MSIZE_16,
	138	DW_DMA_MSIZE_32,
	139	DW_DMA_MSIZE_64,
	140	DW_DMA_MSIZE_128,
	141	DW_DMA_MSIZE_256,
	142	};
	143
2a0fae02 MR	144	/* Bitfields in LLP */
	145	#define DWC_LLP_LMS(x) ((x) & 3) /* list master select */
	146	#define DWC_LLP_LOC(x) ((x) & ~3) /* next lli */
	147
3bfb1d20 HS	148	/* Bitfields in CTL_LO */
	149	#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
	150	#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
	151	#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
	152	#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
	153	#define DWC_CTLL_DST_DEC (1<<7)
	154	#define DWC_CTLL_DST_FIX (2<<7)
c9784a46	155	#define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */
3bfb1d20 HS	156	#define DWC_CTLL_SRC_DEC (1<<9)
	157	#define DWC_CTLL_SRC_FIX (2<<9)
	158	#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
	159	#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
	160	#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
	161	#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
ee66509d	162	#define DWC_CTLL_FC(n) ((n) << 20)
3bfb1d20 HS	163	#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
	164	#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
	165	#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
	166	#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
	167	/* plus 4 transfer types for peripheral-as-flow-controller */
	168	#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
	169	#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
	170	#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
	171	#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
	172
	173	/* Bitfields in CTL_HI */
2d248812 AS	174	#define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0)
	175	#define DWC_CTLH_BLOCK_TS(x) ((x) & DWC_CTLH_BLOCK_TS_MASK)
	176	#define DWC_CTLH_DONE (1 << 12)
3bfb1d20	177
46e8c83c	178	/* Bitfields in CFG_LO */
93317e8e VK	179	#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
93317e8e VK	180	#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
3bfb1d20 HS	181	#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
	182	#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
	183	#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
	184	#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
46e8c83c AS	185	#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
	186	#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
	187	#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
	188	#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
	189	#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
	190	#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
	191	#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
	192	#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
	193	#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
	194	#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
3bfb1d20 HS	195	#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
	196	#define DWC_CFGL_RELOAD_SAR (1 << 30)
	197	#define DWC_CFGL_RELOAD_DAR (1 << 31)
	198
46e8c83c AS	199	/* Bitfields in CFG_HI */
	200	#define DWC_CFGH_FCMODE (1 << 0)
	201	#define DWC_CFGH_FIFO_MODE (1 << 1)
	202	#define DWC_CFGH_PROTCTL(x) ((x) << 2)
3bfb1d20 HS	203	#define DWC_CFGH_DS_UPD_EN (1 << 5)
3bfb1d20 HS	204	#define DWC_CFGH_SS_UPD_EN (1 << 6)
46e8c83c AS	205	#define DWC_CFGH_SRC_PER(x) ((x) << 7)
46e8c83c AS	206	#define DWC_CFGH_DST_PER(x) ((x) << 11)
3bfb1d20 HS	207
	208	/* Bitfields in SGR */
	209	#define DWC_SGR_SGI(x) ((x) << 0)
	210	#define DWC_SGR_SGC(x) ((x) << 20)
	211
	212	/* Bitfields in DSR */
	213	#define DWC_DSR_DSI(x) ((x) << 0)
	214	#define DWC_DSR_DSC(x) ((x) << 20)
	215
	216	/* Bitfields in CFG */
	217	#define DW_CFG_DMA_EN (1 << 0)
	218
a9f4d1b8 AS	219	/* iDMA 32-bit support */
	220
	221	/* Bitfields in CTL_HI */
	222	#define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)
	223	#define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
	224	#define IDMA32C_CTLH_DONE (1 << 17)
	225
	226	/* Bitfields in CFG_LO */
	227	#define IDMA32C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
	228	#define IDMA32C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
	229	#define IDMA32C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */
	230	#define IDMA32C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */
	231	#define IDMA32C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */
	232
	233	/* Bitfields in CFG_HI */
	234	#define IDMA32C_CFGH_SRC_PER(x) ((x) << 0)
	235	#define IDMA32C_CFGH_DST_PER(x) ((x) << 4)
	236	#define IDMA32C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
	237	#define IDMA32C_CFGH_RW_ISSUE_THD(x) ((x) << 18)
	238	#define IDMA32C_CFGH_SRC_PER_EXT(x) ((x) << 28) /* src peripheral extension */
	239	#define IDMA32C_CFGH_DST_PER_EXT(x) ((x) << 30) /* dst peripheral extension */
	240
	241	/* Bitfields in FIFO_PARTITION */
	242	#define IDMA32C_FP_PSIZE_CH0(x) ((x) << 0)
	243	#define IDMA32C_FP_PSIZE_CH1(x) ((x) << 13)
	244	#define IDMA32C_FP_UPDATE (1 << 26)
	245
d9de4519 HCE	246	enum dw_dmac_flags {
d9de4519 HCE	247	DW_DMA_IS_CYCLIC = 0,
fed2574b	248	DW_DMA_IS_SOFT_LLP = 1,
5e09f98e	249	DW_DMA_IS_PAUSED = 2,
423f9cbf	250	DW_DMA_IS_INITIALIZED = 3,
d9de4519 HCE	251	};
d9de4519 HCE	252
3bfb1d20	253	struct dw_dma_chan {
0fdb567f AS	254	struct dma_chan chan;
	255	void __iomem *ch_regs;
	256	u8 mask;
	257	u8 priority;
	258	enum dma_transfer_direction direction;
3bfb1d20	259
fed2574b	260	/* software emulation of the LLP transfers */
fed2574b AS	261	struct list_head *tx_node_active;
fed2574b AS	262
3bfb1d20 HS	263	spinlock_t lock;
	264
	265	/* these other elements are all protected by lock */
d9de4519	266	unsigned long flags;
3bfb1d20 HS	267	struct list_head active_list;
3bfb1d20 HS	268	struct list_head queue;
3bfb1d20	269
3bfb1d20	270	unsigned int descs_allocated;
327e6970	271
4a63a8b3 AS	272	/* hardware configuration */
4a63a8b3 AS	273	unsigned int block_size;
fed2574b	274	bool nollp;
f776076b AB	275
f776076b AB	276	/* custom slave configuration */
9217a5bf	277	struct dw_dma_slave dws;
4a63a8b3	278
295d3e10	279	/* configuration passed via .device_config */
327e6970	280	struct dma_slave_config dma_sconfig;
3bfb1d20 HS	281	};
	282
	283	static inline struct dw_dma_chan_regs __iomem *
	284	__dwc_regs(struct dw_dma_chan *dwc)
	285	{
	286	return dwc->ch_regs;
	287	}
	288
	289	#define channel_readl(dwc, name) \
14bebd01	290	readl(&(__dwc_regs(dwc)->name))
3bfb1d20	291	#define channel_writel(dwc, name, val) \
14bebd01	292	writel((val), &(__dwc_regs(dwc)->name))
3bfb1d20 HS	293
	294	static inline struct dw_dma_chan to_dw_dma_chan(struct dma_chan chan)
	295	{
	296	return container_of(chan, struct dw_dma_chan, chan);
	297	}
	298
3bfb1d20 HS	299	struct dw_dma {
3bfb1d20 HS	300	struct dma_device dma;
08d62f58	301	char name[20];
3bfb1d20	302	void __iomem *regs;
f8122a82	303	struct dma_pool *desc_pool;
3bfb1d20	304	struct tasklet_struct tasklet;
3bfb1d20	305
000871ce AS	306	/* channels */
000871ce AS	307	struct dw_dma_chan *chan;
3bfb1d20	308	u8 all_chan_mask;
99d9bf4e	309	u8 in_use;
3bfb1d20	310
161c3d04 AS	311	/* platform data */
161c3d04 AS	312	struct dw_dma_platform_data *pdata;
3bfb1d20 HS	313	};
	314
	315	static inline struct dw_dma_regs __iomem __dw_regs(struct dw_dma dw)
	316	{
	317	return dw->regs;
	318	}
	319
	320	#define dma_readl(dw, name) \
14bebd01	321	readl(&(__dw_regs(dw)->name))
3bfb1d20	322	#define dma_writel(dw, name, val) \
14bebd01	323	writel((val), &(__dw_regs(dw)->name))
3bfb1d20	324
a9f4d1b8 AS	325	#define idma32_readq(dw, name) \
	326	hi_lo_readq(&(__dw_regs(dw)->name))
	327	#define idma32_writeq(dw, name, val) \
	328	hi_lo_writeq((val), &(__dw_regs(dw)->name))
	329
3bfb1d20 HS	330	#define channel_set_bit(dw, reg, mask) \
	331	dma_writel(dw, reg, ((mask) << 8) \| (mask))
	332	#define channel_clear_bit(dw, reg, mask) \
	333	dma_writel(dw, reg, ((mask) << 8) \| 0)
	334
	335	static inline struct dw_dma to_dw_dma(struct dma_device ddev)
	336	{
	337	return container_of(ddev, struct dw_dma, dma);
	338	}
	339
	340	/* LLI == Linked List Item; a.k.a. DMA block descriptor */
	341	struct dw_lli {
	342	/* values that are not changed by hardware */
14bebd01 AS	343	__le32 sar;
	344	__le32 dar;
	345	__le32 llp; /* chain to next lli */
	346	__le32 ctllo;
3bfb1d20	347	/* values that may get written back: */
14bebd01	348	__le32 ctlhi;
3bfb1d20 HS	349	/* sstat and dstat can snapshot peripheral register state.
	350	* silicon config may discard either or both...
	351	*/
14bebd01 AS	352	__le32 sstat;
14bebd01 AS	353	__le32 dstat;
3bfb1d20 HS	354	};
	355
	356	struct dw_desc {
	357	/* FIRST values the hardware uses */
	358	struct dw_lli lli;
	359
df1f3a23 MR	360	#define lli_set(d, reg, v) ((d)->lli.reg \|= cpu_to_le32(v))
	361	#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v))
	362	#define lli_read(d, reg) le32_to_cpu((d)->lli.reg)
	363	#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v))
df1f3a23	364
3bfb1d20 HS	365	/* THEN values for driver housekeeping */
3bfb1d20 HS	366	struct list_head desc_node;
e0bd0f8c	367	struct list_head tx_list;
3bfb1d20 HS	368	struct dma_async_tx_descriptor txd;
3bfb1d20 HS	369	size_t len;
30d38a32	370	size_t total_len;
b68fd097	371	u32 residue;
3bfb1d20 HS	372	};
3bfb1d20 HS	373
e63a47a3 AS	374	#define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
e63a47a3 AS	375
3bfb1d20 HS	376	static inline struct dw_desc *
	377	txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
	378	{
	379	return container_of(txd, struct dw_desc, txd);
	380	}