[linux.git] / arch / arm / plat-omap / dmtimer.c

/*
 * linux/arch/arm/plat-omap/dmtimer.c
 *
 * OMAP Dual-Mode Timers
 *
 * Copyright (C) 2005 Nokia Corporation
 * OMAP2 support by Juha Yrjola
 * API improvements and OMAP2 clock framework support by Timo Teras
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <asm/hardware.h>
#include <asm/arch/dmtimer.h>
#include <asm/io.h>
#include <asm/arch/irqs.h>

/* register offsets */
#define OMAP_TIMER_ID_REG		0x00
#define OMAP_TIMER_OCP_CFG_REG		0x10
#define OMAP_TIMER_SYS_STAT_REG		0x14
#define OMAP_TIMER_STAT_REG		0x18
#define OMAP_TIMER_INT_EN_REG		0x1c
#define OMAP_TIMER_WAKEUP_EN_REG	0x20
#define OMAP_TIMER_CTRL_REG		0x24
#define OMAP_TIMER_COUNTER_REG		0x28
#define OMAP_TIMER_LOAD_REG		0x2c
#define OMAP_TIMER_TRIGGER_REG		0x30
#define OMAP_TIMER_WRITE_PEND_REG 	0x34
#define OMAP_TIMER_MATCH_REG		0x38
#define OMAP_TIMER_CAPTURE_REG		0x3c
#define OMAP_TIMER_IF_CTRL_REG		0x40

/* timer control reg bits */
#define OMAP_TIMER_CTRL_GPOCFG		(1 << 14)
#define OMAP_TIMER_CTRL_CAPTMODE	(1 << 13)
#define OMAP_TIMER_CTRL_PT		(1 << 12)
#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH	(0x1 << 8)
#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW	(0x2 << 8)
#define OMAP_TIMER_CTRL_TCM_BOTHEDGES	(0x3 << 8)
#define OMAP_TIMER_CTRL_SCPWM		(1 << 7)
#define OMAP_TIMER_CTRL_CE		(1 << 6)	/* compare enable */
#define OMAP_TIMER_CTRL_PRE		(1 << 5)	/* prescaler enable */
#define OMAP_TIMER_CTRL_PTV_SHIFT	2		/* how much to shift the prescaler value */
#define OMAP_TIMER_CTRL_AR		(1 << 1)	/* auto-reload enable */
#define OMAP_TIMER_CTRL_ST		(1 << 0)	/* start timer */

struct omap_dm_timer {
	unsigned long phys_base;
	int irq;
#ifdef CONFIG_ARCH_OMAP2
	struct clk *iclk, *fclk;
#endif
	void __iomem *io_base;
	unsigned reserved:1;
	unsigned enabled:1;
};

#ifdef CONFIG_ARCH_OMAP1

#define omap_dm_clk_enable(x)
#define omap_dm_clk_disable(x)

static struct omap_dm_timer dm_timers[] = {
	{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
	{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
	{ .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
	{ .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
	{ .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
	{ .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
	{ .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
	{ .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
};

#elif defined(CONFIG_ARCH_OMAP2)

#define omap_dm_clk_enable(x) clk_enable(x)
#define omap_dm_clk_disable(x) clk_disable(x)

static struct omap_dm_timer dm_timers[] = {
	{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
	{ .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
	{ .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
	{ .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
	{ .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
	{ .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
	{ .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
	{ .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
	{ .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
	{ .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
	{ .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
	{ .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
};

static const char *dm_source_names[] = {
	"sys_ck",
	"func_32k_ck",
	"alt_ck"
};

static struct clk *dm_source_clocks[3];

#else

#error OMAP architecture not supported!

#endif

static const int dm_timer_count = ARRAY_SIZE(dm_timers);
static spinlock_t dm_timer_lock;

static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
{
	return readl(timer->io_base + reg);
}

static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
{
	writel(value, timer->io_base + reg);
	while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
		;
}

static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
{
	int c;

	c = 0;
	while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
		c++;
		if (c > 100000) {
			printk(KERN_ERR "Timer failed to reset\n");
			return;
		}
	}
}

static void omap_dm_timer_reset(struct omap_dm_timer *timer)
{
	u32 l;

	if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
		omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
		omap_dm_timer_wait_for_reset(timer);
	}
	omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);

	/* Set to smart-idle mode */
	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
	l |= 0x02 << 3;

	if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
		/* Enable wake-up only for GPT1 on OMAP2 CPUs*/
		l |= 1 << 2;
		/* Non-posted mode */
		omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
	}
	omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
}

static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
	omap_dm_timer_enable(timer);
	omap_dm_timer_reset(timer);
}

struct omap_dm_timer *omap_dm_timer_request(void)
{
	struct omap_dm_timer *timer = NULL;
	unsigned long flags;
	int i;

	spin_lock_irqsave(&dm_timer_lock, flags);
	for (i = 0; i < dm_timer_count; i++) {
		if (dm_timers[i].reserved)
			continue;

		timer = &dm_timers[i];
		timer->reserved = 1;
		break;
	}
	spin_unlock_irqrestore(&dm_timer_lock, flags);

	if (timer != NULL)
		omap_dm_timer_prepare(timer);

	return timer;
}

struct omap_dm_timer *omap_dm_timer_request_specific(int id)
{
	struct omap_dm_timer *timer;
	unsigned long flags;

	spin_lock_irqsave(&dm_timer_lock, flags);
	if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
		spin_unlock_irqrestore(&dm_timer_lock, flags);
		printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
		       __FILE__, __LINE__, __FUNCTION__, id);
		dump_stack();
		return NULL;
	}

	timer = &dm_timers[id-1];
	timer->reserved = 1;
	spin_unlock_irqrestore(&dm_timer_lock, flags);

	omap_dm_timer_prepare(timer);

	return timer;
}

void omap_dm_timer_free(struct omap_dm_timer *timer)
{
	omap_dm_timer_enable(timer);
	omap_dm_timer_reset(timer);
	omap_dm_timer_disable(timer);

	WARN_ON(!timer->reserved);
	timer->reserved = 0;
}

void omap_dm_timer_enable(struct omap_dm_timer *timer)
{
	if (timer->enabled)
		return;

	omap_dm_clk_enable(timer->fclk);
	omap_dm_clk_enable(timer->iclk);

	timer->enabled = 1;
}

void omap_dm_timer_disable(struct omap_dm_timer *timer)
{
	if (!timer->enabled)
		return;

	omap_dm_clk_disable(timer->iclk);
	omap_dm_clk_disable(timer->fclk);

	timer->enabled = 0;
}

int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
{
	return timer->irq;
}

#if defined(CONFIG_ARCH_OMAP1)

struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
{
	BUG();
}

/**
 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 * @inputmask: current value of idlect mask
 */
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{
	int i;

	/* If ARMXOR cannot be idled this function call is unnecessary */
	if (!(inputmask & (1 << 1)))
		return inputmask;

	/* If any active timer is using ARMXOR return modified mask */
	for (i = 0; i < dm_timer_count; i++) {
		u32 l;

		l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
		if (l & OMAP_TIMER_CTRL_ST) {
			if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
				inputmask &= ~(1 << 1);
			else
				inputmask &= ~(1 << 2);
		}
	}

	return inputmask;
}

#elif defined(CONFIG_ARCH_OMAP2)

struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
{
	return timer->fclk;
}

__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{
	BUG();
}

#endif

void omap_dm_timer_trigger(struct omap_dm_timer *timer)
{
	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
}

void omap_dm_timer_start(struct omap_dm_timer *timer)
{
	u32 l;

	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	if (!(l & OMAP_TIMER_CTRL_ST)) {
		l |= OMAP_TIMER_CTRL_ST;
		omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
	}
}

void omap_dm_timer_stop(struct omap_dm_timer *timer)
{
	u32 l;

	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	if (l & OMAP_TIMER_CTRL_ST) {
		l &= ~0x1;
		omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
	}
}

#ifdef CONFIG_ARCH_OMAP1

void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
{
	int n = (timer - dm_timers) << 1;
	u32 l;

	l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
	l |= source << n;
	omap_writel(l, MOD_CONF_CTRL_1);
}

#else

void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
{
	if (source < 0 || source >= 3)
		return;

	clk_disable(timer->fclk);
	clk_set_parent(timer->fclk, dm_source_clocks[source]);
	clk_enable(timer->fclk);

	/* When the functional clock disappears, too quick writes seem to
	 * cause an abort. */
	__delay(15000);
}

#endif

void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
			    unsigned int load)
{
	u32 l;

	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	if (autoreload)
		l |= OMAP_TIMER_CTRL_AR;
	else
		l &= ~OMAP_TIMER_CTRL_AR;
	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
}

void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
			     unsigned int match)
{
	u32 l;

	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	if (enable)
		l |= OMAP_TIMER_CTRL_CE;
	else
		l &= ~OMAP_TIMER_CTRL_CE;
	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
}


void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
			   int toggle, int trigger)
{
	u32 l;

	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
	       OMAP_TIMER_CTRL_PT | (0x03 << 10));
	if (def_on)
		l |= OMAP_TIMER_CTRL_SCPWM;
	if (toggle)
		l |= OMAP_TIMER_CTRL_PT;
	l |= trigger << 10;
	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}

void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
{
	u32 l;

	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
	if (prescaler >= 0x00 && prescaler <= 0x07) {
		l |= OMAP_TIMER_CTRL_PRE;
		l |= prescaler << 2;
	}
	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
}

void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
				  unsigned int value)
{
	omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
}

unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
{
	unsigned int l;

	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);

	return l;
}

void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
{
	omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
}

unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
{
	unsigned int l;

	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);

	return l;
}

void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
{
	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
}

int omap_dm_timers_active(void)
{
	int i;

	for (i = 0; i < dm_timer_count; i++) {
		struct omap_dm_timer *timer;

		timer = &dm_timers[i];

		if (!timer->enabled)
			continue;

		if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
		    OMAP_TIMER_CTRL_ST) {
			return 1;
		}
	}
	return 0;
}

int omap_dm_timer_init(void)
{
	struct omap_dm_timer *timer;
	int i;

	if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
		return -ENODEV;

	spin_lock_init(&dm_timer_lock);
#ifdef CONFIG_ARCH_OMAP2
	for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
		dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
		BUG_ON(dm_source_clocks[i] == NULL);
	}
#endif

	for (i = 0; i < dm_timer_count; i++) {
#ifdef CONFIG_ARCH_OMAP2
		char clk_name[16];
#endif

		timer = &dm_timers[i];
		timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
#ifdef CONFIG_ARCH_OMAP2
		sprintf(clk_name, "gpt%d_ick", i + 1);
		timer->iclk = clk_get(NULL, clk_name);
		sprintf(clk_name, "gpt%d_fck", i + 1);
		timer->fclk = clk_get(NULL, clk_name);
#endif
	}

	return 0;
}
Commit	Line	Data
92105bb7 TL	1	/*
	2	* linux/arch/arm/plat-omap/dmtimer.c
	3	*
	4	* OMAP Dual-Mode Timers
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
77900a2f TT	7	* OMAP2 support by Juha Yrjola
77900a2f TT	8	* API improvements and OMAP2 clock framework support by Timo Teras
92105bb7 TL	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
	15	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	16	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	17	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	18	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	19	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	20	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	21	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	22	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	23	*
	24	* You should have received a copy of the GNU General Public License along
	25	* with this program; if not, write to the Free Software Foundation, Inc.,
	26	* 675 Mass Ave, Cambridge, MA 02139, USA.
	27	*/
	28
	29	#include <linux/init.h>
77900a2f TT	30	#include <linux/spinlock.h>
	31	#include <linux/errno.h>
	32	#include <linux/list.h>
	33	#include <linux/clk.h>
	34	#include <linux/delay.h>
0a5709b2	35	#include <asm/hardware.h>
92105bb7 TL	36	#include <asm/arch/dmtimer.h>
	37	#include <asm/io.h>
	38	#include <asm/arch/irqs.h>
92105bb7	39
77900a2f	40	/* register offsets */
92105bb7 TL	41	#define OMAP_TIMER_ID_REG 0x00
	42	#define OMAP_TIMER_OCP_CFG_REG 0x10
	43	#define OMAP_TIMER_SYS_STAT_REG 0x14
	44	#define OMAP_TIMER_STAT_REG 0x18
	45	#define OMAP_TIMER_INT_EN_REG 0x1c
	46	#define OMAP_TIMER_WAKEUP_EN_REG 0x20
	47	#define OMAP_TIMER_CTRL_REG 0x24
	48	#define OMAP_TIMER_COUNTER_REG 0x28
	49	#define OMAP_TIMER_LOAD_REG 0x2c
	50	#define OMAP_TIMER_TRIGGER_REG 0x30
	51	#define OMAP_TIMER_WRITE_PEND_REG 0x34
	52	#define OMAP_TIMER_MATCH_REG 0x38
	53	#define OMAP_TIMER_CAPTURE_REG 0x3c
	54	#define OMAP_TIMER_IF_CTRL_REG 0x40
	55
77900a2f TT	56	/* timer control reg bits */
	57	#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
	58	#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
	59	#define OMAP_TIMER_CTRL_PT (1 << 12)
	60	#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
	61	#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
	62	#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
	63	#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
	64	#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
	65	#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
	66	#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */
	67	#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
	68	#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
	69
	70	struct omap_dm_timer {
	71	unsigned long phys_base;
	72	int irq;
	73	#ifdef CONFIG_ARCH_OMAP2
	74	struct clk iclk, fclk;
	75	#endif
	76	void __iomem *io_base;
	77	unsigned reserved:1;
12583a70	78	unsigned enabled:1;
77900a2f TT	79	};
	80
	81	#ifdef CONFIG_ARCH_OMAP1
	82
fa4bb626 TT	83	#define omap_dm_clk_enable(x)
	84	#define omap_dm_clk_disable(x)
	85
77900a2f TT	86	static struct omap_dm_timer dm_timers[] = {
	87	{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
	88	{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
	89	{ .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
	90	{ .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
	91	{ .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
	92	{ .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
	93	{ .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
	94	{ .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
	95	};
92105bb7	96
77900a2f	97	#elif defined(CONFIG_ARCH_OMAP2)
92105bb7	98
fa4bb626 TT	99	#define omap_dm_clk_enable(x) clk_enable(x)
	100	#define omap_dm_clk_disable(x) clk_disable(x)
	101
92105bb7	102	static struct omap_dm_timer dm_timers[] = {
77900a2f TT	103	{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
	104	{ .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
	105	{ .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
	106	{ .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
	107	{ .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
	108	{ .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
	109	{ .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
	110	{ .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
	111	{ .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
	112	{ .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
	113	{ .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
	114	{ .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
92105bb7 TL	115	};
92105bb7 TL	116
83379c81 TT	117	static const char *dm_source_names[] = {
	118	"sys_ck",
	119	"func_32k_ck",
	120	"alt_ck"
	121	};
	122
	123	static struct clk *dm_source_clocks[3];
	124
77900a2f TT	125	#else
	126
	127	#error OMAP architecture not supported!
	128
	129	#endif
	130
	131	static const int dm_timer_count = ARRAY_SIZE(dm_timers);
92105bb7 TL	132	static spinlock_t dm_timer_lock;
92105bb7 TL	133
77900a2f TT	134	static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
	135	{
	136	return readl(timer->io_base + reg);
	137	}
92105bb7	138
77900a2f	139	static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
92105bb7	140	{
77900a2f	141	writel(value, timer->io_base + reg);
92105bb7 TL	142	while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
	143	;
	144	}
	145
77900a2f	146	static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
92105bb7	147	{
77900a2f TT	148	int c;
	149
	150	c = 0;
	151	while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
	152	c++;
	153	if (c > 100000) {
	154	printk(KERN_ERR "Timer failed to reset\n");
	155	return;
	156	}
	157	}
92105bb7 TL	158	}
92105bb7 TL	159
77900a2f TT	160	static void omap_dm_timer_reset(struct omap_dm_timer *timer)
	161	{
	162	u32 l;
	163
39020842	164	if (!cpu_class_is_omap2() \|\| timer != &dm_timers[0]) {
e32f7ec2 TT	165	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
	166	omap_dm_timer_wait_for_reset(timer);
	167	}
12583a70	168	omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
77900a2f TT	169
	170	/* Set to smart-idle mode */
	171	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
	172	l \|= 0x02 << 3;
39020842 JY	173
	174	if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
	175	/* Enable wake-up only for GPT1 on OMAP2 CPUs*/
	176	l \|= 1 << 2;
	177	/* Non-posted mode */
	178	omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
	179	}
77900a2f TT	180	omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
	181	}
	182
83379c81	183	static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
77900a2f	184	{
12583a70	185	omap_dm_timer_enable(timer);
77900a2f TT	186	omap_dm_timer_reset(timer);
	187	}
	188
	189	struct omap_dm_timer *omap_dm_timer_request(void)
	190	{
	191	struct omap_dm_timer *timer = NULL;
	192	unsigned long flags;
	193	int i;
	194
	195	spin_lock_irqsave(&dm_timer_lock, flags);
	196	for (i = 0; i < dm_timer_count; i++) {
	197	if (dm_timers[i].reserved)
	198	continue;
	199
	200	timer = &dm_timers[i];
83379c81	201	timer->reserved = 1;
77900a2f TT	202	break;
	203	}
	204	spin_unlock_irqrestore(&dm_timer_lock, flags);
	205
83379c81 TT	206	if (timer != NULL)
	207	omap_dm_timer_prepare(timer);
	208
77900a2f TT	209	return timer;
	210	}
	211
	212	struct omap_dm_timer *omap_dm_timer_request_specific(int id)
92105bb7 TL	213	{
92105bb7 TL	214	struct omap_dm_timer *timer;
77900a2f	215	unsigned long flags;
92105bb7	216
77900a2f TT	217	spin_lock_irqsave(&dm_timer_lock, flags);
	218	if (id <= 0 \|\| id > dm_timer_count \|\| dm_timers[id-1].reserved) {
	219	spin_unlock_irqrestore(&dm_timer_lock, flags);
	220	printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
	221	__FILE__, __LINE__, __FUNCTION__, id);
	222	dump_stack();
	223	return NULL;
	224	}
92105bb7	225
77900a2f	226	timer = &dm_timers[id-1];
83379c81	227	timer->reserved = 1;
77900a2f TT	228	spin_unlock_irqrestore(&dm_timer_lock, flags);
77900a2f TT	229
83379c81 TT	230	omap_dm_timer_prepare(timer);
83379c81 TT	231
77900a2f	232	return timer;
92105bb7 TL	233	}
92105bb7 TL	234
77900a2f TT	235	void omap_dm_timer_free(struct omap_dm_timer *timer)
77900a2f TT	236	{
12583a70	237	omap_dm_timer_enable(timer);
77900a2f	238	omap_dm_timer_reset(timer);
12583a70	239	omap_dm_timer_disable(timer);
fa4bb626	240
77900a2f TT	241	WARN_ON(!timer->reserved);
	242	timer->reserved = 0;
	243	}
	244
12583a70 TT	245	void omap_dm_timer_enable(struct omap_dm_timer *timer)
	246	{
	247	if (timer->enabled)
	248	return;
	249
	250	omap_dm_clk_enable(timer->fclk);
	251	omap_dm_clk_enable(timer->iclk);
	252
	253	timer->enabled = 1;
	254	}
	255
	256	void omap_dm_timer_disable(struct omap_dm_timer *timer)
	257	{
	258	if (!timer->enabled)
	259	return;
	260
	261	omap_dm_clk_disable(timer->iclk);
	262	omap_dm_clk_disable(timer->fclk);
	263
	264	timer->enabled = 0;
	265	}
	266
77900a2f TT	267	int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
	268	{
	269	return timer->irq;
	270	}
	271
	272	#if defined(CONFIG_ARCH_OMAP1)
	273
	274	struct clk omap_dm_timer_get_fclk(struct omap_dm_timer timer)
	275	{
	276	BUG();
	277	}
92105bb7	278
a569c6ec TL	279	/**
	280	* omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
	281	* @inputmask: current value of idlect mask
	282	*/
	283	__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
	284	{
77900a2f	285	int i;
a569c6ec TL	286
	287	/* If ARMXOR cannot be idled this function call is unnecessary */
	288	if (!(inputmask & (1 << 1)))
	289	return inputmask;
	290
	291	/* If any active timer is using ARMXOR return modified mask */
77900a2f TT	292	for (i = 0; i < dm_timer_count; i++) {
	293	u32 l;
	294
35912c79	295	l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG);
77900a2f TT	296	if (l & OMAP_TIMER_CTRL_ST) {
77900a2f TT	297	if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
a569c6ec TL	298	inputmask &= ~(1 << 1);
	299	else
	300	inputmask &= ~(1 << 2);
	301	}
77900a2f	302	}
a569c6ec TL	303
	304	return inputmask;
	305	}
	306
77900a2f	307	#elif defined(CONFIG_ARCH_OMAP2)
a569c6ec	308
77900a2f	309	struct clk omap_dm_timer_get_fclk(struct omap_dm_timer timer)
92105bb7	310	{
fa4bb626	311	return timer->fclk;
77900a2f	312	}
92105bb7	313
77900a2f TT	314	__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
	315	{
	316	BUG();
92105bb7 TL	317	}
92105bb7 TL	318
77900a2f	319	#endif
92105bb7	320
77900a2f	321	void omap_dm_timer_trigger(struct omap_dm_timer *timer)
92105bb7	322	{
77900a2f	323	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
92105bb7 TL	324	}
92105bb7 TL	325
77900a2f TT	326	void omap_dm_timer_start(struct omap_dm_timer *timer)
	327	{
	328	u32 l;
92105bb7	329
77900a2f TT	330	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	331	if (!(l & OMAP_TIMER_CTRL_ST)) {
	332	l \|= OMAP_TIMER_CTRL_ST;
	333	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
	334	}
	335	}
92105bb7	336
77900a2f	337	void omap_dm_timer_stop(struct omap_dm_timer *timer)
92105bb7	338	{
77900a2f	339	u32 l;
92105bb7	340
77900a2f TT	341	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
	342	if (l & OMAP_TIMER_CTRL_ST) {
	343	l &= ~0x1;
	344	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
92105bb7	345	}
92105bb7 TL	346	}
92105bb7 TL	347
77900a2f	348	#ifdef CONFIG_ARCH_OMAP1
92105bb7	349
77900a2f	350	void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
92105bb7	351	{
77900a2f TT	352	int n = (timer - dm_timers) << 1;
77900a2f TT	353	u32 l;
92105bb7	354
77900a2f TT	355	l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
	356	l \|= source << n;
	357	omap_writel(l, MOD_CONF_CTRL_1);
92105bb7 TL	358	}
92105bb7 TL	359
77900a2f	360	#else
92105bb7	361
77900a2f	362	void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
92105bb7	363	{
77900a2f TT	364	if (source < 0 \|\| source >= 3)
	365	return;
	366
77900a2f	367	clk_disable(timer->fclk);
83379c81	368	clk_set_parent(timer->fclk, dm_source_clocks[source]);
77900a2f	369	clk_enable(timer->fclk);
77900a2f TT	370
	371	/* When the functional clock disappears, too quick writes seem to
	372	* cause an abort. */
e32f7ec2	373	__delay(15000);
92105bb7 TL	374	}
92105bb7 TL	375
77900a2f	376	#endif
92105bb7	377
77900a2f TT	378	void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
77900a2f TT	379	unsigned int load)
92105bb7 TL	380	{
92105bb7 TL	381	u32 l;
77900a2f	382
92105bb7	383	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
77900a2f TT	384	if (autoreload)
	385	l \|= OMAP_TIMER_CTRL_AR;
	386	else
	387	l &= ~OMAP_TIMER_CTRL_AR;
92105bb7	388	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
77900a2f TT	389	omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
77900a2f TT	390	omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
92105bb7 TL	391	}
92105bb7 TL	392
77900a2f TT	393	void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
77900a2f TT	394	unsigned int match)
92105bb7 TL	395	{
	396	u32 l;
	397
	398	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
83379c81	399	if (enable)
77900a2f TT	400	l \|= OMAP_TIMER_CTRL_CE;
	401	else
	402	l &= ~OMAP_TIMER_CTRL_CE;
92105bb7	403	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
77900a2f	404	omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
92105bb7 TL	405	}
92105bb7 TL	406
77900a2f TT	407
	408	void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
	409	int toggle, int trigger)
92105bb7 TL	410	{
	411	u32 l;
	412
	413	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
77900a2f TT	414	l &= ~(OMAP_TIMER_CTRL_GPOCFG \| OMAP_TIMER_CTRL_SCPWM \|
	415	OMAP_TIMER_CTRL_PT \| (0x03 << 10));
	416	if (def_on)
	417	l \|= OMAP_TIMER_CTRL_SCPWM;
	418	if (toggle)
	419	l \|= OMAP_TIMER_CTRL_PT;
	420	l \|= trigger << 10;
92105bb7 TL	421	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
	422	}
	423
77900a2f	424	void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
92105bb7 TL	425	{
	426	u32 l;
	427
	428	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
77900a2f TT	429	l &= ~(OMAP_TIMER_CTRL_PRE \| (0x07 << 2));
	430	if (prescaler >= 0x00 && prescaler <= 0x07) {
	431	l \|= OMAP_TIMER_CTRL_PRE;
	432	l \|= prescaler << 2;
	433	}
92105bb7 TL	434	omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
	435	}
	436
77900a2f TT	437	void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
77900a2f TT	438	unsigned int value)
92105bb7	439	{
77900a2f	440	omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
39020842	441	omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
92105bb7 TL	442	}
92105bb7 TL	443
77900a2f	444	unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
92105bb7	445	{
fa4bb626 TT	446	unsigned int l;
fa4bb626 TT	447
fa4bb626	448	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
fa4bb626 TT	449
fa4bb626 TT	450	return l;
92105bb7 TL	451	}
92105bb7 TL	452
77900a2f	453	void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
92105bb7	454	{
77900a2f	455	omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
92105bb7 TL	456	}
92105bb7 TL	457
77900a2f	458	unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
92105bb7	459	{
fa4bb626 TT	460	unsigned int l;
fa4bb626 TT	461
fa4bb626	462	l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
fa4bb626 TT	463
fa4bb626 TT	464	return l;
92105bb7 TL	465	}
92105bb7 TL	466
83379c81 TT	467	void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
83379c81 TT	468	{
fa4bb626	469	omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
83379c81 TT	470	}
83379c81 TT	471
77900a2f	472	int omap_dm_timers_active(void)
92105bb7	473	{
77900a2f	474	int i;
92105bb7	475
77900a2f TT	476	for (i = 0; i < dm_timer_count; i++) {
77900a2f TT	477	struct omap_dm_timer *timer;
92105bb7	478
77900a2f	479	timer = &dm_timers[i];
12583a70 TT	480
	481	if (!timer->enabled)
	482	continue;
	483
77900a2f	484	if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
fa4bb626	485	OMAP_TIMER_CTRL_ST) {
77900a2f	486	return 1;
fa4bb626	487	}
77900a2f TT	488	}
	489	return 0;
	490	}
92105bb7	491
77900a2f	492	int omap_dm_timer_init(void)
92105bb7 TL	493	{
92105bb7 TL	494	struct omap_dm_timer *timer;
77900a2f TT	495	int i;
	496
	497	if (!(cpu_is_omap16xx() \|\| cpu_is_omap24xx()))
	498	return -ENODEV;
92105bb7 TL	499
92105bb7 TL	500	spin_lock_init(&dm_timer_lock);
83379c81 TT	501	#ifdef CONFIG_ARCH_OMAP2
	502	for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
	503	dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
	504	BUG_ON(dm_source_clocks[i] == NULL);
	505	}
	506	#endif
	507
77900a2f TT	508	for (i = 0; i < dm_timer_count; i++) {
	509	#ifdef CONFIG_ARCH_OMAP2
	510	char clk_name[16];
	511	#endif
	512
	513	timer = &dm_timers[i];
	514	timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
	515	#ifdef CONFIG_ARCH_OMAP2
	516	sprintf(clk_name, "gpt%d_ick", i + 1);
	517	timer->iclk = clk_get(NULL, clk_name);
	518	sprintf(clk_name, "gpt%d_fck", i + 1);
	519	timer->fclk = clk_get(NULL, clk_name);
	520	#endif
92105bb7	521	}
92105bb7	522
92105bb7 TL	523	return 0;
92105bb7 TL	524	}