[linux.git] / arch / x86 / pci / i386.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	Low-Level PCI Access for i386 machines
 *
 * Copyright 1993, 1994 Drew Eckhardt
 *      Visionary Computing
 *      (Unix and Linux consulting and custom programming)
 *      [email protected]
 *      +1 (303) 786-7975
 *
 * Drew's work was sponsored by:
 *	iX Multiuser Multitasking Magazine
 *	Hannover, Germany
 *	[email protected]
 *
 * Copyright 1997--2000 Martin Mares <[email protected]>
 *
 * For more information, please consult the following manuals (look at
 * http://www.pcisig.com/ for how to get them):
 *
 * PCI BIOS Specification
 * PCI Local Bus Specification
 * PCI to PCI Bridge Specification
 * PCI System Design Guide
 *
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/bootmem.h>

#include <asm/pat.h>
#include <asm/e820/api.h>
#include <asm/pci_x86.h>
#include <asm/io_apic.h>


/*
 * This list of dynamic mappings is for temporarily maintaining
 * original BIOS BAR addresses for possible reinstatement.
 */
struct pcibios_fwaddrmap {
	struct list_head list;
	struct pci_dev *dev;
	resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
};

static LIST_HEAD(pcibios_fwaddrmappings);
static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
static bool pcibios_fw_addr_done;

/* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
{
	struct pcibios_fwaddrmap *map;

	WARN_ON_SMP(!spin_is_locked(&pcibios_fwaddrmap_lock));

	list_for_each_entry(map, &pcibios_fwaddrmappings, list)
		if (map->dev == dev)
			return map;

	return NULL;
}

static void
pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
{
	unsigned long flags;
	struct pcibios_fwaddrmap *map;

	if (pcibios_fw_addr_done)
		return;

	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	map = pcibios_fwaddrmap_lookup(dev);
	if (!map) {
		spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
		map = kzalloc(sizeof(*map), GFP_KERNEL);
		if (!map)
			return;

		map->dev = pci_dev_get(dev);
		map->fw_addr[idx] = fw_addr;
		INIT_LIST_HEAD(&map->list);

		spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
		list_add_tail(&map->list, &pcibios_fwaddrmappings);
	} else
		map->fw_addr[idx] = fw_addr;
	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
}

resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	unsigned long flags;
	struct pcibios_fwaddrmap *map;
	resource_size_t fw_addr = 0;

	if (pcibios_fw_addr_done)
		return 0;

	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	map = pcibios_fwaddrmap_lookup(dev);
	if (map)
		fw_addr = map->fw_addr[idx];
	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);

	return fw_addr;
}

static void __init pcibios_fw_addr_list_del(void)
{
	unsigned long flags;
	struct pcibios_fwaddrmap *entry, *next;

	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
		list_del(&entry->list);
		pci_dev_put(entry->dev);
		kfree(entry);
	}
	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
	pcibios_fw_addr_done = true;
}

static int
skip_isa_ioresource_align(struct pci_dev *dev) {

	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
	    !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
		return 1;
	return 0;
}

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
			resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		if (skip_isa_ioresource_align(dev))
			return start;
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	} else if (res->flags & IORESOURCE_MEM) {
		/* The low 1MB range is reserved for ISA cards */
		if (start < BIOS_END)
			start = BIOS_END;
	}
	return start;
}
EXPORT_SYMBOL(pcibios_align_resource);

/*
 *  Handle resources of PCI devices.  If the world were perfect, we could
 *  just allocate all the resource regions and do nothing more.  It isn't.
 *  On the other hand, we cannot just re-allocate all devices, as it would
 *  require us to know lots of host bridge internals.  So we attempt to
 *  keep as much of the original configuration as possible, but tweak it
 *  when it's found to be wrong.
 *
 *  Known BIOS problems we have to work around:
 *	- I/O or memory regions not configured
 *	- regions configured, but not enabled in the command register
 *	- bogus I/O addresses above 64K used
 *	- expansion ROMs left enabled (this may sound harmless, but given
 *	  the fact the PCI specs explicitly allow address decoders to be
 *	  shared between expansion ROMs and other resource regions, it's
 *	  at least dangerous)
 *	- bad resource sizes or overlaps with other regions
 *
 *  Our solution:
 *	(1) Allocate resources for all buses behind PCI-to-PCI bridges.
 *	    This gives us fixed barriers on where we can allocate.
 *	(2) Allocate resources for all enabled devices.  If there is
 *	    a collision, just mark the resource as unallocated. Also
 *	    disable expansion ROMs during this step.
 *	(3) Try to allocate resources for disabled devices.  If the
 *	    resources were assigned correctly, everything goes well,
 *	    if they weren't, they won't disturb allocation of other
 *	    resources.
 *	(4) Assign new addresses to resources which were either
 *	    not configured at all or misconfigured.  If explicitly
 *	    requested by the user, configure expansion ROM address
 *	    as well.
 */

static void pcibios_allocate_bridge_resources(struct pci_dev *dev)
{
	int idx;
	struct resource *r;

	for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
		r = &dev->resource[idx];
		if (!r->flags)
			continue;
		if (r->parent)	/* Already allocated */
			continue;
		if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) {
			/*
			 * Something is wrong with the region.
			 * Invalidate the resource to prevent
			 * child resource allocations in this
			 * range.
			 */
			r->start = r->end = 0;
			r->flags = 0;
		}
	}
}

static void pcibios_allocate_bus_resources(struct pci_bus *bus)
{
	struct pci_bus *child;

	/* Depth-First Search on bus tree */
	if (bus->self)
		pcibios_allocate_bridge_resources(bus->self);
	list_for_each_entry(child, &bus->children, node)
		pcibios_allocate_bus_resources(child);
}

struct pci_check_idx_range {
	int start;
	int end;
};

static void pcibios_allocate_dev_resources(struct pci_dev *dev, int pass)
{
	int idx, disabled, i;
	u16 command;
	struct resource *r;

	struct pci_check_idx_range idx_range[] = {
		{ PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
#ifdef CONFIG_PCI_IOV
		{ PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
#endif
	};

	pci_read_config_word(dev, PCI_COMMAND, &command);
	for (i = 0; i < ARRAY_SIZE(idx_range); i++)
		for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
			r = &dev->resource[idx];
			if (r->parent)	/* Already allocated */
				continue;
			if (!r->start)	/* Address not assigned at all */
				continue;
			if (r->flags & IORESOURCE_IO)
				disabled = !(command & PCI_COMMAND_IO);
			else
				disabled = !(command & PCI_COMMAND_MEMORY);
			if (pass == disabled) {
				dev_dbg(&dev->dev,
					"BAR %d: reserving %pr (d=%d, p=%d)\n",
					idx, r, disabled, pass);
				if (pci_claim_resource(dev, idx) < 0) {
					if (r->flags & IORESOURCE_PCI_FIXED) {
						dev_info(&dev->dev, "BAR %d %pR is immovable\n",
							 idx, r);
					} else {
						/* We'll assign a new address later */
						pcibios_save_fw_addr(dev,
								idx, r->start);
						r->end -= r->start;
						r->start = 0;
					}
				}
			}
		}
	if (!pass) {
		r = &dev->resource[PCI_ROM_RESOURCE];
		if (r->flags & IORESOURCE_ROM_ENABLE) {
			/* Turn the ROM off, leave the resource region,
			 * but keep it unregistered. */
			u32 reg;
			dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
			r->flags &= ~IORESOURCE_ROM_ENABLE;
			pci_read_config_dword(dev, dev->rom_base_reg, &reg);
			pci_write_config_dword(dev, dev->rom_base_reg,
						reg & ~PCI_ROM_ADDRESS_ENABLE);
		}
	}
}

static void pcibios_allocate_resources(struct pci_bus *bus, int pass)
{
	struct pci_dev *dev;
	struct pci_bus *child;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		pcibios_allocate_dev_resources(dev, pass);

		child = dev->subordinate;
		if (child)
			pcibios_allocate_resources(child, pass);
	}
}

static void pcibios_allocate_dev_rom_resource(struct pci_dev *dev)
{
	struct resource *r;

	/*
	 * Try to use BIOS settings for ROMs, otherwise let
	 * pci_assign_unassigned_resources() allocate the new
	 * addresses.
	 */
	r = &dev->resource[PCI_ROM_RESOURCE];
	if (!r->flags || !r->start)
		return;
	if (r->parent) /* Already allocated */
		return;

	if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
		r->end -= r->start;
		r->start = 0;
	}
}
static void pcibios_allocate_rom_resources(struct pci_bus *bus)
{
	struct pci_dev *dev;
	struct pci_bus *child;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		pcibios_allocate_dev_rom_resource(dev);

		child = dev->subordinate;
		if (child)
			pcibios_allocate_rom_resources(child);
	}
}

static int __init pcibios_assign_resources(void)
{
	struct pci_bus *bus;

	if (!(pci_probe & PCI_ASSIGN_ROMS))
		list_for_each_entry(bus, &pci_root_buses, node)
			pcibios_allocate_rom_resources(bus);

	pci_assign_unassigned_resources();
	pcibios_fw_addr_list_del();

	return 0;
}

/**
 * called in fs_initcall (one below subsys_initcall),
 * give a chance for motherboard reserve resources
 */
fs_initcall(pcibios_assign_resources);

void pcibios_resource_survey_bus(struct pci_bus *bus)
{
	dev_printk(KERN_DEBUG, &bus->dev, "Allocating resources\n");

	pcibios_allocate_bus_resources(bus);

	pcibios_allocate_resources(bus, 0);
	pcibios_allocate_resources(bus, 1);

	if (!(pci_probe & PCI_ASSIGN_ROMS))
		pcibios_allocate_rom_resources(bus);
}

void __init pcibios_resource_survey(void)
{
	struct pci_bus *bus;

	DBG("PCI: Allocating resources\n");

	list_for_each_entry(bus, &pci_root_buses, node)
		pcibios_allocate_bus_resources(bus);

	list_for_each_entry(bus, &pci_root_buses, node)
		pcibios_allocate_resources(bus, 0);
	list_for_each_entry(bus, &pci_root_buses, node)
		pcibios_allocate_resources(bus, 1);

	e820__reserve_resources_late();
	/*
	 * Insert the IO APIC resources after PCI initialization has
	 * occurred to handle IO APICS that are mapped in on a BAR in
	 * PCI space, but before trying to assign unassigned pci res.
	 */
	ioapic_insert_resources();
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* Low-Level PCI Access for i386 machines
	4	*
	5	* Copyright 1993, 1994 Drew Eckhardt
	6	* Visionary Computing
	7	* (Unix and Linux consulting and custom programming)
	8	* [email protected]
	9	* +1 (303) 786-7975
	10	*
	11	* Drew's work was sponsored by:
	12	* iX Multiuser Multitasking Magazine
	13	* Hannover, Germany
	14	* [email protected]
	15	*
	16	* Copyright 1997--2000 Martin Mares <[email protected]>
	17	*
	18	* For more information, please consult the following manuals (look at
	19	* http://www.pcisig.com/ for how to get them):
	20	*
	21	* PCI BIOS Specification
	22	* PCI Local Bus Specification
	23	* PCI to PCI Bridge Specification
	24	* PCI System Design Guide
	25	*
	26	*/
	27
	28	#include <linux/types.h>
	29	#include <linux/kernel.h>
69c60c88	30	#include <linux/export.h>
1da177e4 LT	31	#include <linux/pci.h>
	32	#include <linux/init.h>
	33	#include <linux/ioport.h>
	34	#include <linux/errno.h>
03d72aa1	35	#include <linux/bootmem.h>
	36
	37	#include <asm/pat.h>
66441bd3	38	#include <asm/e820/api.h>
82487711	39	#include <asm/pci_x86.h>
857fdc53	40	#include <asm/io_apic.h>
1da177e4	41
1da177e4	42
925845bd MS	43	/*
	44	* This list of dynamic mappings is for temporarily maintaining
	45	* original BIOS BAR addresses for possible reinstatement.
	46	*/
	47	struct pcibios_fwaddrmap {
	48	struct list_head list;
	49	struct pci_dev *dev;
	50	resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
	51	};
	52
	53	static LIST_HEAD(pcibios_fwaddrmappings);
	54	static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
74521602	55	static bool pcibios_fw_addr_done;
925845bd MS	56
	57	/* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
	58	static struct pcibios_fwaddrmap pcibios_fwaddrmap_lookup(struct pci_dev dev)
	59	{
	60	struct pcibios_fwaddrmap *map;
	61
867aae6e	62	WARN_ON_SMP(!spin_is_locked(&pcibios_fwaddrmap_lock));
63ab387c	63
925845bd MS	64	list_for_each_entry(map, &pcibios_fwaddrmappings, list)
	65	if (map->dev == dev)
	66	return map;
	67
	68	return NULL;
	69	}
	70
	71	static void
	72	pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
	73	{
	74	unsigned long flags;
	75	struct pcibios_fwaddrmap *map;
	76
74521602 YL	77	if (pcibios_fw_addr_done)
	78	return;
	79
925845bd MS	80	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	81	map = pcibios_fwaddrmap_lookup(dev);
	82	if (!map) {
	83	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
	84	map = kzalloc(sizeof(*map), GFP_KERNEL);
	85	if (!map)
	86	return;
	87
	88	map->dev = pci_dev_get(dev);
	89	map->fw_addr[idx] = fw_addr;
	90	INIT_LIST_HEAD(&map->list);
	91
	92	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	93	list_add_tail(&map->list, &pcibios_fwaddrmappings);
	94	} else
	95	map->fw_addr[idx] = fw_addr;
	96	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
	97	}
	98
	99	resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	100	{
	101	unsigned long flags;
	102	struct pcibios_fwaddrmap *map;
	103	resource_size_t fw_addr = 0;
	104
74521602 YL	105	if (pcibios_fw_addr_done)
	106	return 0;
	107
925845bd MS	108	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	109	map = pcibios_fwaddrmap_lookup(dev);
	110	if (map)
	111	fw_addr = map->fw_addr[idx];
	112	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
	113
	114	return fw_addr;
	115	}
	116
74521602	117	static void __init pcibios_fw_addr_list_del(void)
925845bd MS	118	{
	119	unsigned long flags;
	120	struct pcibios_fwaddrmap entry, next;
	121
	122	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	123	list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
	124	list_del(&entry->list);
	125	pci_dev_put(entry->dev);
	126	kfree(entry);
	127	}
	128	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
74521602	129	pcibios_fw_addr_done = true;
925845bd MS	130	}
925845bd MS	131
036fff4c GH	132	static int
	133	skip_isa_ioresource_align(struct pci_dev *dev) {
	134
	135	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
11949255	136	!(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
036fff4c GH	137	return 1;
	138	return 0;
	139	}
	140
1da177e4 LT	141	/*
	142	* We need to avoid collisions with `mirrored' VGA ports
	143	* and other strange ISA hardware, so we always want the
	144	* addresses to be allocated in the 0x000-0x0ff region
	145	* modulo 0x400.
	146	*
	147	* Why? Because some silly external IO cards only decode
	148	* the low 10 bits of the IO address. The 0x00-0xff region
	149	* is reserved for motherboard devices that decode all 16
	150	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	151	* but we want to try to avoid allocating at 0x2900-0x2bff
	152	* which might have be mirrored at 0x0100-0x03ff..
	153	*/
b26b2d49	154	resource_size_t
3b7a17fc	155	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	156	resource_size_t size, resource_size_t align)
1da177e4	157	{
036fff4c	158	struct pci_dev *dev = data;
d14125ec	159	resource_size_t start = res->start;
036fff4c	160
1da177e4	161	if (res->flags & IORESOURCE_IO) {
d14125ec BH	162	if (skip_isa_ioresource_align(dev))
	163	return start;
	164	if (start & 0x300)
	165	start = (start + 0x3ff) & ~0x3ff;
cbace46a CS	166	} else if (res->flags & IORESOURCE_MEM) {
	167	/* The low 1MB range is reserved for ISA cards */
	168	if (start < BIOS_END)
	169	start = BIOS_END;
1da177e4	170	}
b26b2d49	171	return start;
1da177e4	172	}
6c00a61e	173	EXPORT_SYMBOL(pcibios_align_resource);
1da177e4 LT	174
	175	/*
	176	* Handle resources of PCI devices. If the world were perfect, we could
	177	* just allocate all the resource regions and do nothing more. It isn't.
	178	* On the other hand, we cannot just re-allocate all devices, as it would
	179	* require us to know lots of host bridge internals. So we attempt to
	180	* keep as much of the original configuration as possible, but tweak it
	181	* when it's found to be wrong.
	182	*
	183	* Known BIOS problems we have to work around:
	184	* - I/O or memory regions not configured
	185	* - regions configured, but not enabled in the command register
	186	* - bogus I/O addresses above 64K used
	187	* - expansion ROMs left enabled (this may sound harmless, but given
	188	* the fact the PCI specs explicitly allow address decoders to be
	189	* shared between expansion ROMs and other resource regions, it's
	190	* at least dangerous)
837c4ef1	191	* - bad resource sizes or overlaps with other regions
1da177e4 LT	192	*
	193	* Our solution:
	194	* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
	195	* This gives us fixed barriers on where we can allocate.
	196	* (2) Allocate resources for all enabled devices. If there is
	197	* a collision, just mark the resource as unallocated. Also
	198	* disable expansion ROMs during this step.
	199	* (3) Try to allocate resources for disabled devices. If the
	200	* resources were assigned correctly, everything goes well,
	201	* if they weren't, they won't disturb allocation of other
	202	* resources.
	203	* (4) Assign new addresses to resources which were either
	204	* not configured at all or misconfigured. If explicitly
	205	* requested by the user, configure expansion ROM address
	206	* as well.
	207	*/
	208
b95168e0	209	static void pcibios_allocate_bridge_resources(struct pci_dev *dev)
1da177e4	210	{
1da177e4	211	int idx;
a76117df	212	struct resource *r;
1da177e4	213
f7ac356d YL	214	for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
	215	r = &dev->resource[idx];
	216	if (!r->flags)
	217	continue;
c70d6505 MW	218	if (r->parent) /* Already allocated */
c70d6505 MW	219	continue;
851b0936	220	if (!r->start \|\| pci_claim_bridge_resource(dev, idx) < 0) {
f7ac356d YL	221	/*
	222	* Something is wrong with the region.
	223	* Invalidate the resource to prevent
	224	* child resource allocations in this
	225	* range.
	226	*/
	227	r->start = r->end = 0;
	228	r->flags = 0;
	229	}
	230	}
	231	}
	232
b95168e0	233	static void pcibios_allocate_bus_resources(struct pci_bus *bus)
f7ac356d	234	{
83edc87c	235	struct pci_bus *child;
f7ac356d	236
1da177e4	237	/* Depth-First Search on bus tree */
83edc87c YL	238	if (bus->self)
	239	pcibios_allocate_bridge_resources(bus->self);
	240	list_for_each_entry(child, &bus->children, node)
	241	pcibios_allocate_bus_resources(child);
1da177e4 LT	242	}
1da177e4 LT	243
575939cf YL	244	struct pci_check_idx_range {
	245	int start;
	246	int end;
	247	};
	248
b95168e0	249	static void pcibios_allocate_dev_resources(struct pci_dev *dev, int pass)
1da177e4	250	{
575939cf	251	int idx, disabled, i;
1da177e4	252	u16 command;
a76117df	253	struct resource *r;
1da177e4	254
575939cf YL	255	struct pci_check_idx_range idx_range[] = {
	256	{ PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
	257	#ifdef CONFIG_PCI_IOV
	258	{ PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
	259	#endif
	260	};
	261
c7f4bbc9 YL	262	pci_read_config_word(dev, PCI_COMMAND, &command);
c7f4bbc9 YL	263	for (i = 0; i < ARRAY_SIZE(idx_range); i++)
575939cf	264	for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
1da177e4	265	r = &dev->resource[idx];
c7f4bbc9	266	if (r->parent) /* Already allocated */
1da177e4	267	continue;
c7f4bbc9	268	if (!r->start) /* Address not assigned at all */
1da177e4 LT	269	continue;
	270	if (r->flags & IORESOURCE_IO)
	271	disabled = !(command & PCI_COMMAND_IO);
	272	else
	273	disabled = !(command & PCI_COMMAND_MEMORY);
	274	if (pass == disabled) {
c7dabef8	275	dev_dbg(&dev->dev,
865df576	276	"BAR %d: reserving %pr (d=%d, p=%d)\n",
c7dabef8	277	idx, r, disabled, pass);
a76117df	278	if (pci_claim_resource(dev, idx) < 0) {
4e4ba944 BH	279	if (r->flags & IORESOURCE_PCI_FIXED) {
	280	dev_info(&dev->dev, "BAR %d %pR is immovable\n",
	281	idx, r);
	282	} else {
	283	/* We'll assign a new address later */
	284	pcibios_save_fw_addr(dev,
	285	idx, r->start);
	286	r->end -= r->start;
	287	r->start = 0;
	288	}
1da177e4 LT	289	}
	290	}
	291	}
c7f4bbc9 YL	292	if (!pass) {
	293	r = &dev->resource[PCI_ROM_RESOURCE];
	294	if (r->flags & IORESOURCE_ROM_ENABLE) {
	295	/* Turn the ROM off, leave the resource region,
	296	* but keep it unregistered. */
	297	u32 reg;
	298	dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
	299	r->flags &= ~IORESOURCE_ROM_ENABLE;
	300	pci_read_config_dword(dev, dev->rom_base_reg, &reg);
	301	pci_write_config_dword(dev, dev->rom_base_reg,
7edab2f0	302	reg & ~PCI_ROM_ADDRESS_ENABLE);
1da177e4 LT	303	}
	304	}
	305	}
	306
b95168e0	307	static void pcibios_allocate_resources(struct pci_bus *bus, int pass)
c7f4bbc9	308	{
83edc87c YL	309	struct pci_dev *dev;
83edc87c YL	310	struct pci_bus *child;
c7f4bbc9	311
83edc87c	312	list_for_each_entry(dev, &bus->devices, bus_list) {
c7f4bbc9	313	pcibios_allocate_dev_resources(dev, pass);
83edc87c YL	314
	315	child = dev->subordinate;
	316	if (child)
	317	pcibios_allocate_resources(child, pass);
	318	}
c7f4bbc9 YL	319	}
c7f4bbc9 YL	320
b95168e0	321	static void pcibios_allocate_dev_rom_resource(struct pci_dev *dev)
1da177e4	322	{
a76117df	323	struct resource *r;
1da177e4	324
dc2f56fa YL	325	/*
	326	* Try to use BIOS settings for ROMs, otherwise let
	327	* pci_assign_unassigned_resources() allocate the new
	328	* addresses.
	329	*/
	330	r = &dev->resource[PCI_ROM_RESOURCE];
	331	if (!r->flags \|\| !r->start)
	332	return;
c70d6505 MW	333	if (r->parent) /* Already allocated */
c70d6505 MW	334	return;
dc2f56fa YL	335
	336	if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
	337	r->end -= r->start;
	338	r->start = 0;
1da177e4	339	}
dc2f56fa	340	}
b95168e0	341	static void pcibios_allocate_rom_resources(struct pci_bus *bus)
dc2f56fa YL	342	{
	343	struct pci_dev *dev;
	344	struct pci_bus *child;
	345
	346	list_for_each_entry(dev, &bus->devices, bus_list) {
	347	pcibios_allocate_dev_rom_resource(dev);
	348
	349	child = dev->subordinate;
	350	if (child)
	351	pcibios_allocate_rom_resources(child);
	352	}
	353	}
	354
	355	static int __init pcibios_assign_resources(void)
	356	{
	357	struct pci_bus *bus;
	358
	359	if (!(pci_probe & PCI_ASSIGN_ROMS))
	360	list_for_each_entry(bus, &pci_root_buses, node)
	361	pcibios_allocate_rom_resources(bus);
81d4af13 IK	362
81d4af13 IK	363	pci_assign_unassigned_resources();
6535943f	364	pcibios_fw_addr_list_del();
81d4af13	365
1da177e4 LT	366	return 0;
	367	}
	368
adc429d6 BH	369	/**
	370	* called in fs_initcall (one below subsys_initcall),
	371	* give a chance for motherboard reserve resources
	372	*/
	373	fs_initcall(pcibios_assign_resources);
	374
b3e65e1f YL	375	void pcibios_resource_survey_bus(struct pci_bus *bus)
	376	{
	377	dev_printk(KERN_DEBUG, &bus->dev, "Allocating resources\n");
	378
	379	pcibios_allocate_bus_resources(bus);
	380
	381	pcibios_allocate_resources(bus, 0);
	382	pcibios_allocate_resources(bus, 1);
	383
	384	if (!(pci_probe & PCI_ASSIGN_ROMS))
	385	pcibios_allocate_rom_resources(bus);
	386	}
	387
1da177e4 LT	388	void __init pcibios_resource_survey(void)
1da177e4 LT	389	{
83edc87c YL	390	struct pci_bus *bus;
83edc87c YL	391
1da177e4	392	DBG("PCI: Allocating resources\n");
83edc87c YL	393
	394	list_for_each_entry(bus, &pci_root_buses, node)
	395	pcibios_allocate_bus_resources(bus);
	396
	397	list_for_each_entry(bus, &pci_root_buses, node)
	398	pcibios_allocate_resources(bus, 0);
	399	list_for_each_entry(bus, &pci_root_buses, node)
	400	pcibios_allocate_resources(bus, 1);
a5444d15	401
1506c8dc	402	e820__reserve_resources_late();
857fdc53 YL	403	/*
857fdc53 YL	404	* Insert the IO APIC resources after PCI initialization has
0d2eb44f	405	* occurred to handle IO APICS that are mapped in on a BAR in
857fdc53 YL	406	* PCI space, but before trying to assign unassigned pci res.
	407	*/
	408	ioapic_insert_resources();
1da177e4	409	}