[linux.git] / arch / x86 / kernel / amd_iommu_init.c

/*
 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
 * Author: Joerg Roedel <[email protected]>
 *         Leo Duran <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/gfp.h>
#include <linux/list.h>
#include <asm/pci-direct.h>
#include <asm/amd_iommu_types.h>
#include <asm/gart.h>

/*
 * definitions for the ACPI scanning code
 */
#define UPDATE_LAST_BDF(x) do {\
	if ((x) > amd_iommu_last_bdf) \
		amd_iommu_last_bdf = (x); \
	} while (0);

#define DEVID(bus, devfn) (((bus) << 8) | (devfn))
#define PCI_BUS(x) (((x) >> 8) & 0xff)
#define IVRS_HEADER_LENGTH 48
#define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))

#define ACPI_IVHD_TYPE                  0x10
#define ACPI_IVMD_TYPE_ALL              0x20
#define ACPI_IVMD_TYPE                  0x21
#define ACPI_IVMD_TYPE_RANGE            0x22

#define IVHD_DEV_ALL                    0x01
#define IVHD_DEV_SELECT                 0x02
#define IVHD_DEV_SELECT_RANGE_START     0x03
#define IVHD_DEV_RANGE_END              0x04
#define IVHD_DEV_ALIAS                  0x42
#define IVHD_DEV_ALIAS_RANGE            0x43
#define IVHD_DEV_EXT_SELECT             0x46
#define IVHD_DEV_EXT_SELECT_RANGE       0x47

#define IVHD_FLAG_HT_TUN_EN             0x00
#define IVHD_FLAG_PASSPW_EN             0x01
#define IVHD_FLAG_RESPASSPW_EN          0x02
#define IVHD_FLAG_ISOC_EN               0x03

#define IVMD_FLAG_EXCL_RANGE            0x08
#define IVMD_FLAG_UNITY_MAP             0x01

#define ACPI_DEVFLAG_INITPASS           0x01
#define ACPI_DEVFLAG_EXTINT             0x02
#define ACPI_DEVFLAG_NMI                0x04
#define ACPI_DEVFLAG_SYSMGT1            0x10
#define ACPI_DEVFLAG_SYSMGT2            0x20
#define ACPI_DEVFLAG_LINT0              0x40
#define ACPI_DEVFLAG_LINT1              0x80
#define ACPI_DEVFLAG_ATSDIS             0x10000000

struct ivhd_header {
	u8 type;
	u8 flags;
	u16 length;
	u16 devid;
	u16 cap_ptr;
	u64 mmio_phys;
	u16 pci_seg;
	u16 info;
	u32 reserved;
} __attribute__((packed));

struct ivhd_entry {
	u8 type;
	u16 devid;
	u8 flags;
	u32 ext;
} __attribute__((packed));

struct ivmd_header {
	u8 type;
	u8 flags;
	u16 length;
	u16 devid;
	u16 aux;
	u64 resv;
	u64 range_start;
	u64 range_length;
} __attribute__((packed));

static int __initdata amd_iommu_disable;

u16 amd_iommu_last_bdf;
struct list_head amd_iommu_unity_map;
unsigned amd_iommu_aperture_order = 26;
int amd_iommu_isolate;

struct list_head amd_iommu_list;
struct dev_table_entry *amd_iommu_dev_table;
u16 *amd_iommu_alias_table;
struct amd_iommu **amd_iommu_rlookup_table;
struct protection_domain **amd_iommu_pd_table;
unsigned long *amd_iommu_pd_alloc_bitmap;

static u32 dev_table_size;
static u32 alias_table_size;
static u32 rlookup_table_size;

static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
{
	u64 start = iommu->exclusion_start & PAGE_MASK;
	u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
	u64 entry;

	if (!iommu->exclusion_start)
		return;

	entry = start | MMIO_EXCL_ENABLE_MASK;
	memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
			&entry, sizeof(entry));

	entry = limit;
	memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
			&entry, sizeof(entry));
}

static void __init iommu_set_device_table(struct amd_iommu *iommu)
{
	u32 entry;

	BUG_ON(iommu->mmio_base == NULL);

	entry = virt_to_phys(amd_iommu_dev_table);
	entry |= (dev_table_size >> 12) - 1;
	memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
			&entry, sizeof(entry));
}

static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
{
	u32 ctrl;

	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	ctrl |= (1 << bit);
	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
}

static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
{
	u32 ctrl;

	ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	ctrl &= ~(1 << bit);
	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
}

void __init iommu_enable(struct amd_iommu *iommu)
{
	u32 ctrl;

	printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
	print_devid(iommu->devid, 0);
	printk(" cap 0x%hx\n", iommu->cap_ptr);

	iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
}

static u8 * __init iommu_map_mmio_space(u64 address)
{
	u8 *ret;

	if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
		return NULL;

	ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
	if (ret != NULL)
		return ret;

	release_mem_region(address, MMIO_REGION_LENGTH);

	return NULL;
}

static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
{
	if (iommu->mmio_base)
		iounmap(iommu->mmio_base);
	release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
}

static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
{
	u32 cap;

	cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
	UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));

	return 0;
}

static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
{
	u8 *p = (void *)h, *end = (void *)h;
	struct ivhd_entry *dev;

	p += sizeof(*h);
	end += h->length;

	find_last_devid_on_pci(PCI_BUS(h->devid),
			PCI_SLOT(h->devid),
			PCI_FUNC(h->devid),
			h->cap_ptr);

	while (p < end) {
		dev = (struct ivhd_entry *)p;
		switch (dev->type) {
		case IVHD_DEV_SELECT:
		case IVHD_DEV_RANGE_END:
		case IVHD_DEV_ALIAS:
		case IVHD_DEV_EXT_SELECT:
			UPDATE_LAST_BDF(dev->devid);
			break;
		default:
			break;
		}
		p += 0x04 << (*p >> 6);
	}

	WARN_ON(p != end);

	return 0;
}

static int __init find_last_devid_acpi(struct acpi_table_header *table)
{
	int i;
	u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
	struct ivhd_header *h;

	/*
	 * Validate checksum here so we don't need to do it when
	 * we actually parse the table
	 */
	for (i = 0; i < table->length; ++i)
		checksum += p[i];
	if (checksum != 0)
		/* ACPI table corrupt */
		return -ENODEV;

	p += IVRS_HEADER_LENGTH;

	end += table->length;
	while (p < end) {
		h = (struct ivhd_header *)p;
		switch (h->type) {
		case ACPI_IVHD_TYPE:
			find_last_devid_from_ivhd(h);
			break;
		default:
			break;
		}
		p += h->length;
	}
	WARN_ON(p != end);

	return 0;
}
Commit	Line	Data
f6e2e6b6 JR	1	/*
	2	* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
	3	* Author: Joerg Roedel <[email protected]>
	4	* Leo Duran <[email protected]>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/pci.h>
	21	#include <linux/acpi.h>
	22	#include <linux/gfp.h>
	23	#include <linux/list.h>
	24	#include <asm/pci-direct.h>
	25	#include <asm/amd_iommu_types.h>
	26	#include <asm/gart.h>
	27
	28	/*
	29	* definitions for the ACPI scanning code
	30	*/
	31	#define UPDATE_LAST_BDF(x) do {\
	32	if ((x) > amd_iommu_last_bdf) \
	33	amd_iommu_last_bdf = (x); \
	34	} while (0);
	35
	36	#define DEVID(bus, devfn) (((bus) << 8) \| (devfn))
	37	#define PCI_BUS(x) (((x) >> 8) & 0xff)
	38	#define IVRS_HEADER_LENGTH 48
	39	#define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
	40
	41	#define ACPI_IVHD_TYPE 0x10
	42	#define ACPI_IVMD_TYPE_ALL 0x20
	43	#define ACPI_IVMD_TYPE 0x21
	44	#define ACPI_IVMD_TYPE_RANGE 0x22
	45
	46	#define IVHD_DEV_ALL 0x01
	47	#define IVHD_DEV_SELECT 0x02
	48	#define IVHD_DEV_SELECT_RANGE_START 0x03
	49	#define IVHD_DEV_RANGE_END 0x04
	50	#define IVHD_DEV_ALIAS 0x42
	51	#define IVHD_DEV_ALIAS_RANGE 0x43
	52	#define IVHD_DEV_EXT_SELECT 0x46
	53	#define IVHD_DEV_EXT_SELECT_RANGE 0x47
	54
	55	#define IVHD_FLAG_HT_TUN_EN 0x00
	56	#define IVHD_FLAG_PASSPW_EN 0x01
	57	#define IVHD_FLAG_RESPASSPW_EN 0x02
	58	#define IVHD_FLAG_ISOC_EN 0x03
	59
	60	#define IVMD_FLAG_EXCL_RANGE 0x08
	61	#define IVMD_FLAG_UNITY_MAP 0x01
	62
	63	#define ACPI_DEVFLAG_INITPASS 0x01
	64	#define ACPI_DEVFLAG_EXTINT 0x02
65	#define ACPI_DEVFLAG_NMI 0x04
66	#define ACPI_DEVFLAG_SYSMGT1 0x10
67	#define ACPI_DEVFLAG_SYSMGT2 0x20
68	#define ACPI_DEVFLAG_LINT0 0x40
69	#define ACPI_DEVFLAG_LINT1 0x80
70	#define ACPI_DEVFLAG_ATSDIS 0x10000000
71
72	struct ivhd_header {
73	u8 type;
74	u8 flags;
75	u16 length;
76	u16 devid;
77	u16 cap_ptr;
78	u64 mmio_phys;
79	u16 pci_seg;
80	u16 info;
81	u32 reserved;
82	} __attribute__((packed));
83
84	struct ivhd_entry {
85	u8 type;
86	u16 devid;
87	u8 flags;
88	u32 ext;
89	} __attribute__((packed));
90
91	struct ivmd_header {
92	u8 type;
93	u8 flags;
94	u16 length;
95	u16 devid;
96	u16 aux;
97	u64 resv;
98	u64 range_start;
99	u64 range_length;
100	} __attribute__((packed));
101
928abd25 JR	102	static int __initdata amd_iommu_disable;
	103
	104	u16 amd_iommu_last_bdf;
	105	struct list_head amd_iommu_unity_map;
	106	unsigned amd_iommu_aperture_order = 26;
	107	int amd_iommu_isolate;
	108
	109	struct list_head amd_iommu_list;
	110	struct dev_table_entry *amd_iommu_dev_table;
	111	u16 *amd_iommu_alias_table;
	112	struct amd_iommu **amd_iommu_rlookup_table;
	113	struct protection_domain **amd_iommu_pd_table;
	114	unsigned long *amd_iommu_pd_alloc_bitmap;
	115
	116	static u32 dev_table_size;
	117	static u32 alias_table_size;
	118	static u32 rlookup_table_size;
3e8064ba	119
b2026aa2 JR	120	static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
	121	{
	122	u64 start = iommu->exclusion_start & PAGE_MASK;
	123	u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
	124	u64 entry;
	125
	126	if (!iommu->exclusion_start)
	127	return;
	128
	129	entry = start \| MMIO_EXCL_ENABLE_MASK;
	130	memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
	131	&entry, sizeof(entry));
	132
	133	entry = limit;
	134	memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
	135	&entry, sizeof(entry));
	136	}
	137
	138	static void __init iommu_set_device_table(struct amd_iommu *iommu)
	139	{
	140	u32 entry;
	141
	142	BUG_ON(iommu->mmio_base == NULL);
	143
	144	entry = virt_to_phys(amd_iommu_dev_table);
	145	entry \|= (dev_table_size >> 12) - 1;
	146	memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
	147	&entry, sizeof(entry));
	148	}
	149
	150	static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
	151	{
	152	u32 ctrl;
	153
	154	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	155	ctrl \|= (1 << bit);
	156	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
	157	}
	158
	159	static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
	160	{
	161	u32 ctrl;
	162
	163	ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	164	ctrl &= ~(1 << bit);
	165	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
	166	}
	167
	168	void __init iommu_enable(struct amd_iommu *iommu)
	169	{
	170	u32 ctrl;
	171
	172	printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
	173	print_devid(iommu->devid, 0);
	174	printk(" cap 0x%hx\n", iommu->cap_ptr);
	175
	176	iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
	177	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	178	}
	179
6c56747b JR	180	static u8 * __init iommu_map_mmio_space(u64 address)
	181	{
	182	u8 *ret;
	183
	184	if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
	185	return NULL;
	186
	187	ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
	188	if (ret != NULL)
	189	return ret;
	190
	191	release_mem_region(address, MMIO_REGION_LENGTH);
	192
	193	return NULL;
	194	}
	195
	196	static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
	197	{
	198	if (iommu->mmio_base)
	199	iounmap(iommu->mmio_base);
	200	release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
	201	}
	202
3e8064ba JR	203	static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
	204	{
	205	u32 cap;
	206
	207	cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
	208	UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
	209
	210	return 0;
	211	}
	212
	213	static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
	214	{
	215	u8 p = (void )h, end = (void )h;
	216	struct ivhd_entry *dev;
	217
	218	p += sizeof(*h);
	219	end += h->length;
	220
	221	find_last_devid_on_pci(PCI_BUS(h->devid),
	222	PCI_SLOT(h->devid),
	223	PCI_FUNC(h->devid),
	224	h->cap_ptr);
	225
	226	while (p < end) {
	227	dev = (struct ivhd_entry *)p;
	228	switch (dev->type) {
	229	case IVHD_DEV_SELECT:
	230	case IVHD_DEV_RANGE_END:
	231	case IVHD_DEV_ALIAS:
	232	case IVHD_DEV_EXT_SELECT:
	233	UPDATE_LAST_BDF(dev->devid);
	234	break;
	235	default:
	236	break;
	237	}
	238	p += 0x04 << (*p >> 6);
	239	}
	240
	241	WARN_ON(p != end);
	242
	243	return 0;
	244	}
	245
	246	static int __init find_last_devid_acpi(struct acpi_table_header *table)
	247	{
	248	int i;
	249	u8 checksum = 0, p = (u8 )table, end = (u8 )table;
	250	struct ivhd_header *h;
	251
	252	/*
	253	* Validate checksum here so we don't need to do it when
	254	* we actually parse the table
	255	*/
	256	for (i = 0; i < table->length; ++i)
	257	checksum += p[i];
	258	if (checksum != 0)
	259	/* ACPI table corrupt */
	260	return -ENODEV;
	261
	262	p += IVRS_HEADER_LENGTH;
	263
	264	end += table->length;
	265	while (p < end) {
	266	h = (struct ivhd_header *)p;
267	switch (h->type) {
268	case ACPI_IVHD_TYPE:
269	find_last_devid_from_ivhd(h);
270	break;
271	default:
272	break;
273	}
274	p += h->length;
275	}
276	WARN_ON(p != end);
277
278	return 0;
279	}
280