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Commit | Line | Data |
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317a6104 PM |
1 | /* |
2 | * SuperH On-Chip RTC Support | |
3 | * | |
b420b1a7 | 4 | * Copyright (C) 2006, 2007, 2008 Paul Mundt |
1b73e6ae | 5 | * Copyright (C) 2006 Jamie Lenehan |
b420b1a7 | 6 | * Copyright (C) 2008 Angelo Castello |
317a6104 PM |
7 | * |
8 | * Based on the old arch/sh/kernel/cpu/rtc.c by: | |
9 | * | |
10 | * Copyright (C) 2000 Philipp Rumpf <[email protected]> | |
11 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka | |
12 | * | |
13 | * This file is subject to the terms and conditions of the GNU General Public | |
14 | * License. See the file "COPYING" in the main directory of this archive | |
15 | * for more details. | |
16 | */ | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/bcd.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/seq_file.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/spinlock.h> | |
31ccb081 | 26 | #include <linux/io.h> |
ad89f87a | 27 | #include <asm/rtc.h> |
317a6104 | 28 | |
1b73e6ae | 29 | #define DRV_NAME "sh-rtc" |
b420b1a7 | 30 | #define DRV_VERSION "0.2.0" |
317a6104 PM |
31 | |
32 | #define RTC_REG(r) ((r) * rtc_reg_size) | |
33 | ||
31ccb081 | 34 | #define R64CNT RTC_REG(0) |
1b73e6ae JL |
35 | |
36 | #define RSECCNT RTC_REG(1) /* RTC sec */ | |
37 | #define RMINCNT RTC_REG(2) /* RTC min */ | |
38 | #define RHRCNT RTC_REG(3) /* RTC hour */ | |
39 | #define RWKCNT RTC_REG(4) /* RTC week */ | |
40 | #define RDAYCNT RTC_REG(5) /* RTC day */ | |
41 | #define RMONCNT RTC_REG(6) /* RTC month */ | |
42 | #define RYRCNT RTC_REG(7) /* RTC year */ | |
43 | #define RSECAR RTC_REG(8) /* ALARM sec */ | |
44 | #define RMINAR RTC_REG(9) /* ALARM min */ | |
45 | #define RHRAR RTC_REG(10) /* ALARM hour */ | |
46 | #define RWKAR RTC_REG(11) /* ALARM week */ | |
47 | #define RDAYAR RTC_REG(12) /* ALARM day */ | |
48 | #define RMONAR RTC_REG(13) /* ALARM month */ | |
49 | #define RCR1 RTC_REG(14) /* Control */ | |
50 | #define RCR2 RTC_REG(15) /* Control */ | |
51 | ||
ff1b7506 PM |
52 | /* |
53 | * Note on RYRAR and RCR3: Up until this point most of the register | |
54 | * definitions are consistent across all of the available parts. However, | |
55 | * the placement of the optional RYRAR and RCR3 (the RYRAR control | |
56 | * register used to control RYRCNT/RYRAR compare) varies considerably | |
57 | * across various parts, occasionally being mapped in to a completely | |
58 | * unrelated address space. For proper RYRAR support a separate resource | |
59 | * would have to be handed off, but as this is purely optional in | |
60 | * practice, we simply opt not to support it, thereby keeping the code | |
61 | * quite a bit more simplified. | |
62 | */ | |
63 | ||
1b73e6ae JL |
64 | /* ALARM Bits - or with BCD encoded value */ |
65 | #define AR_ENB 0x80 /* Enable for alarm cmp */ | |
317a6104 | 66 | |
b420b1a7 AC |
67 | /* Period Bits */ |
68 | #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */ | |
69 | #define PF_COUNT 0x200 /* Half periodic counter */ | |
70 | #define PF_OXS 0x400 /* Periodic One x Second */ | |
71 | #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */ | |
72 | #define PF_MASK 0xf00 | |
73 | ||
317a6104 PM |
74 | /* RCR1 Bits */ |
75 | #define RCR1_CF 0x80 /* Carry Flag */ | |
76 | #define RCR1_CIE 0x10 /* Carry Interrupt Enable */ | |
77 | #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ | |
78 | #define RCR1_AF 0x01 /* Alarm Flag */ | |
79 | ||
80 | /* RCR2 Bits */ | |
81 | #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ | |
82 | #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ | |
83 | #define RCR2_RTCEN 0x08 /* ENable RTC */ | |
84 | #define RCR2_ADJ 0x04 /* ADJustment (30-second) */ | |
85 | #define RCR2_RESET 0x02 /* Reset bit */ | |
86 | #define RCR2_START 0x01 /* Start bit */ | |
87 | ||
88 | struct sh_rtc { | |
89 | void __iomem *regbase; | |
90 | unsigned long regsize; | |
91 | struct resource *res; | |
92 | unsigned int alarm_irq, periodic_irq, carry_irq; | |
93 | struct rtc_device *rtc_dev; | |
94 | spinlock_t lock; | |
ad89f87a | 95 | unsigned long capabilities; /* See asm-sh/rtc.h for cap bits */ |
b420b1a7 | 96 | unsigned short periodic_freq; |
317a6104 PM |
97 | }; |
98 | ||
31ccb081 | 99 | static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) |
317a6104 | 100 | { |
b420b1a7 AC |
101 | struct sh_rtc *rtc = dev_id; |
102 | unsigned int tmp; | |
317a6104 PM |
103 | |
104 | spin_lock(&rtc->lock); | |
105 | ||
106 | tmp = readb(rtc->regbase + RCR1); | |
1b73e6ae | 107 | tmp &= ~RCR1_CF; |
317a6104 PM |
108 | writeb(tmp, rtc->regbase + RCR1); |
109 | ||
b420b1a7 AC |
110 | /* Users have requested One x Second IRQ */ |
111 | if (rtc->periodic_freq & PF_OXS) | |
112 | rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); | |
317a6104 PM |
113 | |
114 | spin_unlock(&rtc->lock); | |
115 | ||
116 | return IRQ_HANDLED; | |
117 | } | |
118 | ||
1b73e6ae JL |
119 | static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) |
120 | { | |
b420b1a7 AC |
121 | struct sh_rtc *rtc = dev_id; |
122 | unsigned int tmp; | |
1b73e6ae JL |
123 | |
124 | spin_lock(&rtc->lock); | |
125 | ||
126 | tmp = readb(rtc->regbase + RCR1); | |
b420b1a7 | 127 | tmp &= ~(RCR1_AF | RCR1_AIE); |
1b73e6ae JL |
128 | writeb(tmp, rtc->regbase + RCR1); |
129 | ||
b420b1a7 | 130 | rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); |
1b73e6ae JL |
131 | |
132 | spin_unlock(&rtc->lock); | |
b420b1a7 | 133 | |
1b73e6ae JL |
134 | return IRQ_HANDLED; |
135 | } | |
136 | ||
31ccb081 | 137 | static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) |
317a6104 | 138 | { |
b420b1a7 AC |
139 | struct sh_rtc *rtc = dev_id; |
140 | struct rtc_device *rtc_dev = rtc->rtc_dev; | |
141 | unsigned int tmp; | |
317a6104 PM |
142 | |
143 | spin_lock(&rtc->lock); | |
144 | ||
b420b1a7 AC |
145 | tmp = readb(rtc->regbase + RCR2); |
146 | tmp &= ~RCR2_PEF; | |
147 | writeb(tmp, rtc->regbase + RCR2); | |
148 | ||
149 | /* Half period enabled than one skipped and the next notified */ | |
150 | if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) | |
151 | rtc->periodic_freq &= ~PF_COUNT; | |
152 | else { | |
153 | if (rtc->periodic_freq & PF_HP) | |
154 | rtc->periodic_freq |= PF_COUNT; | |
155 | if (rtc->periodic_freq & PF_KOU) { | |
156 | spin_lock(&rtc_dev->irq_task_lock); | |
157 | if (rtc_dev->irq_task) | |
158 | rtc_dev->irq_task->func(rtc_dev->irq_task->private_data); | |
159 | spin_unlock(&rtc_dev->irq_task_lock); | |
160 | } else | |
161 | rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); | |
162 | } | |
317a6104 PM |
163 | |
164 | spin_unlock(&rtc->lock); | |
165 | ||
166 | return IRQ_HANDLED; | |
167 | } | |
168 | ||
169 | static inline void sh_rtc_setpie(struct device *dev, unsigned int enable) | |
170 | { | |
171 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
172 | unsigned int tmp; | |
173 | ||
174 | spin_lock_irq(&rtc->lock); | |
175 | ||
176 | tmp = readb(rtc->regbase + RCR2); | |
177 | ||
178 | if (enable) { | |
b420b1a7 AC |
179 | tmp &= ~RCR2_PEF; /* Clear PES bit */ |
180 | tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ | |
317a6104 PM |
181 | } else |
182 | tmp &= ~(RCR2_PESMASK | RCR2_PEF); | |
183 | ||
184 | writeb(tmp, rtc->regbase + RCR2); | |
185 | ||
186 | spin_unlock_irq(&rtc->lock); | |
187 | } | |
188 | ||
b420b1a7 | 189 | static inline int sh_rtc_setfreq(struct device *dev, unsigned int freq) |
317a6104 PM |
190 | { |
191 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
b420b1a7 | 192 | int tmp, ret = 0; |
317a6104 PM |
193 | |
194 | spin_lock_irq(&rtc->lock); | |
b420b1a7 | 195 | tmp = rtc->periodic_freq & PF_MASK; |
317a6104 | 196 | |
b420b1a7 AC |
197 | switch (freq) { |
198 | case 0: | |
199 | rtc->periodic_freq = 0x00; | |
200 | break; | |
201 | case 1: | |
202 | rtc->periodic_freq = 0x60; | |
203 | break; | |
204 | case 2: | |
205 | rtc->periodic_freq = 0x50; | |
206 | break; | |
207 | case 4: | |
208 | rtc->periodic_freq = 0x40; | |
209 | break; | |
210 | case 8: | |
211 | rtc->periodic_freq = 0x30 | PF_HP; | |
212 | break; | |
213 | case 16: | |
214 | rtc->periodic_freq = 0x30; | |
215 | break; | |
216 | case 32: | |
217 | rtc->periodic_freq = 0x20 | PF_HP; | |
218 | break; | |
219 | case 64: | |
220 | rtc->periodic_freq = 0x20; | |
221 | break; | |
222 | case 128: | |
223 | rtc->periodic_freq = 0x10 | PF_HP; | |
224 | break; | |
225 | case 256: | |
226 | rtc->periodic_freq = 0x10; | |
227 | break; | |
228 | default: | |
229 | ret = -ENOTSUPP; | |
230 | } | |
317a6104 | 231 | |
b420b1a7 AC |
232 | if (ret == 0) { |
233 | rtc->periodic_freq |= tmp; | |
234 | rtc->rtc_dev->irq_freq = freq; | |
235 | } | |
317a6104 PM |
236 | |
237 | spin_unlock_irq(&rtc->lock); | |
b420b1a7 | 238 | return ret; |
317a6104 PM |
239 | } |
240 | ||
b420b1a7 | 241 | static inline void sh_rtc_setaie(struct device *dev, unsigned int enable) |
317a6104 PM |
242 | { |
243 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
244 | unsigned int tmp; | |
317a6104 | 245 | |
b420b1a7 | 246 | spin_lock_irq(&rtc->lock); |
317a6104 | 247 | |
b420b1a7 | 248 | tmp = readb(rtc->regbase + RCR1); |
317a6104 | 249 | |
b420b1a7 AC |
250 | if (!enable) |
251 | tmp &= ~RCR1_AIE; | |
252 | else | |
253 | tmp |= RCR1_AIE; | |
317a6104 | 254 | |
b420b1a7 | 255 | writeb(tmp, rtc->regbase + RCR1); |
317a6104 | 256 | |
b420b1a7 | 257 | spin_unlock_irq(&rtc->lock); |
317a6104 PM |
258 | } |
259 | ||
260 | static void sh_rtc_release(struct device *dev) | |
261 | { | |
317a6104 | 262 | sh_rtc_setpie(dev, 0); |
1b73e6ae | 263 | sh_rtc_setaie(dev, 0); |
317a6104 PM |
264 | } |
265 | ||
266 | static int sh_rtc_proc(struct device *dev, struct seq_file *seq) | |
267 | { | |
268 | struct sh_rtc *rtc = dev_get_drvdata(dev); | |
269 | unsigned int tmp; | |
270 | ||
271 | tmp = readb(rtc->regbase + RCR1); | |
b420b1a7 | 272 | seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); |
317a6104 PM |
273 | |
274 | tmp = readb(rtc->regbase + RCR2); | |
275 | seq_printf(seq, "periodic_IRQ\t: %s\n", | |
b420b1a7 | 276 | (tmp & RCR2_PESMASK) ? "yes" : "no"); |
317a6104 PM |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
281 | static int sh_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
282 | { | |
b420b1a7 AC |
283 | struct sh_rtc *rtc = dev_get_drvdata(dev); |
284 | unsigned int ret = 0; | |
317a6104 PM |
285 | |
286 | switch (cmd) { | |
287 | case RTC_PIE_OFF: | |
288 | case RTC_PIE_ON: | |
289 | sh_rtc_setpie(dev, cmd == RTC_PIE_ON); | |
317a6104 PM |
290 | break; |
291 | case RTC_AIE_OFF: | |
292 | case RTC_AIE_ON: | |
293 | sh_rtc_setaie(dev, cmd == RTC_AIE_ON); | |
317a6104 | 294 | break; |
b420b1a7 AC |
295 | case RTC_UIE_OFF: |
296 | rtc->periodic_freq &= ~PF_OXS; | |
297 | break; | |
298 | case RTC_UIE_ON: | |
299 | rtc->periodic_freq |= PF_OXS; | |
300 | break; | |
301 | case RTC_IRQP_READ: | |
302 | ret = put_user(rtc->rtc_dev->irq_freq, | |
303 | (unsigned long __user *)arg); | |
304 | break; | |
305 | case RTC_IRQP_SET: | |
306 | ret = sh_rtc_setfreq(dev, arg); | |
307 | break; | |
308 | default: | |
309 | ret = -ENOIOCTLCMD; | |
317a6104 PM |
310 | } |
311 | ||
312 | return ret; | |
313 | } | |
314 | ||
315 | static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
316 | { | |
317 | struct platform_device *pdev = to_platform_device(dev); | |
318 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
319 | unsigned int sec128, sec2, yr, yr100, cf_bit; | |
320 | ||
321 | do { | |
322 | unsigned int tmp; | |
323 | ||
324 | spin_lock_irq(&rtc->lock); | |
325 | ||
326 | tmp = readb(rtc->regbase + RCR1); | |
327 | tmp &= ~RCR1_CF; /* Clear CF-bit */ | |
328 | tmp |= RCR1_CIE; | |
329 | writeb(tmp, rtc->regbase + RCR1); | |
330 | ||
331 | sec128 = readb(rtc->regbase + R64CNT); | |
332 | ||
333 | tm->tm_sec = BCD2BIN(readb(rtc->regbase + RSECCNT)); | |
334 | tm->tm_min = BCD2BIN(readb(rtc->regbase + RMINCNT)); | |
335 | tm->tm_hour = BCD2BIN(readb(rtc->regbase + RHRCNT)); | |
336 | tm->tm_wday = BCD2BIN(readb(rtc->regbase + RWKCNT)); | |
337 | tm->tm_mday = BCD2BIN(readb(rtc->regbase + RDAYCNT)); | |
a1614796 | 338 | tm->tm_mon = BCD2BIN(readb(rtc->regbase + RMONCNT)) - 1; |
317a6104 | 339 | |
ad89f87a PM |
340 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
341 | yr = readw(rtc->regbase + RYRCNT); | |
342 | yr100 = BCD2BIN(yr >> 8); | |
343 | yr &= 0xff; | |
344 | } else { | |
345 | yr = readb(rtc->regbase + RYRCNT); | |
346 | yr100 = BCD2BIN((yr == 0x99) ? 0x19 : 0x20); | |
347 | } | |
317a6104 PM |
348 | |
349 | tm->tm_year = (yr100 * 100 + BCD2BIN(yr)) - 1900; | |
350 | ||
351 | sec2 = readb(rtc->regbase + R64CNT); | |
352 | cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; | |
353 | ||
354 | spin_unlock_irq(&rtc->lock); | |
355 | } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); | |
356 | ||
357 | #if RTC_BIT_INVERTED != 0 | |
358 | if ((sec128 & RTC_BIT_INVERTED)) | |
359 | tm->tm_sec--; | |
360 | #endif | |
361 | ||
435c55d1 | 362 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " |
317a6104 | 363 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 364 | __func__, |
317a6104 | 365 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
a1614796 | 366 | tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); |
317a6104 | 367 | |
0ac554b9 | 368 | if (rtc_valid_tm(tm) < 0) { |
317a6104 | 369 | dev_err(dev, "invalid date\n"); |
0ac554b9 PM |
370 | rtc_time_to_tm(0, tm); |
371 | } | |
317a6104 PM |
372 | |
373 | return 0; | |
374 | } | |
375 | ||
376 | static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
377 | { | |
378 | struct platform_device *pdev = to_platform_device(dev); | |
379 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
380 | unsigned int tmp; | |
381 | int year; | |
382 | ||
383 | spin_lock_irq(&rtc->lock); | |
384 | ||
385 | /* Reset pre-scaler & stop RTC */ | |
386 | tmp = readb(rtc->regbase + RCR2); | |
387 | tmp |= RCR2_RESET; | |
699bc661 | 388 | tmp &= ~RCR2_START; |
317a6104 PM |
389 | writeb(tmp, rtc->regbase + RCR2); |
390 | ||
391 | writeb(BIN2BCD(tm->tm_sec), rtc->regbase + RSECCNT); | |
392 | writeb(BIN2BCD(tm->tm_min), rtc->regbase + RMINCNT); | |
393 | writeb(BIN2BCD(tm->tm_hour), rtc->regbase + RHRCNT); | |
394 | writeb(BIN2BCD(tm->tm_wday), rtc->regbase + RWKCNT); | |
395 | writeb(BIN2BCD(tm->tm_mday), rtc->regbase + RDAYCNT); | |
a1614796 | 396 | writeb(BIN2BCD(tm->tm_mon + 1), rtc->regbase + RMONCNT); |
317a6104 | 397 | |
ad89f87a PM |
398 | if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { |
399 | year = (BIN2BCD((tm->tm_year + 1900) / 100) << 8) | | |
400 | BIN2BCD(tm->tm_year % 100); | |
401 | writew(year, rtc->regbase + RYRCNT); | |
402 | } else { | |
403 | year = tm->tm_year % 100; | |
404 | writeb(BIN2BCD(year), rtc->regbase + RYRCNT); | |
405 | } | |
317a6104 PM |
406 | |
407 | /* Start RTC */ | |
408 | tmp = readb(rtc->regbase + RCR2); | |
409 | tmp &= ~RCR2_RESET; | |
410 | tmp |= RCR2_RTCEN | RCR2_START; | |
411 | writeb(tmp, rtc->regbase + RCR2); | |
412 | ||
413 | spin_unlock_irq(&rtc->lock); | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
1b73e6ae JL |
418 | static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) |
419 | { | |
420 | unsigned int byte; | |
421 | int value = 0xff; /* return 0xff for ignored values */ | |
422 | ||
423 | byte = readb(rtc->regbase + reg_off); | |
424 | if (byte & AR_ENB) { | |
425 | byte &= ~AR_ENB; /* strip the enable bit */ | |
426 | value = BCD2BIN(byte); | |
427 | } | |
428 | ||
429 | return value; | |
430 | } | |
431 | ||
432 | static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
433 | { | |
434 | struct platform_device *pdev = to_platform_device(dev); | |
435 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
b420b1a7 | 436 | struct rtc_time *tm = &wkalrm->time; |
1b73e6ae JL |
437 | |
438 | spin_lock_irq(&rtc->lock); | |
439 | ||
440 | tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); | |
441 | tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); | |
442 | tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); | |
443 | tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); | |
444 | tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); | |
445 | tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); | |
446 | if (tm->tm_mon > 0) | |
447 | tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ | |
448 | tm->tm_year = 0xffff; | |
449 | ||
0d103e90 DB |
450 | wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; |
451 | ||
1b73e6ae JL |
452 | spin_unlock_irq(&rtc->lock); |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, | |
458 | int value, int reg_off) | |
459 | { | |
460 | /* < 0 for a value that is ignored */ | |
461 | if (value < 0) | |
462 | writeb(0, rtc->regbase + reg_off); | |
463 | else | |
464 | writeb(BIN2BCD(value) | AR_ENB, rtc->regbase + reg_off); | |
465 | } | |
466 | ||
b420b1a7 | 467 | static int sh_rtc_check_alarm(struct rtc_time *tm) |
1b73e6ae JL |
468 | { |
469 | /* | |
470 | * The original rtc says anything > 0xc0 is "don't care" or "match | |
471 | * all" - most users use 0xff but rtc-dev uses -1 for the same thing. | |
472 | * The original rtc doesn't support years - some things use -1 and | |
473 | * some 0xffff. We use -1 to make out tests easier. | |
474 | */ | |
475 | if (tm->tm_year == 0xffff) | |
476 | tm->tm_year = -1; | |
477 | if (tm->tm_mon >= 0xff) | |
478 | tm->tm_mon = -1; | |
479 | if (tm->tm_mday >= 0xff) | |
480 | tm->tm_mday = -1; | |
481 | if (tm->tm_wday >= 0xff) | |
482 | tm->tm_wday = -1; | |
483 | if (tm->tm_hour >= 0xff) | |
484 | tm->tm_hour = -1; | |
485 | if (tm->tm_min >= 0xff) | |
486 | tm->tm_min = -1; | |
487 | if (tm->tm_sec >= 0xff) | |
488 | tm->tm_sec = -1; | |
489 | ||
490 | if (tm->tm_year > 9999 || | |
491 | tm->tm_mon >= 12 || | |
492 | tm->tm_mday == 0 || tm->tm_mday >= 32 || | |
493 | tm->tm_wday >= 7 || | |
494 | tm->tm_hour >= 24 || | |
495 | tm->tm_min >= 60 || | |
496 | tm->tm_sec >= 60) | |
497 | return -EINVAL; | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
502 | static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) | |
503 | { | |
504 | struct platform_device *pdev = to_platform_device(dev); | |
505 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
506 | unsigned int rcr1; | |
507 | struct rtc_time *tm = &wkalrm->time; | |
508 | int mon, err; | |
509 | ||
510 | err = sh_rtc_check_alarm(tm); | |
511 | if (unlikely(err < 0)) | |
512 | return err; | |
513 | ||
514 | spin_lock_irq(&rtc->lock); | |
515 | ||
15c945c3 | 516 | /* disable alarm interrupt and clear the alarm flag */ |
1b73e6ae | 517 | rcr1 = readb(rtc->regbase + RCR1); |
b420b1a7 | 518 | rcr1 &= ~(RCR1_AF | RCR1_AIE); |
15c945c3 | 519 | writeb(rcr1, rtc->regbase + RCR1); |
1b73e6ae | 520 | |
1b73e6ae JL |
521 | /* set alarm time */ |
522 | sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); | |
523 | sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); | |
524 | sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); | |
525 | sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); | |
526 | sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); | |
527 | mon = tm->tm_mon; | |
528 | if (mon >= 0) | |
529 | mon += 1; | |
530 | sh_rtc_write_alarm_value(rtc, mon, RMONAR); | |
531 | ||
15c945c3 JL |
532 | if (wkalrm->enabled) { |
533 | rcr1 |= RCR1_AIE; | |
534 | writeb(rcr1, rtc->regbase + RCR1); | |
535 | } | |
1b73e6ae JL |
536 | |
537 | spin_unlock_irq(&rtc->lock); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
b420b1a7 AC |
542 | static int sh_rtc_irq_set_state(struct device *dev, int enabled) |
543 | { | |
544 | struct platform_device *pdev = to_platform_device(dev); | |
545 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
546 | ||
547 | if (enabled) { | |
548 | rtc->periodic_freq |= PF_KOU; | |
549 | return sh_rtc_ioctl(dev, RTC_PIE_ON, 0); | |
550 | } else { | |
551 | rtc->periodic_freq &= ~PF_KOU; | |
552 | return sh_rtc_ioctl(dev, RTC_PIE_OFF, 0); | |
553 | } | |
554 | } | |
555 | ||
556 | static int sh_rtc_irq_set_freq(struct device *dev, int freq) | |
557 | { | |
558 | return sh_rtc_ioctl(dev, RTC_IRQP_SET, freq); | |
559 | } | |
560 | ||
317a6104 | 561 | static struct rtc_class_ops sh_rtc_ops = { |
317a6104 PM |
562 | .release = sh_rtc_release, |
563 | .ioctl = sh_rtc_ioctl, | |
564 | .read_time = sh_rtc_read_time, | |
565 | .set_time = sh_rtc_set_time, | |
1b73e6ae JL |
566 | .read_alarm = sh_rtc_read_alarm, |
567 | .set_alarm = sh_rtc_set_alarm, | |
b420b1a7 AC |
568 | .irq_set_state = sh_rtc_irq_set_state, |
569 | .irq_set_freq = sh_rtc_irq_set_freq, | |
317a6104 PM |
570 | .proc = sh_rtc_proc, |
571 | }; | |
572 | ||
573 | static int __devinit sh_rtc_probe(struct platform_device *pdev) | |
574 | { | |
575 | struct sh_rtc *rtc; | |
576 | struct resource *res; | |
b420b1a7 | 577 | unsigned int tmp; |
317a6104 PM |
578 | int ret = -ENOENT; |
579 | ||
580 | rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL); | |
581 | if (unlikely(!rtc)) | |
582 | return -ENOMEM; | |
583 | ||
584 | spin_lock_init(&rtc->lock); | |
585 | ||
b420b1a7 | 586 | /* get periodic/carry/alarm irqs */ |
317a6104 PM |
587 | rtc->periodic_irq = platform_get_irq(pdev, 0); |
588 | if (unlikely(rtc->periodic_irq < 0)) { | |
589 | dev_err(&pdev->dev, "No IRQ for period\n"); | |
590 | goto err_badres; | |
591 | } | |
592 | ||
593 | rtc->carry_irq = platform_get_irq(pdev, 1); | |
594 | if (unlikely(rtc->carry_irq < 0)) { | |
595 | dev_err(&pdev->dev, "No IRQ for carry\n"); | |
596 | goto err_badres; | |
597 | } | |
598 | ||
599 | rtc->alarm_irq = platform_get_irq(pdev, 2); | |
600 | if (unlikely(rtc->alarm_irq < 0)) { | |
601 | dev_err(&pdev->dev, "No IRQ for alarm\n"); | |
602 | goto err_badres; | |
603 | } | |
604 | ||
605 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
606 | if (unlikely(res == NULL)) { | |
607 | dev_err(&pdev->dev, "No IO resource\n"); | |
608 | goto err_badres; | |
609 | } | |
610 | ||
611 | rtc->regsize = res->end - res->start + 1; | |
612 | ||
613 | rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name); | |
614 | if (unlikely(!rtc->res)) { | |
615 | ret = -EBUSY; | |
616 | goto err_badres; | |
617 | } | |
618 | ||
0305794c | 619 | rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize); |
317a6104 PM |
620 | if (unlikely(!rtc->regbase)) { |
621 | ret = -EINVAL; | |
622 | goto err_badmap; | |
623 | } | |
624 | ||
625 | rtc->rtc_dev = rtc_device_register("sh", &pdev->dev, | |
626 | &sh_rtc_ops, THIS_MODULE); | |
29dd0dae | 627 | if (IS_ERR(rtc->rtc_dev)) { |
317a6104 | 628 | ret = PTR_ERR(rtc->rtc_dev); |
0305794c | 629 | goto err_unmap; |
317a6104 PM |
630 | } |
631 | ||
ad89f87a PM |
632 | rtc->capabilities = RTC_DEF_CAPABILITIES; |
633 | if (pdev->dev.platform_data) { | |
634 | struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data; | |
635 | ||
636 | /* | |
637 | * Some CPUs have special capabilities in addition to the | |
638 | * default set. Add those in here. | |
639 | */ | |
640 | rtc->capabilities |= pinfo->capabilities; | |
641 | } | |
642 | ||
b420b1a7 AC |
643 | rtc->rtc_dev->max_user_freq = 256; |
644 | rtc->rtc_dev->irq_freq = 1; | |
645 | rtc->periodic_freq = 0x60; | |
646 | ||
317a6104 PM |
647 | platform_set_drvdata(pdev, rtc); |
648 | ||
b420b1a7 AC |
649 | /* register periodic/carry/alarm irqs */ |
650 | ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, IRQF_DISABLED, | |
651 | "sh-rtc period", rtc); | |
652 | if (unlikely(ret)) { | |
653 | dev_err(&pdev->dev, | |
654 | "request period IRQ failed with %d, IRQ %d\n", ret, | |
655 | rtc->periodic_irq); | |
0305794c | 656 | goto err_unmap; |
b420b1a7 AC |
657 | } |
658 | ||
659 | ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED, | |
660 | "sh-rtc carry", rtc); | |
661 | if (unlikely(ret)) { | |
662 | dev_err(&pdev->dev, | |
663 | "request carry IRQ failed with %d, IRQ %d\n", ret, | |
664 | rtc->carry_irq); | |
665 | free_irq(rtc->periodic_irq, rtc); | |
0305794c | 666 | goto err_unmap; |
b420b1a7 AC |
667 | } |
668 | ||
669 | ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED, | |
670 | "sh-rtc alarm", rtc); | |
671 | if (unlikely(ret)) { | |
672 | dev_err(&pdev->dev, | |
673 | "request alarm IRQ failed with %d, IRQ %d\n", ret, | |
674 | rtc->alarm_irq); | |
675 | free_irq(rtc->carry_irq, rtc); | |
676 | free_irq(rtc->periodic_irq, rtc); | |
0305794c | 677 | goto err_unmap; |
b420b1a7 AC |
678 | } |
679 | ||
680 | tmp = readb(rtc->regbase + RCR1); | |
681 | tmp &= ~RCR1_CF; | |
682 | tmp |= RCR1_CIE; | |
683 | writeb(tmp, rtc->regbase + RCR1); | |
684 | ||
317a6104 PM |
685 | return 0; |
686 | ||
0305794c PM |
687 | err_unmap: |
688 | iounmap(rtc->regbase); | |
317a6104 PM |
689 | err_badmap: |
690 | release_resource(rtc->res); | |
691 | err_badres: | |
692 | kfree(rtc); | |
693 | ||
694 | return ret; | |
695 | } | |
696 | ||
697 | static int __devexit sh_rtc_remove(struct platform_device *pdev) | |
698 | { | |
699 | struct sh_rtc *rtc = platform_get_drvdata(pdev); | |
700 | ||
701 | if (likely(rtc->rtc_dev)) | |
702 | rtc_device_unregister(rtc->rtc_dev); | |
703 | ||
704 | sh_rtc_setpie(&pdev->dev, 0); | |
705 | sh_rtc_setaie(&pdev->dev, 0); | |
706 | ||
b420b1a7 AC |
707 | free_irq(rtc->carry_irq, rtc); |
708 | free_irq(rtc->periodic_irq, rtc); | |
709 | free_irq(rtc->alarm_irq, rtc); | |
710 | ||
317a6104 PM |
711 | release_resource(rtc->res); |
712 | ||
0305794c PM |
713 | iounmap(rtc->regbase); |
714 | ||
317a6104 PM |
715 | platform_set_drvdata(pdev, NULL); |
716 | ||
717 | kfree(rtc); | |
718 | ||
719 | return 0; | |
720 | } | |
721 | static struct platform_driver sh_rtc_platform_driver = { | |
722 | .driver = { | |
1b73e6ae | 723 | .name = DRV_NAME, |
317a6104 PM |
724 | .owner = THIS_MODULE, |
725 | }, | |
726 | .probe = sh_rtc_probe, | |
727 | .remove = __devexit_p(sh_rtc_remove), | |
728 | }; | |
729 | ||
730 | static int __init sh_rtc_init(void) | |
731 | { | |
732 | return platform_driver_register(&sh_rtc_platform_driver); | |
733 | } | |
734 | ||
735 | static void __exit sh_rtc_exit(void) | |
736 | { | |
737 | platform_driver_unregister(&sh_rtc_platform_driver); | |
738 | } | |
739 | ||
740 | module_init(sh_rtc_init); | |
741 | module_exit(sh_rtc_exit); | |
742 | ||
743 | MODULE_DESCRIPTION("SuperH on-chip RTC driver"); | |
1b73e6ae | 744 | MODULE_VERSION(DRV_VERSION); |
b420b1a7 AC |
745 | MODULE_AUTHOR("Paul Mundt <[email protected]>, " |
746 | "Jamie Lenehan <[email protected]>, " | |
747 | "Angelo Castello <[email protected]>"); | |
317a6104 | 748 | MODULE_LICENSE("GPL"); |
ad28a07b | 749 | MODULE_ALIAS("platform:" DRV_NAME); |