[linux.git] / drivers / pwm / pwm-atmel.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Atmel Pulse Width Modulation Controller
 *
 * Copyright (C) 2013 Atmel Corporation
 *		 Bo Shen <[email protected]>
 *
 * Links to reference manuals for the supported PWM chips can be found in
 * Documentation/arm/microchip.rst.
 *
 * Limitations:
 * - Periods start with the inactive level.
 * - Hardware has to be stopped in general to update settings.
 *
 * Software bugs/possible improvements:
 * - When atmel_pwm_apply() is called with state->enabled=false a change in
 *   state->polarity isn't honored.
 * - Instead of sleeping to wait for a completed period, the interrupt
 *   functionality could be used.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

/* The following is global registers for PWM controller */
#define PWM_ENA			0x04
#define PWM_DIS			0x08
#define PWM_SR			0x0C
#define PWM_ISR			0x1C
/* Bit field in SR */
#define PWM_SR_ALL_CH_ON	0x0F

/* The following register is PWM channel related registers */
#define PWM_CH_REG_OFFSET	0x200
#define PWM_CH_REG_SIZE		0x20

#define PWM_CMR			0x0
/* Bit field in CMR */
#define PWM_CMR_CPOL		(1 << 9)
#define PWM_CMR_UPD_CDTY	(1 << 10)
#define PWM_CMR_CPRE_MSK	0xF

/* The following registers for PWM v1 */
#define PWMV1_CDTY		0x04
#define PWMV1_CPRD		0x08
#define PWMV1_CUPD		0x10

/* The following registers for PWM v2 */
#define PWMV2_CDTY		0x04
#define PWMV2_CDTYUPD		0x08
#define PWMV2_CPRD		0x0C
#define PWMV2_CPRDUPD		0x10

#define PWM_MAX_PRES		10

struct atmel_pwm_registers {
	u8 period;
	u8 period_upd;
	u8 duty;
	u8 duty_upd;
};

struct atmel_pwm_config {
	u32 period_bits;
};

struct atmel_pwm_data {
	struct atmel_pwm_registers regs;
	struct atmel_pwm_config cfg;
};

struct atmel_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
	const struct atmel_pwm_data *data;

	/*
	 * The hardware supports a mechanism to update a channel's duty cycle at
	 * the end of the currently running period. When such an update is
	 * pending we delay disabling the PWM until the new configuration is
	 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
	 * might not result in an inactive output.
	 * This bitmask tracks for which channels an update is pending in
	 * hardware.
	 */
	u32 update_pending;

	/* Protects .update_pending */
	spinlock_t lock;
};

static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct atmel_pwm_chip, chip);
}

static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
				  unsigned long offset)
{
	return readl_relaxed(chip->base + offset);
}

static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
				    unsigned long offset, unsigned long val)
{
	writel_relaxed(val, chip->base + offset);
}

static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
				     unsigned int ch, unsigned long offset)
{
	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;

	return atmel_pwm_readl(chip, base + offset);
}

static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
				       unsigned int ch, unsigned long offset,
				       unsigned long val)
{
	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;

	atmel_pwm_writel(chip, base + offset, val);
}

static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
{
	/*
	 * Each channel that has its bit in ISR set started a new period since
	 * ISR was cleared and so there is no more update pending.  Note that
	 * reading ISR clears it, so this needs to handle all channels to not
	 * loose information.
	 */
	u32 isr = atmel_pwm_readl(chip, PWM_ISR);

	chip->update_pending &= ~isr;
}

static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
{
	spin_lock(&chip->lock);

	/*
	 * Clear pending flags in hardware because otherwise there might still
	 * be a stale flag in ISR.
	 */
	atmel_pwm_update_pending(chip);

	chip->update_pending |= (1 << ch);

	spin_unlock(&chip->lock);
}

static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
{
	int ret = 0;

	spin_lock(&chip->lock);

	if (chip->update_pending & (1 << ch)) {
		atmel_pwm_update_pending(chip);

		if (chip->update_pending & (1 << ch))
			ret = 1;
	}

	spin_unlock(&chip->lock);

	return ret;
}

static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
{
	unsigned long timeout = jiffies + 2 * HZ;
	int ret;

	while ((ret = atmel_pwm_test_pending(chip, ch)) &&
	       time_before(jiffies, timeout))
		usleep_range(10, 100);

	return ret ? -ETIMEDOUT : 0;
}

static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
					     unsigned long clkrate,
					     const struct pwm_state *state,
					     unsigned long *cprd, u32 *pres)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	unsigned long long cycles = state->period;
	int shift;

	/* Calculate the period cycles and prescale value */
	cycles *= clkrate;
	do_div(cycles, NSEC_PER_SEC);

	/*
	 * The register for the period length is cfg.period_bits bits wide.
	 * So for each bit the number of clock cycles is wider divide the input
	 * clock frequency by two using pres and shift cprd accordingly.
	 */
	shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;

	if (shift > PWM_MAX_PRES) {
		dev_err(chip->dev, "pres exceeds the maximum value\n");
		return -EINVAL;
	} else if (shift > 0) {
		*pres = shift;
		cycles >>= *pres;
	} else {
		*pres = 0;
	}

	*cprd = cycles;

	return 0;
}

static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
				     unsigned long clkrate, unsigned long cprd,
				     u32 pres, unsigned long *cdty)
{
	unsigned long long cycles = state->duty_cycle;

	cycles *= clkrate;
	do_div(cycles, NSEC_PER_SEC);
	cycles >>= pres;
	*cdty = cprd - cycles;
}

static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
				  unsigned long cdty)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	u32 val;

	if (atmel_pwm->data->regs.duty_upd ==
	    atmel_pwm->data->regs.period_upd) {
		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
		val &= ~PWM_CMR_UPD_CDTY;
		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
	}

	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.duty_upd, cdty);
	atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
}

static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
				    struct pwm_device *pwm,
				    unsigned long cprd, unsigned long cdty)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);

	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.duty, cdty);
	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
			    atmel_pwm->data->regs.period, cprd);
}

static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
			      bool disable_clk)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	unsigned long timeout;

	atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);

	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);

	/*
	 * Wait for the PWM channel disable operation to be effective before
	 * stopping the clock.
	 */
	timeout = jiffies + 2 * HZ;

	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
	       time_before(jiffies, timeout))
		usleep_range(10, 100);

	if (disable_clk)
		clk_disable(atmel_pwm->clk);
}

static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	struct pwm_state cstate;
	unsigned long cprd, cdty;
	u32 pres, val;
	int ret;

	pwm_get_state(pwm, &cstate);

	if (state->enabled) {
		unsigned long clkrate = clk_get_rate(atmel_pwm->clk);

		if (cstate.enabled &&
		    cstate.polarity == state->polarity &&
		    cstate.period == state->period) {
			u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);

			cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
						  atmel_pwm->data->regs.period);
			pres = cmr & PWM_CMR_CPRE_MSK;

			atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
			atmel_pwm_update_cdty(chip, pwm, cdty);
			return 0;
		}

		ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
							&pres);
		if (ret) {
			dev_err(chip->dev,
				"failed to calculate cprd and prescaler\n");
			return ret;
		}

		atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);

		if (cstate.enabled) {
			atmel_pwm_disable(chip, pwm, false);
		} else {
			ret = clk_enable(atmel_pwm->clk);
			if (ret) {
				dev_err(chip->dev, "failed to enable clock\n");
				return ret;
			}
		}

		/* It is necessary to preserve CPOL, inside CMR */
		val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
		val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
		if (state->polarity == PWM_POLARITY_NORMAL)
			val &= ~PWM_CMR_CPOL;
		else
			val |= PWM_CMR_CPOL;
		atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
		atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
		atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
	} else if (cstate.enabled) {
		atmel_pwm_disable(chip, pwm, true);
	}

	return 0;
}

static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				struct pwm_state *state)
{
	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	u32 sr, cmr;

	sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
	cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);

	if (sr & (1 << pwm->hwpwm)) {
		unsigned long rate = clk_get_rate(atmel_pwm->clk);
		u32 cdty, cprd, pres;
		u64 tmp;

		pres = cmr & PWM_CMR_CPRE_MSK;

		cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
					  atmel_pwm->data->regs.period);
		tmp = (u64)cprd * NSEC_PER_SEC;
		tmp <<= pres;
		state->period = DIV64_U64_ROUND_UP(tmp, rate);

		/* Wait for an updated duty_cycle queued in hardware */
		atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);

		cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
					  atmel_pwm->data->regs.duty);
		tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
		tmp <<= pres;
		state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);

		state->enabled = true;
	} else {
		state->enabled = false;
	}

	if (cmr & PWM_CMR_CPOL)
		state->polarity = PWM_POLARITY_INVERSED;
	else
		state->polarity = PWM_POLARITY_NORMAL;
}

static const struct pwm_ops atmel_pwm_ops = {
	.apply = atmel_pwm_apply,
	.get_state = atmel_pwm_get_state,
	.owner = THIS_MODULE,
};

static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
	.regs = {
		.period		= PWMV1_CPRD,
		.period_upd	= PWMV1_CUPD,
		.duty		= PWMV1_CDTY,
		.duty_upd	= PWMV1_CUPD,
	},
	.cfg = {
		/* 16 bits to keep period and duty. */
		.period_bits	= 16,
	},
};

static const struct atmel_pwm_data atmel_sama5_pwm_data = {
	.regs = {
		.period		= PWMV2_CPRD,
		.period_upd	= PWMV2_CPRDUPD,
		.duty		= PWMV2_CDTY,
		.duty_upd	= PWMV2_CDTYUPD,
	},
	.cfg = {
		/* 16 bits to keep period and duty. */
		.period_bits	= 16,
	},
};

static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
	.regs = {
		.period		= PWMV1_CPRD,
		.period_upd	= PWMV1_CUPD,
		.duty		= PWMV1_CDTY,
		.duty_upd	= PWMV1_CUPD,
	},
	.cfg = {
		/* 32 bits to keep period and duty. */
		.period_bits	= 32,
	},
};

static const struct of_device_id atmel_pwm_dt_ids[] = {
	{
		.compatible = "atmel,at91sam9rl-pwm",
		.data = &atmel_sam9rl_pwm_data,
	}, {
		.compatible = "atmel,sama5d3-pwm",
		.data = &atmel_sama5_pwm_data,
	}, {
		.compatible = "atmel,sama5d2-pwm",
		.data = &atmel_sama5_pwm_data,
	}, {
		.compatible = "microchip,sam9x60-pwm",
		.data = &mchp_sam9x60_pwm_data,
	}, {
		/* sentinel */
	},
};
MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);

static int atmel_pwm_probe(struct platform_device *pdev)
{
	struct atmel_pwm_chip *atmel_pwm;
	int ret;

	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
	if (!atmel_pwm)
		return -ENOMEM;

	atmel_pwm->data = of_device_get_match_data(&pdev->dev);

	atmel_pwm->update_pending = 0;
	spin_lock_init(&atmel_pwm->lock);

	atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(atmel_pwm->base))
		return PTR_ERR(atmel_pwm->base);

	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(atmel_pwm->clk))
		return PTR_ERR(atmel_pwm->clk);

	ret = clk_prepare(atmel_pwm->clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to prepare PWM clock\n");
		return ret;
	}

	atmel_pwm->chip.dev = &pdev->dev;
	atmel_pwm->chip.ops = &atmel_pwm_ops;
	atmel_pwm->chip.npwm = 4;

	ret = pwmchip_add(&atmel_pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
		goto unprepare_clk;
	}

	platform_set_drvdata(pdev, atmel_pwm);

	return ret;

unprepare_clk:
	clk_unprepare(atmel_pwm->clk);
	return ret;
}

static int atmel_pwm_remove(struct platform_device *pdev)
{
	struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);

	pwmchip_remove(&atmel_pwm->chip);

	clk_unprepare(atmel_pwm->clk);

	return 0;
}

static struct platform_driver atmel_pwm_driver = {
	.driver = {
		.name = "atmel-pwm",
		.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
	},
	.probe = atmel_pwm_probe,
	.remove = atmel_pwm_remove,
};
module_platform_driver(atmel_pwm_driver);

MODULE_ALIAS("platform:atmel-pwm");
MODULE_AUTHOR("Bo Shen <[email protected]>");
MODULE_DESCRIPTION("Atmel PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f50a7f3d	1	// SPDX-License-Identifier: GPL-2.0-only
32b16d46 BS	2	/*
	3	* Driver for Atmel Pulse Width Modulation Controller
	4	*
	5	* Copyright (C) 2013 Atmel Corporation
	6	* Bo Shen <[email protected]>
3c269ba6 UKK	7	*
	8	* Links to reference manuals for the supported PWM chips can be found in
	9	* Documentation/arm/microchip.rst.
998d189a UKK	10	*
	11	* Limitations:
	12	* - Periods start with the inactive level.
	13	* - Hardware has to be stopped in general to update settings.
	14	*
	15	* Software bugs/possible improvements:
	16	* - When atmel_pwm_apply() is called with state->enabled=false a change in
	17	* state->polarity isn't honored.
	18	* - Instead of sleeping to wait for a completed period, the interrupt
	19	* functionality could be used.
32b16d46 BS	20	*/
	21
	22	#include <linux/clk.h>
472ac3dc	23	#include <linux/delay.h>
32b16d46 BS	24	#include <linux/err.h>
	25	#include <linux/io.h>
	26	#include <linux/module.h>
	27	#include <linux/of.h>
	28	#include <linux/of_device.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/pwm.h>
	31	#include <linux/slab.h>
	32
	33	/* The following is global registers for PWM controller */
	34	#define PWM_ENA 0x04
	35	#define PWM_DIS 0x08
	36	#define PWM_SR 0x0C
472ac3dc	37	#define PWM_ISR 0x1C
32b16d46 BS	38	/* Bit field in SR */
	39	#define PWM_SR_ALL_CH_ON 0x0F
	40
	41	/* The following register is PWM channel related registers */
	42	#define PWM_CH_REG_OFFSET 0x200
	43	#define PWM_CH_REG_SIZE 0x20
	44
	45	#define PWM_CMR 0x0
	46	/* Bit field in CMR */
	47	#define PWM_CMR_CPOL (1 << 9)
	48	#define PWM_CMR_UPD_CDTY (1 << 10)
8db9e29f	49	#define PWM_CMR_CPRE_MSK 0xF
32b16d46 BS	50
	51	/* The following registers for PWM v1 */
	52	#define PWMV1_CDTY 0x04
	53	#define PWMV1_CPRD 0x08
	54	#define PWMV1_CUPD 0x10
	55
	56	/* The following registers for PWM v2 */
	57	#define PWMV2_CDTY 0x04
	58	#define PWMV2_CDTYUPD 0x08
	59	#define PWMV2_CPRD 0x0C
	60	#define PWMV2_CPRDUPD 0x10
	61
ff55e7a3 UKK	62	#define PWM_MAX_PRES 10
ff55e7a3 UKK	63
1a722aad CB	64	struct atmel_pwm_registers {
	65	u8 period;
	66	u8 period_upd;
	67	u8 duty;
	68	u8 duty_upd;
	69	};
	70
0285827d	71	struct atmel_pwm_config {
2101c878	72	u32 period_bits;
0285827d CB	73	};
0285827d CB	74
53784159 CB	75	struct atmel_pwm_data {
53784159 CB	76	struct atmel_pwm_registers regs;
0285827d	77	struct atmel_pwm_config cfg;
53784159 CB	78	};
53784159 CB	79
32b16d46 BS	80	struct atmel_pwm_chip {
	81	struct pwm_chip chip;
	82	struct clk *clk;
	83	void __iomem *base;
53784159	84	const struct atmel_pwm_data *data;
32b16d46	85
52eaba4c UKK	86	/*
	87	* The hardware supports a mechanism to update a channel's duty cycle at
	88	* the end of the currently running period. When such an update is
	89	* pending we delay disabling the PWM until the new configuration is
	90	* active because otherwise pmw_config(duty_cycle=0); pwm_disable();
	91	* might not result in an inactive output.
	92	* This bitmask tracks for which channels an update is pending in
	93	* hardware.
	94	*/
	95	u32 update_pending;
	96
	97	/* Protects .update_pending */
	98	spinlock_t lock;
32b16d46 BS	99	};
	100
	101	static inline struct atmel_pwm_chip to_atmel_pwm_chip(struct pwm_chip chip)
	102	{
	103	return container_of(chip, struct atmel_pwm_chip, chip);
	104	}
	105
	106	static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
	107	unsigned long offset)
	108	{
	109	return readl_relaxed(chip->base + offset);
	110	}
	111
	112	static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
	113	unsigned long offset, unsigned long val)
	114	{
	115	writel_relaxed(val, chip->base + offset);
	116	}
	117
	118	static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
	119	unsigned int ch, unsigned long offset)
	120	{
	121	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
	122
02afb811	123	return atmel_pwm_readl(chip, base + offset);
32b16d46 BS	124	}
	125
	126	static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
	127	unsigned int ch, unsigned long offset,
	128	unsigned long val)
	129	{
	130	unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
	131
02afb811	132	atmel_pwm_writel(chip, base + offset, val);
32b16d46 BS	133	}
32b16d46 BS	134
52eaba4c UKK	135	static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
	136	{
	137	/*
	138	* Each channel that has its bit in ISR set started a new period since
	139	* ISR was cleared and so there is no more update pending. Note that
	140	* reading ISR clears it, so this needs to handle all channels to not
	141	* loose information.
	142	*/
	143	u32 isr = atmel_pwm_readl(chip, PWM_ISR);
	144
	145	chip->update_pending &= ~isr;
	146	}
	147
	148	static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
	149	{
	150	spin_lock(&chip->lock);
	151
	152	/*
	153	* Clear pending flags in hardware because otherwise there might still
	154	* be a stale flag in ISR.
	155	*/
	156	atmel_pwm_update_pending(chip);
	157
	158	chip->update_pending \|= (1 << ch);
	159
	160	spin_unlock(&chip->lock);
	161	}
	162
	163	static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
	164	{
	165	int ret = 0;
	166
	167	spin_lock(&chip->lock);
	168
	169	if (chip->update_pending & (1 << ch)) {
	170	atmel_pwm_update_pending(chip);
	171
	172	if (chip->update_pending & (1 << ch))
	173	ret = 1;
	174	}
	175
	176	spin_unlock(&chip->lock);
	177
	178	return ret;
	179	}
	180
	181	static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
	182	{
	183	unsigned long timeout = jiffies + 2 * HZ;
	184	int ret;
	185
	186	while ((ret = atmel_pwm_test_pending(chip, ch)) &&
	187	time_before(jiffies, timeout))
	188	usleep_range(10, 100);
	189
	190	return ret ? -ETIMEDOUT : 0;
	191	}
	192
1a722aad	193	static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
8035e6c6	194	unsigned long clkrate,
1a722aad CB	195	const struct pwm_state *state,
1a722aad CB	196	unsigned long cprd, u32 pres)
32b16d46 BS	197	{
32b16d46 BS	198	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
1a722aad	199	unsigned long long cycles = state->period;
2101c878	200	int shift;
32b16d46	201
e2e08970	202	/* Calculate the period cycles and prescale value */
8035e6c6	203	cycles *= clkrate;
1a722aad	204	do_div(cycles, NSEC_PER_SEC);
32b16d46	205
2101c878 UKK	206	/*
	207	* The register for the period length is cfg.period_bits bits wide.
	208	* So for each bit the number of clock cycles is wider divide the input
	209	* clock frequency by two using pres and shift cprd accordingly.
	210	*/
	211	shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
e2e08970	212
2101c878	213	if (shift > PWM_MAX_PRES) {
e2e08970 NV	214	dev_err(chip->dev, "pres exceeds the maximum value\n");
e2e08970 NV	215	return -EINVAL;
2101c878 UKK	216	} else if (shift > 0) {
	217	*pres = shift;
	218	cycles >>= *pres;
	219	} else {
	220	*pres = 0;
32b16d46 BS	221	}
32b16d46 BS	222
1a722aad	223	*cprd = cycles;
32b16d46	224
1a722aad	225	return 0;
32b16d46 BS	226	}
32b16d46 BS	227
1a722aad	228	static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
8035e6c6 UKK	229	unsigned long clkrate, unsigned long cprd,
8035e6c6 UKK	230	u32 pres, unsigned long *cdty)
32b16d46	231	{
1a722aad	232	unsigned long long cycles = state->duty_cycle;
32b16d46	233
8035e6c6 UKK	234	cycles *= clkrate;
	235	do_div(cycles, NSEC_PER_SEC);
	236	cycles >>= pres;
1a722aad	237	*cdty = cprd - cycles;
32b16d46 BS	238	}
32b16d46 BS	239
1a722aad CB	240	static void atmel_pwm_update_cdty(struct pwm_chip chip, struct pwm_device pwm,
1a722aad CB	241	unsigned long cdty)
32b16d46 BS	242	{
	243	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	244	u32 val;
32b16d46	245
53784159 CB	246	if (atmel_pwm->data->regs.duty_upd ==
53784159 CB	247	atmel_pwm->data->regs.period_upd) {
1a722aad CB	248	val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
	249	val &= ~PWM_CMR_UPD_CDTY;
	250	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
32b16d46 BS	251	}
32b16d46 BS	252
1a722aad	253	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	254	atmel_pwm->data->regs.duty_upd, cdty);
52eaba4c	255	atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
32b16d46 BS	256	}
32b16d46 BS	257
1a722aad CB	258	static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
	259	struct pwm_device *pwm,
	260	unsigned long cprd, unsigned long cdty)
32b16d46 BS	261	{
32b16d46 BS	262	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
32b16d46	263
1a722aad	264	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	265	atmel_pwm->data->regs.duty, cdty);
1a722aad	266	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
53784159	267	atmel_pwm->data->regs.period, cprd);
32b16d46 BS	268	}
32b16d46 BS	269
1a722aad CB	270	static void atmel_pwm_disable(struct pwm_chip chip, struct pwm_device pwm,
1a722aad CB	271	bool disable_clk)
32b16d46 BS	272	{
32b16d46 BS	273	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
dc1adb3c	274	unsigned long timeout;
472ac3dc	275
52eaba4c	276	atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
32b16d46 BS	277
	278	atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
	279
f718c54c GR	280	/*
	281	* Wait for the PWM channel disable operation to be effective before
	282	* stopping the clock.
	283	*/
	284	timeout = jiffies + 2 * HZ;
	285
	286	while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
	287	time_before(jiffies, timeout))
	288	usleep_range(10, 100);
	289
1a722aad CB	290	if (disable_clk)
	291	clk_disable(atmel_pwm->clk);
	292	}
	293
	294	static int atmel_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	295	const struct pwm_state *state)
1a722aad CB	296	{
	297	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	298	struct pwm_state cstate;
	299	unsigned long cprd, cdty;
	300	u32 pres, val;
	301	int ret;
	302
	303	pwm_get_state(pwm, &cstate);
	304
	305	if (state->enabled) {
8035e6c6 UKK	306	unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
8035e6c6 UKK	307
1a722aad CB	308	if (cstate.enabled &&
	309	cstate.polarity == state->polarity &&
	310	cstate.period == state->period) {
8035e6c6 UKK	311	u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
8035e6c6 UKK	312
1a722aad	313	cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
53784159	314	atmel_pwm->data->regs.period);
8035e6c6 UKK	315	pres = cmr & PWM_CMR_CPRE_MSK;
	316
	317	atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
1a722aad CB	318	atmel_pwm_update_cdty(chip, pwm, cdty);
	319	return 0;
	320	}
	321
8035e6c6	322	ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
1a722aad CB	323	&pres);
	324	if (ret) {
	325	dev_err(chip->dev,
	326	"failed to calculate cprd and prescaler\n");
	327	return ret;
	328	}
	329
8035e6c6	330	atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
1a722aad CB	331
	332	if (cstate.enabled) {
	333	atmel_pwm_disable(chip, pwm, false);
	334	} else {
	335	ret = clk_enable(atmel_pwm->clk);
	336	if (ret) {
	337	dev_err(chip->dev, "failed to enable clock\n");
	338	return ret;
	339	}
	340	}
	341
	342	/* It is necessary to preserve CPOL, inside CMR */
	343	val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
	344	val = (val & ~PWM_CMR_CPRE_MSK) \| (pres & PWM_CMR_CPRE_MSK);
	345	if (state->polarity == PWM_POLARITY_NORMAL)
	346	val &= ~PWM_CMR_CPOL;
	347	else
	348	val \|= PWM_CMR_CPOL;
	349	atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
	350	atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
1a722aad CB	351	atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
	352	} else if (cstate.enabled) {
	353	atmel_pwm_disable(chip, pwm, true);
	354	}
	355
	356	return 0;
32b16d46 BS	357	}
32b16d46 BS	358
651b510a UKK	359	static void atmel_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
	360	struct pwm_state *state)
	361	{
	362	struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
	363	u32 sr, cmr;
	364
	365	sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
	366	cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
	367
	368	if (sr & (1 << pwm->hwpwm)) {
	369	unsigned long rate = clk_get_rate(atmel_pwm->clk);
	370	u32 cdty, cprd, pres;
	371	u64 tmp;
	372
	373	pres = cmr & PWM_CMR_CPRE_MSK;
	374
	375	cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
	376	atmel_pwm->data->regs.period);
	377	tmp = (u64)cprd * NSEC_PER_SEC;
	378	tmp <<= pres;
	379	state->period = DIV64_U64_ROUND_UP(tmp, rate);
	380
52eaba4c UKK	381	/* Wait for an updated duty_cycle queued in hardware */
	382	atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
	383
651b510a UKK	384	cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
651b510a UKK	385	atmel_pwm->data->regs.duty);
453e8b3d	386	tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
651b510a UKK	387	tmp <<= pres;
	388	state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
	389
	390	state->enabled = true;
	391	} else {
	392	state->enabled = false;
	393	}
	394
	395	if (cmr & PWM_CMR_CPOL)
	396	state->polarity = PWM_POLARITY_INVERSED;
	397	else
	398	state->polarity = PWM_POLARITY_NORMAL;
	399	}
	400
32b16d46	401	static const struct pwm_ops atmel_pwm_ops = {
1a722aad	402	.apply = atmel_pwm_apply,
651b510a	403	.get_state = atmel_pwm_get_state,
32b16d46 BS	404	.owner = THIS_MODULE,
	405	};
	406
abcbe373	407	static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
53784159 CB	408	.regs = {
	409	.period = PWMV1_CPRD,
	410	.period_upd = PWMV1_CUPD,
	411	.duty = PWMV1_CDTY,
	412	.duty_upd = PWMV1_CUPD,
	413	},
0285827d CB	414	.cfg = {
0285827d CB	415	/* 16 bits to keep period and duty. */
2101c878	416	.period_bits = 16,
0285827d	417	},
32b16d46 BS	418	};
32b16d46 BS	419
abcbe373	420	static const struct atmel_pwm_data atmel_sama5_pwm_data = {
53784159 CB	421	.regs = {
	422	.period = PWMV2_CPRD,
	423	.period_upd = PWMV2_CPRDUPD,
	424	.duty = PWMV2_CDTY,
	425	.duty_upd = PWMV2_CDTYUPD,
	426	},
0285827d CB	427	.cfg = {
0285827d CB	428	/* 16 bits to keep period and duty. */
2101c878	429	.period_bits = 16,
0285827d	430	},
32b16d46 BS	431	};
32b16d46 BS	432
74d0c3b2 CB	433	static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
	434	.regs = {
	435	.period = PWMV1_CPRD,
	436	.period_upd = PWMV1_CUPD,
	437	.duty = PWMV1_CDTY,
	438	.duty_upd = PWMV1_CUPD,
	439	},
	440	.cfg = {
	441	/* 32 bits to keep period and duty. */
2101c878	442	.period_bits = 32,
74d0c3b2 CB	443	},
	444	};
	445
32b16d46 BS	446	static const struct of_device_id atmel_pwm_dt_ids[] = {
	447	{
	448	.compatible = "atmel,at91sam9rl-pwm",
abcbe373	449	.data = &atmel_sam9rl_pwm_data,
32b16d46 BS	450	}, {
32b16d46 BS	451	.compatible = "atmel,sama5d3-pwm",
abcbe373	452	.data = &atmel_sama5_pwm_data,
44521afa CB	453	}, {
44521afa CB	454	.compatible = "atmel,sama5d2-pwm",
abcbe373	455	.data = &atmel_sama5_pwm_data,
74d0c3b2 CB	456	}, {
	457	.compatible = "microchip,sam9x60-pwm",
	458	.data = &mchp_sam9x60_pwm_data,
32b16d46 BS	459	}, {
	460	/* sentinel */
	461	},
	462	};
	463	MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
	464
32b16d46 BS	465	static int atmel_pwm_probe(struct platform_device *pdev)
32b16d46 BS	466	{
32b16d46	467	struct atmel_pwm_chip *atmel_pwm;
32b16d46 BS	468	int ret;
32b16d46 BS	469
32b16d46 BS	470	atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
	471	if (!atmel_pwm)
	472	return -ENOMEM;
	473
d85b9ce1	474	atmel_pwm->data = of_device_get_match_data(&pdev->dev);
52eaba4c UKK	475
	476	atmel_pwm->update_pending = 0;
	477	spin_lock_init(&atmel_pwm->lock);
d85b9ce1	478
accef074	479	atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
32b16d46 BS	480	if (IS_ERR(atmel_pwm->base))
	481	return PTR_ERR(atmel_pwm->base);
	482
	483	atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
	484	if (IS_ERR(atmel_pwm->clk))
	485	return PTR_ERR(atmel_pwm->clk);
	486
	487	ret = clk_prepare(atmel_pwm->clk);
	488	if (ret) {
	489	dev_err(&pdev->dev, "failed to prepare PWM clock\n");
	490	return ret;
	491	}
	492
	493	atmel_pwm->chip.dev = &pdev->dev;
	494	atmel_pwm->chip.ops = &atmel_pwm_ops;
32b16d46	495	atmel_pwm->chip.npwm = 4;
32b16d46 BS	496
	497	ret = pwmchip_add(&atmel_pwm->chip);
	498	if (ret < 0) {
	499	dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
	500	goto unprepare_clk;
	501	}
	502
	503	platform_set_drvdata(pdev, atmel_pwm);
	504
6a683356 BS	505	return ret;
6a683356 BS	506
32b16d46 BS	507	unprepare_clk:
	508	clk_unprepare(atmel_pwm->clk);
	509	return ret;
	510	}
	511
	512	static int atmel_pwm_remove(struct platform_device *pdev)
	513	{
	514	struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
	515
89c6f314 UKK	516	pwmchip_remove(&atmel_pwm->chip);
89c6f314 UKK	517
32b16d46 BS	518	clk_unprepare(atmel_pwm->clk);
32b16d46 BS	519
89c6f314	520	return 0;
32b16d46 BS	521	}
	522
	523	static struct platform_driver atmel_pwm_driver = {
	524	.driver = {
	525	.name = "atmel-pwm",
	526	.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
	527	},
32b16d46 BS	528	.probe = atmel_pwm_probe,
	529	.remove = atmel_pwm_remove,
	530	};
	531	module_platform_driver(atmel_pwm_driver);
	532
	533	MODULE_ALIAS("platform:atmel-pwm");
	534	MODULE_AUTHOR("Bo Shen <[email protected]>");
	535	MODULE_DESCRIPTION("Atmel PWM driver");
	536	MODULE_LICENSE("GPL v2");