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Commit | Line | Data |
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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
eed6b3eb OJ |
2 | menu "Platform selection" |
3 | ||
c88cc3ee AF |
4 | config ARCH_ACTIONS |
5 | bool "Actions Semi Platforms" | |
6 | select OWL_TIMER | |
e0c27a10 | 7 | select PINCTRL |
c88cc3ee AF |
8 | help |
9 | This enables support for the Actions Semiconductor S900 SoC family. | |
10 | ||
4b36daf9 DN |
11 | config ARCH_AGILEX |
12 | bool "Intel's Agilex SoCFPGA Family" | |
13 | help | |
14 | This enables support for Intel's Agilex SoCFPGA Family. | |
15 | ||
ce3dd55b AP |
16 | config ARCH_SUNXI |
17 | bool "Allwinner sunxi 64-bit SoC Family" | |
900a9020 | 18 | select ARCH_HAS_RESET_CONTROLLER |
23485482 | 19 | select GENERIC_IRQ_CHIP |
d229d205 | 20 | select PINCTRL |
900a9020 | 21 | select RESET_CONTROLLER |
ce3dd55b AP |
22 | help |
23 | This enables support for Allwinner sunxi based SoCs like the A64. | |
24 | ||
e2f0abaf AT |
25 | config ARCH_ALPINE |
26 | bool "Annapurna Labs Alpine platform" | |
5a3f75a4 | 27 | select ALPINE_MSI if PCI |
e2f0abaf AT |
28 | help |
29 | This enables support for the Annapurna Labs Alpine | |
30 | Soc family. | |
31 | ||
628d30d1 EA |
32 | config ARCH_BCM2835 |
33 | bool "Broadcom BCM2835 family" | |
bb0eb050 | 34 | select TIMER_OF |
da9a1c67 | 35 | select GPIOLIB |
7a9b6be9 | 36 | select MFD_CORE |
628d30d1 EA |
37 | select PINCTRL |
38 | select PINCTRL_BCM2835 | |
39 | select ARM_AMBA | |
781fa0a9 | 40 | select ARM_GIC |
628d30d1 | 41 | select ARM_TIMER_SP804 |
628d30d1 | 42 | help |
781fa0a9 SW |
43 | This enables support for the Broadcom BCM2837 and BCM2711 SoC. |
44 | These SoCs are used in the Raspberry Pi 3 and 4 devices. | |
628d30d1 | 45 | |
36b7c583 RJ |
46 | config ARCH_BCM_IPROC |
47 | bool "Broadcom iProc SoC Family" | |
382618bb | 48 | select COMMON_CLK_IPROC |
da9a1c67 | 49 | select GPIOLIB |
382618bb | 50 | select PINCTRL |
36b7c583 RJ |
51 | help |
52 | This enables support for Broadcom iProc based SoCs | |
53 | ||
dd40fd92 JZ |
54 | config ARCH_BERLIN |
55 | bool "Marvell Berlin SoC Family" | |
56 | select DW_APB_ICTL | |
b0fc70ce | 57 | select DW_APB_TIMER_OF |
da9a1c67 | 58 | select GPIOLIB |
75d8e1ba | 59 | select PINCTRL |
dd40fd92 JZ |
60 | help |
61 | This enables support for Marvell Berlin SoC Family | |
62 | ||
ea367d38 MS |
63 | config ARCH_BITMAIN |
64 | bool "Bitmain SoC Platforms" | |
65 | help | |
66 | This enables support for the Bitmain SoC Family. | |
67 | ||
37eb56dc FF |
68 | config ARCH_BRCMSTB |
69 | bool "Broadcom Set-Top-Box SoCs" | |
809eec69 | 70 | select ARCH_HAS_RESET_CONTROLLER |
bf0349df | 71 | select BCM7038_L1_IRQ |
37eb56dc FF |
72 | select BRCMSTB_L2_IRQ |
73 | select GENERIC_IRQ_CHIP | |
724cf0ae | 74 | select PINCTRL |
37eb56dc FF |
75 | help |
76 | This enables support for Broadcom's ARMv8 Set Top Box SoCs | |
77 | ||
eed6b3eb | 78 | config ARCH_EXYNOS |
c87b3e97 | 79 | bool "ARMv8 based Samsung Exynos SoC family" |
eed6b3eb | 80 | select COMMON_CLK_SAMSUNG |
a6fe8c77 | 81 | select EXYNOS_CHIPID |
caab3df9 KK |
82 | select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS |
83 | select EXYNOS_PMU | |
eed6b3eb OJ |
84 | select HAVE_S3C_RTC if RTC_CLASS |
85 | select PINCTRL | |
86 | select PINCTRL_EXYNOS | |
5220a73a | 87 | select PM_GENERIC_DOMAINS if PM |
3b3428e3 | 88 | select SOC_SAMSUNG |
eed6b3eb | 89 | help |
c87b3e97 | 90 | This enables support for ARMv8 based Samsung Exynos SoC family. |
eed6b3eb | 91 | |
31a91c87 LP |
92 | config ARCH_SPARX5 |
93 | bool "ARMv8 based Microchip Sparx5 SoC family" | |
94 | select PINCTRL | |
95 | select DW_APB_TIMER_OF | |
96 | help | |
97 | This enables support for the Microchip Sparx5 ARMv8-based | |
98 | SoC family of TSN-capable gigabit switches. | |
99 | ||
100 | The SparX-5 Ethernet switch family provides a rich set of | |
101 | switching features such as advanced TCAM-based VLAN and QoS | |
102 | processing enabling delivery of differentiated services, and | |
103 | security through TCAM-based frame processing using versatile | |
104 | content aware processor (VCAP). | |
105 | ||
c7724572 NM |
106 | config ARCH_K3 |
107 | bool "Texas Instruments Inc. K3 multicore SoC architecture" | |
108 | select PM_GENERIC_DOMAINS if PM | |
009669e7 | 109 | select MAILBOX |
a6b112b0 | 110 | select SOC_TI |
009669e7 LV |
111 | select TI_MESSAGE_MANAGER |
112 | select TI_SCI_PROTOCOL | |
113 | select TI_SCI_INTR_IRQCHIP | |
114 | select TI_SCI_INTA_IRQCHIP | |
ec792ecf | 115 | select TI_K3_SOCINFO |
c7724572 NM |
116 | help |
117 | This enables support for Texas Instruments' K3 multicore SoC | |
118 | architecture. | |
119 | ||
53a5fde0 BS |
120 | config ARCH_LAYERSCAPE |
121 | bool "ARMv8 based Freescale Layerscape SoC family" | |
eeb3d68b | 122 | select EDAC_SUPPORT |
eed6b3eb | 123 | help |
53a5fde0 | 124 | This enables support for the Freescale Layerscape SoC family. |
eed6b3eb | 125 | |
198ed962 CM |
126 | config ARCH_LG1K |
127 | bool "LG Electronics LG1K SoC Family" | |
128 | help | |
129 | This enables support for LG Electronics LG1K SoC Family | |
130 | ||
eed6b3eb OJ |
131 | config ARCH_HISI |
132 | bool "Hisilicon SoC Family" | |
2b905d3a | 133 | select ARM_TIMER_SP804 |
f9db43bc | 134 | select HISILICON_IRQ_MBIGEN if PCI |
21adc4d7 | 135 | select PINCTRL |
eed6b3eb OJ |
136 | help |
137 | This enables support for Hisilicon ARMv8 SoC family | |
138 | ||
a6a4abf8 DA |
139 | config ARCH_KEEMBAY |
140 | bool "Keem Bay SoC" | |
141 | help | |
142 | This enables support for Intel Movidius SoC code-named Keem Bay. | |
143 | ||
eed6b3eb | 144 | config ARCH_MEDIATEK |
598f9b2e | 145 | bool "MediaTek SoC Family" |
eed6b3eb OJ |
146 | select ARM_GIC |
147 | select PINCTRL | |
c050b45d | 148 | select MTK_TIMER |
eed6b3eb | 149 | help |
598f9b2e SW |
150 | This enables support for MediaTek MT27xx, MT65xx, MT76xx |
151 | & MT81xx ARMv8 SoCs | |
eed6b3eb | 152 | |
451e9e54 AF |
153 | config ARCH_MESON |
154 | bool "Amlogic Platforms" | |
bf56c776 CC |
155 | select PINCTRL |
156 | select PINCTRL_MESON | |
59bdefe9 | 157 | select COMMON_CLK_GXBB |
78b4af31 | 158 | select COMMON_CLK_AXG |
b3077ffc | 159 | select COMMON_CLK_G12A |
f2c2122a | 160 | select MESON_IRQ_GPIO |
451e9e54 | 161 | help |
b3077ffc JB |
162 | This enables support for the arm64 based Amlogic SoCs |
163 | such as the s905, S905X/D, S912, A113X/D or S905X/D2 | |
451e9e54 | 164 | |
b4f596b1 GC |
165 | config ARCH_MVEBU |
166 | bool "Marvell EBU SoC Family" | |
ad87c0f6 TP |
167 | select ARMADA_AP806_SYSCON |
168 | select ARMADA_CP110_SYSCON | |
ff60d834 | 169 | select ARMADA_37XX_CLK |
d2718d13 GC |
170 | select GPIOLIB |
171 | select GPIOLIB_IRQCHIP | |
29ad6bd9 TP |
172 | select MVEBU_GICP |
173 | select MVEBU_ICU | |
b3920b2b | 174 | select MVEBU_ODMI |
04208a24 | 175 | select MVEBU_PIC |
228197c5 | 176 | select MVEBU_SEI |
d2718d13 GC |
177 | select OF_GPIO |
178 | select PINCTRL | |
179 | select PINCTRL_ARMADA_37XX | |
c4c14365 GC |
180 | select PINCTRL_ARMADA_AP806 |
181 | select PINCTRL_ARMADA_CP110 | |
b4f596b1 | 182 | help |
b3920b2b TP |
183 | This enables support for Marvell EBU familly, including: |
184 | - Armada 3700 SoC Family | |
185 | - Armada 7K SoC Family | |
186 | - Armada 8K SoC Family | |
b4f596b1 | 187 | |
930507c1 LS |
188 | config ARCH_MXC |
189 | bool "ARMv8 based NXP i.MX SoC family" | |
190 | select ARM64_ERRATUM_843419 | |
a29c7823 | 191 | select ARM64_ERRATUM_845719 if COMPAT |
67b92823 | 192 | select IMX_GPCV2 |
84a2ab25 LS |
193 | select IMX_GPCV2_PM_DOMAINS |
194 | select PM | |
195 | select PM_GENERIC_DOMAINS | |
fafaa0a2 | 196 | select SOC_BUS |
1991529f | 197 | select TIMER_IMX_SYS_CTR |
930507c1 LS |
198 | help |
199 | This enables support for the ARMv8 based SoCs in the | |
200 | NXP i.MX family. | |
201 | ||
eed6b3eb OJ |
202 | config ARCH_QCOM |
203 | bool "Qualcomm Platforms" | |
e19811a8 | 204 | select GPIOLIB |
eed6b3eb OJ |
205 | select PINCTRL |
206 | help | |
207 | This enables support for the ARMv8 based Qualcomm chipsets. | |
208 | ||
1b0d665e AF |
209 | config ARCH_REALTEK |
210 | bool "Realtek Platforms" | |
e3ca9556 | 211 | select RESET_CONTROLLER |
1b0d665e AF |
212 | help |
213 | This enables support for the ARMv8 based Realtek chipsets, | |
214 | like the RTD1295. | |
215 | ||
26a7e06d SH |
216 | config ARCH_RENESAS |
217 | bool "Renesas SoC Platforms" | |
9374eee3 | 218 | select GPIOLIB |
26a7e06d | 219 | select PINCTRL |
8d6799a9 | 220 | select SOC_BUS |
26a7e06d SH |
221 | help |
222 | This enables support for the ARMv8 based Renesas SoCs. | |
223 | ||
0964d660 GU |
224 | config ARCH_ROCKCHIP |
225 | bool "Rockchip Platforms" | |
226 | select ARCH_HAS_RESET_CONTROLLER | |
227 | select GPIOLIB | |
228 | select PINCTRL | |
229 | select PINCTRL_ROCKCHIP | |
230 | select PM | |
231 | select ROCKCHIP_TIMER | |
232 | help | |
233 | This enables support for the ARMv8 based Rockchip chipsets, | |
234 | like the RK3368. | |
235 | ||
3d4e0158 MM |
236 | config ARCH_S32 |
237 | bool "NXP S32 SoC Family" | |
238 | help | |
239 | This enables support for the NXP S32 family of processors. | |
240 | ||
0964d660 GU |
241 | config ARCH_SEATTLE |
242 | bool "AMD Seattle SoC Family" | |
243 | help | |
244 | This enables support for AMD Seattle SOC Family | |
245 | ||
78cd6a9d DN |
246 | config ARCH_STRATIX10 |
247 | bool "Altera's Stratix 10 SoCFPGA Family" | |
248 | help | |
249 | This enables support for Altera's Stratix 10 SoCFPGA Family. | |
250 | ||
0964d660 GU |
251 | config ARCH_SYNQUACER |
252 | bool "Socionext SynQuacer SoC Family" | |
253 | ||
eed6b3eb OJ |
254 | config ARCH_TEGRA |
255 | bool "NVIDIA Tegra SoC Family" | |
256 | select ARCH_HAS_RESET_CONTROLLER | |
2e988a83 | 257 | select ARM_GIC_PM |
eed6b3eb | 258 | select CLKSRC_MMIO |
bb0eb050 | 259 | select TIMER_OF |
eed6b3eb | 260 | select GENERIC_CLOCKEVENTS |
da9a1c67 | 261 | select GPIOLIB |
eed6b3eb | 262 | select PINCTRL |
98823241 JH |
263 | select PM |
264 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
265 | select RESET_CONTROLLER |
266 | help | |
267 | This enables support for the NVIDIA Tegra SoC family. | |
268 | ||
eed6b3eb | 269 | config ARCH_SPRD |
b5f73d47 | 270 | bool "Spreadtrum SoC platform" |
eed6b3eb OJ |
271 | help |
272 | Support for Spreadtrum ARM based SoCs | |
273 | ||
274 | config ARCH_THUNDER | |
275 | bool "Cavium Inc. Thunder SoC Family" | |
276 | help | |
277 | This enables support for Cavium's Thunder Family of SoCs. | |
278 | ||
03b6fd5d J |
279 | config ARCH_THUNDER2 |
280 | bool "Cavium ThunderX2 Server Processors" | |
281 | select GPIOLIB | |
282 | help | |
283 | This enables support for Cavium's ThunderX2 CN99XX family of | |
284 | server processors. | |
285 | ||
56aaafb6 MY |
286 | config ARCH_UNIPHIER |
287 | bool "Socionext UniPhier SoC Family" | |
75924903 | 288 | select ARCH_HAS_RESET_CONTROLLER |
56aaafb6 | 289 | select PINCTRL |
ab6ab445 | 290 | select RESET_CONTROLLER |
56aaafb6 MY |
291 | help |
292 | This enables support for Socionext UniPhier SoC family. | |
293 | ||
eed6b3eb OJ |
294 | config ARCH_VEXPRESS |
295 | bool "ARMv8 software model (Versatile Express)" | |
da9a1c67 | 296 | select GPIOLIB |
8da7cc08 SH |
297 | select PM |
298 | select PM_GENERIC_DOMAINS | |
eed6b3eb OJ |
299 | help |
300 | This enables support for the ARMv8 software model (Versatile | |
301 | Express). | |
302 | ||
0aa56c7e NI |
303 | config ARCH_VISCONTI |
304 | bool "Toshiba Visconti SoC Family" | |
305 | select PINCTRL | |
306 | select PINCTRL_VISCONTI | |
307 | help | |
308 | This enables support for Toshiba Visconti SoCs Family. | |
309 | ||
5bfb3889 | 310 | config ARCH_VULCAN |
a314520d | 311 | def_bool n |
5bfb3889 | 312 | |
eed6b3eb OJ |
313 | config ARCH_XGENE |
314 | bool "AppliedMicro X-Gene SOC Family" | |
315 | help | |
316 | This enables support for AppliedMicro X-Gene SOC Family | |
317 | ||
12496aea JN |
318 | config ARCH_ZX |
319 | bool "ZTE ZX SoC Family" | |
03d95c26 | 320 | select PINCTRL |
12496aea JN |
321 | help |
322 | This enables support for ZTE ZX SoC Family | |
323 | ||
eed6b3eb OJ |
324 | config ARCH_ZYNQMP |
325 | bool "Xilinx ZynqMP Family" | |
326 | help | |
327 | This enables support for Xilinx ZynqMP Family | |
328 | ||
329 | endmenu |