[linux.git] / drivers / pwm / pwm-sifive.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017-2018 SiFive
 * For SiFive's PWM IP block documentation please refer Chapter 14 of
 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
 *
 * Limitations:
 * - When changing both duty cycle and period, we cannot prevent in
 *   software that the output might produce a period with mixed
 *   settings (new period length and old duty cycle).
 * - The hardware cannot generate a 100% duty cycle.
 * - The hardware generates only inverted output.
 */
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/bitfield.h>

/* Register offsets */
#define PWM_SIFIVE_PWMCFG		0x0
#define PWM_SIFIVE_PWMCOUNT		0x8
#define PWM_SIFIVE_PWMS			0x10
#define PWM_SIFIVE_PWMCMP(i)		(0x20 + 4 * (i))

/* PWMCFG fields */
#define PWM_SIFIVE_PWMCFG_SCALE		GENMASK(3, 0)
#define PWM_SIFIVE_PWMCFG_STICKY	BIT(8)
#define PWM_SIFIVE_PWMCFG_ZERO_CMP	BIT(9)
#define PWM_SIFIVE_PWMCFG_DEGLITCH	BIT(10)
#define PWM_SIFIVE_PWMCFG_EN_ALWAYS	BIT(12)
#define PWM_SIFIVE_PWMCFG_EN_ONCE	BIT(13)
#define PWM_SIFIVE_PWMCFG_CENTER	BIT(16)
#define PWM_SIFIVE_PWMCFG_GANG		BIT(24)
#define PWM_SIFIVE_PWMCFG_IP		BIT(28)

#define PWM_SIFIVE_CMPWIDTH		16
#define PWM_SIFIVE_DEFAULT_PERIOD	10000000

struct pwm_sifive_ddata {
	struct pwm_chip	chip;
	struct mutex lock; /* lock to protect user_count and approx_period */
	struct notifier_block notifier;
	struct clk *clk;
	void __iomem *regs;
	unsigned int real_period;
	unsigned int approx_period;
	int user_count;
};

static inline
struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_sifive_ddata, chip);
}

static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);

	mutex_lock(&ddata->lock);
	ddata->user_count++;
	mutex_unlock(&ddata->lock);

	return 0;
}

static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);

	mutex_lock(&ddata->lock);
	ddata->user_count--;
	mutex_unlock(&ddata->lock);
}

/* Called holding ddata->lock */
static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
				    unsigned long rate)
{
	unsigned long long num;
	unsigned long scale_pow;
	int scale;
	u32 val;
	/*
	 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
	 * period length is using pwmscale which provides the number of bits the
	 * counter is shifted before being feed to the comparators. A period
	 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
	 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
	 */
	scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
	scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);

	val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
	      FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
	writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);

	/* As scale <= 15 the shift operation cannot overflow. */
	num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
	ddata->real_period = div64_ul(num, rate);
	dev_dbg(ddata->chip.dev,
		"New real_period = %u ns\n", ddata->real_period);
}

static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				struct pwm_state *state)
{
	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
	u32 duty, val;

	duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));

	state->enabled = duty > 0;

	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
	if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
		state->enabled = false;

	state->period = ddata->real_period;
	state->duty_cycle =
		(u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
	state->polarity = PWM_POLARITY_INVERSED;

	return 0;
}

static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			    const struct pwm_state *state)
{
	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
	struct pwm_state cur_state;
	unsigned int duty_cycle;
	unsigned long long num;
	bool enabled;
	int ret = 0;
	u32 frac;

	if (state->polarity != PWM_POLARITY_INVERSED)
		return -EINVAL;

	cur_state = pwm->state;
	enabled = cur_state.enabled;

	duty_cycle = state->duty_cycle;
	if (!state->enabled)
		duty_cycle = 0;

	/*
	 * The problem of output producing mixed setting as mentioned at top,
	 * occurs here. To minimize the window for this problem, we are
	 * calculating the register values first and then writing them
	 * consecutively
	 */
	num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
	frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
	/* The hardware cannot generate a 100% duty cycle */
	frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);

	mutex_lock(&ddata->lock);
	if (state->period != ddata->approx_period) {
		/*
		 * Don't let a 2nd user change the period underneath the 1st user.
		 * However if ddate->approx_period == 0 this is the first time we set
		 * any period, so let whoever gets here first set the period so other
		 * users who agree on the period won't fail.
		 */
		if (ddata->user_count != 1 && ddata->approx_period) {
			mutex_unlock(&ddata->lock);
			return -EBUSY;
		}
		ddata->approx_period = state->period;
		pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
	}
	mutex_unlock(&ddata->lock);

	/*
	 * If the PWM is enabled the clk is already on. So only enable it
	 * conditionally to have it on exactly once afterwards independent of
	 * the PWM state.
	 */
	if (!enabled) {
		ret = clk_enable(ddata->clk);
		if (ret) {
			dev_err(ddata->chip.dev, "Enable clk failed\n");
			return ret;
		}
	}

	writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));

	if (!state->enabled)
		clk_disable(ddata->clk);

	return 0;
}

static const struct pwm_ops pwm_sifive_ops = {
	.request = pwm_sifive_request,
	.free = pwm_sifive_free,
	.get_state = pwm_sifive_get_state,
	.apply = pwm_sifive_apply,
	.owner = THIS_MODULE,
};

static int pwm_sifive_clock_notifier(struct notifier_block *nb,
				     unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct pwm_sifive_ddata *ddata =
		container_of(nb, struct pwm_sifive_ddata, notifier);

	if (event == POST_RATE_CHANGE) {
		mutex_lock(&ddata->lock);
		pwm_sifive_update_clock(ddata, ndata->new_rate);
		mutex_unlock(&ddata->lock);
	}

	return NOTIFY_OK;
}

static int pwm_sifive_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct pwm_sifive_ddata *ddata;
	struct pwm_chip *chip;
	int ret;
	u32 val;
	unsigned int enabled_pwms = 0, enabled_clks = 1;

	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
	if (!ddata)
		return -ENOMEM;

	mutex_init(&ddata->lock);
	chip = &ddata->chip;
	chip->dev = dev;
	chip->ops = &pwm_sifive_ops;
	chip->npwm = 4;

	ddata->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(ddata->regs))
		return PTR_ERR(ddata->regs);

	ddata->clk = devm_clk_get_prepared(dev, NULL);
	if (IS_ERR(ddata->clk))
		return dev_err_probe(dev, PTR_ERR(ddata->clk),
				     "Unable to find controller clock\n");

	ret = clk_enable(ddata->clk);
	if (ret) {
		dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
		return ret;
	}

	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
	if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
		unsigned int i;

		for (i = 0; i < chip->npwm; ++i) {
			val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
			if (val > 0)
				++enabled_pwms;
		}
	}

	/* The clk should be on once for each running PWM. */
	if (enabled_pwms) {
		while (enabled_clks < enabled_pwms) {
			/* This is not expected to fail as the clk is already on */
			ret = clk_enable(ddata->clk);
			if (unlikely(ret)) {
				dev_err_probe(dev, ret, "Failed to enable clk\n");
				goto disable_clk;
			}
			++enabled_clks;
		}
	} else {
		clk_disable(ddata->clk);
		enabled_clks = 0;
	}

	/* Watch for changes to underlying clock frequency */
	ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
	ret = clk_notifier_register(ddata->clk, &ddata->notifier);
	if (ret) {
		dev_err(dev, "failed to register clock notifier: %d\n", ret);
		goto disable_clk;
	}

	ret = pwmchip_add(chip);
	if (ret < 0) {
		dev_err(dev, "cannot register PWM: %d\n", ret);
		goto unregister_clk;
	}

	platform_set_drvdata(pdev, ddata);
	dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);

	return 0;

unregister_clk:
	clk_notifier_unregister(ddata->clk, &ddata->notifier);
disable_clk:
	while (enabled_clks) {
		clk_disable(ddata->clk);
		--enabled_clks;
	}

	return ret;
}

static void pwm_sifive_remove(struct platform_device *dev)
{
	struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
	struct pwm_device *pwm;
	int ch;

	pwmchip_remove(&ddata->chip);
	clk_notifier_unregister(ddata->clk, &ddata->notifier);

	for (ch = 0; ch < ddata->chip.npwm; ch++) {
		pwm = &ddata->chip.pwms[ch];
		if (pwm->state.enabled)
			clk_disable(ddata->clk);
	}
}

static const struct of_device_id pwm_sifive_of_match[] = {
	{ .compatible = "sifive,pwm0" },
	{},
};
MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);

static struct platform_driver pwm_sifive_driver = {
	.probe = pwm_sifive_probe,
	.remove_new = pwm_sifive_remove,
	.driver = {
		.name = "pwm-sifive",
		.of_match_table = pwm_sifive_of_match,
	},
};
module_platform_driver(pwm_sifive_driver);

MODULE_DESCRIPTION("SiFive PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9e37a53e YS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2017-2018 SiFive
	4	* For SiFive's PWM IP block documentation please refer Chapter 14 of
	5	* Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
	6	*
	7	* Limitations:
	8	* - When changing both duty cycle and period, we cannot prevent in
	9	* software that the output might produce a period with mixed
	10	* settings (new period length and old duty cycle).
	11	* - The hardware cannot generate a 100% duty cycle.
	12	* - The hardware generates only inverted output.
	13	*/
	14	#include <linux/clk.h>
	15	#include <linux/io.h>
0a41b0c5	16	#include <linux/mod_devicetable.h>
9e37a53e YS	17	#include <linux/module.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/pwm.h>
	20	#include <linux/slab.h>
	21	#include <linux/bitfield.h>
	22
	23	/* Register offsets */
	24	#define PWM_SIFIVE_PWMCFG 0x0
	25	#define PWM_SIFIVE_PWMCOUNT 0x8
	26	#define PWM_SIFIVE_PWMS 0x10
20550a61	27	#define PWM_SIFIVE_PWMCMP(i) (0x20 + 4 * (i))
9e37a53e YS	28
	29	/* PWMCFG fields */
	30	#define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
	31	#define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
	32	#define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
	33	#define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
	34	#define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
	35	#define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
	36	#define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
	37	#define PWM_SIFIVE_PWMCFG_GANG BIT(24)
	38	#define PWM_SIFIVE_PWMCFG_IP BIT(28)
	39
9e37a53e YS	40	#define PWM_SIFIVE_CMPWIDTH 16
	41	#define PWM_SIFIVE_DEFAULT_PERIOD 10000000
	42
	43	struct pwm_sifive_ddata {
	44	struct pwm_chip chip;
0f02f491	45	struct mutex lock; /* lock to protect user_count and approx_period */
9e37a53e YS	46	struct notifier_block notifier;
	47	struct clk *clk;
	48	void __iomem *regs;
	49	unsigned int real_period;
	50	unsigned int approx_period;
	51	int user_count;
	52	};
	53
	54	static inline
daf3facb	55	struct pwm_sifive_ddata pwm_sifive_chip_to_ddata(struct pwm_chip chip)
9e37a53e	56	{
daf3facb	57	return container_of(chip, struct pwm_sifive_ddata, chip);
9e37a53e YS	58	}
	59
	60	static int pwm_sifive_request(struct pwm_chip chip, struct pwm_device pwm)
	61	{
	62	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
	63
	64	mutex_lock(&ddata->lock);
	65	ddata->user_count++;
	66	mutex_unlock(&ddata->lock);
	67
	68	return 0;
	69	}
	70
	71	static void pwm_sifive_free(struct pwm_chip chip, struct pwm_device pwm)
	72	{
	73	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
	74
	75	mutex_lock(&ddata->lock);
	76	ddata->user_count--;
	77	mutex_unlock(&ddata->lock);
	78	}
	79
0f02f491	80	/* Called holding ddata->lock */
9e37a53e YS	81	static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
	82	unsigned long rate)
	83	{
	84	unsigned long long num;
	85	unsigned long scale_pow;
	86	int scale;
	87	u32 val;
	88	/*
	89	* The PWM unit is used with pwmzerocmp=0, so the only way to modify the
	90	* period length is using pwmscale which provides the number of bits the
	91	* counter is shifted before being feed to the comparators. A period
	92	* lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
	93	* (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
	94	*/
	95	scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
	96	scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
	97
	98	val = PWM_SIFIVE_PWMCFG_EN_ALWAYS \|
	99	FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
	100	writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
	101
	102	/* As scale <= 15 the shift operation cannot overflow. */
	103	num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
	104	ddata->real_period = div64_ul(num, rate);
	105	dev_dbg(ddata->chip.dev,
	106	"New real_period = %u ns\n", ddata->real_period);
	107	}
	108
6c452cff UKK	109	static int pwm_sifive_get_state(struct pwm_chip chip, struct pwm_device pwm,
6c452cff UKK	110	struct pwm_state *state)
9e37a53e YS	111	{
	112	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
	113	u32 duty, val;
	114
20550a61	115	duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
9e37a53e YS	116
	117	state->enabled = duty > 0;
	118
	119	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
	120	if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
	121	state->enabled = false;
	122
	123	state->period = ddata->real_period;
	124	state->duty_cycle =
	125	(u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
	126	state->polarity = PWM_POLARITY_INVERSED;
6c452cff UKK	127
6c452cff UKK	128	return 0;
9e37a53e YS	129	}
9e37a53e YS	130
9e37a53e	131	static int pwm_sifive_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	132	const struct pwm_state *state)
9e37a53e YS	133	{
	134	struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
	135	struct pwm_state cur_state;
	136	unsigned int duty_cycle;
	137	unsigned long long num;
	138	bool enabled;
	139	int ret = 0;
	140	u32 frac;
	141
	142	if (state->polarity != PWM_POLARITY_INVERSED)
	143	return -EINVAL;
	144
9e37a53e YS	145	cur_state = pwm->state;
	146	enabled = cur_state.enabled;
	147
	148	duty_cycle = state->duty_cycle;
	149	if (!state->enabled)
	150	duty_cycle = 0;
	151
	152	/*
	153	* The problem of output producing mixed setting as mentioned at top,
	154	* occurs here. To minimize the window for this problem, we are
	155	* calculating the register values first and then writing them
	156	* consecutively
	157	*/
	158	num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
4cc23430	159	frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
9e37a53e YS	160	/* The hardware cannot generate a 100% duty cycle */
	161	frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
	162
0f02f491	163	mutex_lock(&ddata->lock);
9e37a53e	164	if (state->period != ddata->approx_period) {
334c7b13 ERB	165	/*
	166	* Don't let a 2nd user change the period underneath the 1st user.
	167	* However if ddate->approx_period == 0 this is the first time we set
	168	* any period, so let whoever gets here first set the period so other
	169	* users who agree on the period won't fail.
	170	*/
	171	if (ddata->user_count != 1 && ddata->approx_period) {
0f02f491	172	mutex_unlock(&ddata->lock);
3586b026	173	return -EBUSY;
9e37a53e YS	174	}
	175	ddata->approx_period = state->period;
	176	pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
	177	}
0f02f491	178	mutex_unlock(&ddata->lock);
9e37a53e	179
1695b421 UKK	180	/*
	181	* If the PWM is enabled the clk is already on. So only enable it
	182	* conditionally to have it on exactly once afterwards independent of
	183	* the PWM state.
	184	*/
	185	if (!enabled) {
	186	ret = clk_enable(ddata->clk);
	187	if (ret) {
	188	dev_err(ddata->chip.dev, "Enable clk failed\n");
	189	return ret;
	190	}
3586b026 UKK	191	}
3586b026 UKK	192
20550a61	193	writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
9e37a53e	194
1695b421 UKK	195	if (!state->enabled)
1695b421 UKK	196	clk_disable(ddata->clk);
9e37a53e	197
3586b026	198	return 0;
9e37a53e YS	199	}
	200
	201	static const struct pwm_ops pwm_sifive_ops = {
	202	.request = pwm_sifive_request,
	203	.free = pwm_sifive_free,
	204	.get_state = pwm_sifive_get_state,
	205	.apply = pwm_sifive_apply,
	206	.owner = THIS_MODULE,
	207	};
	208
	209	static int pwm_sifive_clock_notifier(struct notifier_block *nb,
	210	unsigned long event, void *data)
	211	{
	212	struct clk_notifier_data *ndata = data;
	213	struct pwm_sifive_ddata *ddata =
	214	container_of(nb, struct pwm_sifive_ddata, notifier);
	215
45558b3a UKK	216	if (event == POST_RATE_CHANGE) {
45558b3a UKK	217	mutex_lock(&ddata->lock);
9e37a53e	218	pwm_sifive_update_clock(ddata, ndata->new_rate);
45558b3a UKK	219	mutex_unlock(&ddata->lock);
45558b3a UKK	220	}
9e37a53e YS	221
	222	return NOTIFY_OK;
	223	}
	224
	225	static int pwm_sifive_probe(struct platform_device *pdev)
	226	{
	227	struct device *dev = &pdev->dev;
	228	struct pwm_sifive_ddata *ddata;
	229	struct pwm_chip *chip;
9e37a53e	230	int ret;
ace41d75 UKK	231	u32 val;
ace41d75 UKK	232	unsigned int enabled_pwms = 0, enabled_clks = 1;
9e37a53e YS	233
	234	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
	235	if (!ddata)
	236	return -ENOMEM;
	237
	238	mutex_init(&ddata->lock);
	239	chip = &ddata->chip;
	240	chip->dev = dev;
	241	chip->ops = &pwm_sifive_ops;
9e37a53e YS	242	chip->npwm = 4;
9e37a53e YS	243
96cfceba	244	ddata->regs = devm_platform_ioremap_resource(pdev, 0);
f6abac03	245	if (IS_ERR(ddata->regs))
9e37a53e	246	return PTR_ERR(ddata->regs);
9e37a53e	247
55e644b8	248	ddata->clk = devm_clk_get_prepared(dev, NULL);
5530fcaf KK	249	if (IS_ERR(ddata->clk))
	250	return dev_err_probe(dev, PTR_ERR(ddata->clk),
	251	"Unable to find controller clock\n");
9e37a53e	252
55e644b8	253	ret = clk_enable(ddata->clk);
9e37a53e YS	254	if (ret) {
	255	dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
	256	return ret;
	257	}
	258
ace41d75 UKK	259	val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
	260	if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
	261	unsigned int i;
	262
	263	for (i = 0; i < chip->npwm; ++i) {
	264	val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
	265	if (val > 0)
	266	++enabled_pwms;
	267	}
	268	}
	269
	270	/* The clk should be on once for each running PWM. */
	271	if (enabled_pwms) {
	272	while (enabled_clks < enabled_pwms) {
	273	/* This is not expected to fail as the clk is already on */
	274	ret = clk_enable(ddata->clk);
	275	if (unlikely(ret)) {
	276	dev_err_probe(dev, ret, "Failed to enable clk\n");
	277	goto disable_clk;
	278	}
	279	++enabled_clks;
	280	}
	281	} else {
	282	clk_disable(ddata->clk);
	283	enabled_clks = 0;
	284	}
	285
9e37a53e YS	286	/* Watch for changes to underlying clock frequency */
	287	ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
	288	ret = clk_notifier_register(ddata->clk, &ddata->notifier);
	289	if (ret) {
	290	dev_err(dev, "failed to register clock notifier: %d\n", ret);
	291	goto disable_clk;
	292	}
	293
	294	ret = pwmchip_add(chip);
	295	if (ret < 0) {
	296	dev_err(dev, "cannot register PWM: %d\n", ret);
	297	goto unregister_clk;
	298	}
	299
	300	platform_set_drvdata(pdev, ddata);
	301	dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
	302
	303	return 0;
	304
	305	unregister_clk:
	306	clk_notifier_unregister(ddata->clk, &ddata->notifier);
	307	disable_clk:
ace41d75 UKK	308	while (enabled_clks) {
	309	clk_disable(ddata->clk);
	310	--enabled_clks;
	311	}
9e37a53e YS	312
	313	return ret;
	314	}
	315
533d2947	316	static void pwm_sifive_remove(struct platform_device *dev)
9e37a53e YS	317	{
9e37a53e YS	318	struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
9e37a53e	319	struct pwm_device *pwm;
ceb2c284	320	int ch;
9e37a53e	321
2375e964 UKK	322	pwmchip_remove(&ddata->chip);
	323	clk_notifier_unregister(ddata->clk, &ddata->notifier);
	324
9e37a53e YS	325	for (ch = 0; ch < ddata->chip.npwm; ch++) {
9e37a53e YS	326	pwm = &ddata->chip.pwms[ch];
ace41d75 UKK	327	if (pwm->state.enabled)
ace41d75 UKK	328	clk_disable(ddata->clk);
9e37a53e	329	}
9e37a53e YS	330	}
	331
	332	static const struct of_device_id pwm_sifive_of_match[] = {
	333	{ .compatible = "sifive,pwm0" },
	334	{},
	335	};
	336	MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
	337
	338	static struct platform_driver pwm_sifive_driver = {
	339	.probe = pwm_sifive_probe,
533d2947	340	.remove_new = pwm_sifive_remove,
9e37a53e YS	341	.driver = {
	342	.name = "pwm-sifive",
	343	.of_match_table = pwm_sifive_of_match,
	344	},
	345	};
	346	module_platform_driver(pwm_sifive_driver);
	347
	348	MODULE_DESCRIPTION("SiFive PWM driver");
	349	MODULE_LICENSE("GPL v2");