[linux.git] / drivers / gpio / gpio-vf610.c

/*
 * Freescale vf610 GPIO support through PORT and GPIO
 *
 * Copyright (c) 2014 Toradex AG.
 *
 * Author: Stefan Agner <[email protected]>.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>

#define VF610_GPIO_PER_PORT		32

struct vf610_gpio_port {
	struct gpio_chip gc;
	void __iomem *base;
	void __iomem *gpio_base;
	u8 irqc[VF610_GPIO_PER_PORT];
	int irq;
};

#define GPIO_PDOR		0x00
#define GPIO_PSOR		0x04
#define GPIO_PCOR		0x08
#define GPIO_PTOR		0x0c
#define GPIO_PDIR		0x10

#define PORT_PCR(n)		((n) * 0x4)
#define PORT_PCR_IRQC_OFFSET	16

#define PORT_ISFR		0xa0
#define PORT_DFER		0xc0
#define PORT_DFCR		0xc4
#define PORT_DFWR		0xc8

#define PORT_INT_OFF		0x0
#define PORT_INT_LOGIC_ZERO	0x8
#define PORT_INT_RISING_EDGE	0x9
#define PORT_INT_FALLING_EDGE	0xa
#define PORT_INT_EITHER_EDGE	0xb
#define PORT_INT_LOGIC_ONE	0xc

static struct irq_chip vf610_gpio_irq_chip;

static const struct of_device_id vf610_gpio_dt_ids[] = {
	{ .compatible = "fsl,vf610-gpio" },
	{ /* sentinel */ }
};

static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
{
	writel_relaxed(val, reg);
}

static inline u32 vf610_gpio_readl(void __iomem *reg)
{
	return readl_relaxed(reg);
}

static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);

	return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR) & BIT(gpio));
}

static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	unsigned long mask = BIT(gpio);

	if (val)
		vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR);
	else
		vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR);
}

static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
	return pinctrl_gpio_direction_input(chip->base + gpio);
}

static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
				       int value)
{
	vf610_gpio_set(chip, gpio, value);

	return pinctrl_gpio_direction_output(chip->base + gpio);
}

static void vf610_gpio_irq_handler(struct irq_desc *desc)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int pin;
	unsigned long irq_isfr;

	chained_irq_enter(chip, desc);

	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);

	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
		vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);

		generic_handle_irq(irq_find_mapping(port->gc.irqdomain, pin));
	}

	chained_irq_exit(chip, desc);
}

static void vf610_gpio_irq_ack(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	int gpio = d->hwirq;

	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
}

static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	u8 irqc;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irqc = PORT_INT_RISING_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irqc = PORT_INT_FALLING_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		irqc = PORT_INT_EITHER_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irqc = PORT_INT_LOGIC_ZERO;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irqc = PORT_INT_LOGIC_ONE;
		break;
	default:
		return -EINVAL;
	}

	port->irqc[d->hwirq] = irqc;

	if (type & IRQ_TYPE_LEVEL_MASK)
		irq_set_handler_locked(d, handle_level_irq);
	else
		irq_set_handler_locked(d, handle_edge_irq);

	return 0;
}

static void vf610_gpio_irq_mask(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);

	vf610_gpio_writel(0, pcr_base);
}

static void vf610_gpio_irq_unmask(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);

	vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
			  pcr_base);
}

static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static struct irq_chip vf610_gpio_irq_chip = {
	.name		= "gpio-vf610",
	.irq_ack	= vf610_gpio_irq_ack,
	.irq_mask	= vf610_gpio_irq_mask,
	.irq_unmask	= vf610_gpio_irq_unmask,
	.irq_set_type	= vf610_gpio_irq_set_type,
	.irq_set_wake	= vf610_gpio_irq_set_wake,
};

static int vf610_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct vf610_gpio_port *port;
	struct resource *iores;
	struct gpio_chip *gc;
	int ret;

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	port->base = devm_ioremap_resource(dev, iores);
	if (IS_ERR(port->base))
		return PTR_ERR(port->base);

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	port->gpio_base = devm_ioremap_resource(dev, iores);
	if (IS_ERR(port->gpio_base))
		return PTR_ERR(port->gpio_base);

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	gc = &port->gc;
	gc->of_node = np;
	gc->parent = dev;
	gc->label = "vf610-gpio";
	gc->ngpio = VF610_GPIO_PER_PORT;
	gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;

	gc->request = gpiochip_generic_request;
	gc->free = gpiochip_generic_free;
	gc->direction_input = vf610_gpio_direction_input;
	gc->get = vf610_gpio_get;
	gc->direction_output = vf610_gpio_direction_output;
	gc->set = vf610_gpio_set;

	ret = gpiochip_add_data(gc, port);
	if (ret < 0)
		return ret;

	/* Clear the interrupt status register for all GPIO's */
	vf610_gpio_writel(~0, port->base + PORT_ISFR);

	ret = gpiochip_irqchip_add(gc, &vf610_gpio_irq_chip, 0,
				   handle_edge_irq, IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "failed to add irqchip\n");
		gpiochip_remove(gc);
		return ret;
	}
	gpiochip_set_chained_irqchip(gc, &vf610_gpio_irq_chip, port->irq,
				     vf610_gpio_irq_handler);

	return 0;
}

static struct platform_driver vf610_gpio_driver = {
	.driver		= {
		.name	= "gpio-vf610",
		.of_match_table = vf610_gpio_dt_ids,
	},
	.probe		= vf610_gpio_probe,
};

builtin_platform_driver(vf610_gpio_driver);
Commit	Line	Data
7f2691a1	1	/*
adaaf63e	2	* Freescale vf610 GPIO support through PORT and GPIO
7f2691a1 SA	3	*
	4	* Copyright (c) 2014 Toradex AG.
	5	*
	6	* Author: Stefan Agner <[email protected]>.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/bitops.h>
	19	#include <linux/err.h>
	20	#include <linux/gpio.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/io.h>
	24	#include <linux/ioport.h>
	25	#include <linux/irq.h>
7f2691a1 SA	26	#include <linux/platform_device.h>
	27	#include <linux/of.h>
	28	#include <linux/of_device.h>
	29	#include <linux/of_irq.h>
	30
	31	#define VF610_GPIO_PER_PORT 32
	32
	33	struct vf610_gpio_port {
	34	struct gpio_chip gc;
	35	void __iomem *base;
	36	void __iomem *gpio_base;
	37	u8 irqc[VF610_GPIO_PER_PORT];
	38	int irq;
	39	};
	40
	41	#define GPIO_PDOR 0x00
	42	#define GPIO_PSOR 0x04
	43	#define GPIO_PCOR 0x08
	44	#define GPIO_PTOR 0x0c
	45	#define GPIO_PDIR 0x10
	46
	47	#define PORT_PCR(n) ((n) * 0x4)
	48	#define PORT_PCR_IRQC_OFFSET 16
	49
	50	#define PORT_ISFR 0xa0
	51	#define PORT_DFER 0xc0
	52	#define PORT_DFCR 0xc4
	53	#define PORT_DFWR 0xc8
	54
	55	#define PORT_INT_OFF 0x0
	56	#define PORT_INT_LOGIC_ZERO 0x8
	57	#define PORT_INT_RISING_EDGE 0x9
	58	#define PORT_INT_FALLING_EDGE 0xa
	59	#define PORT_INT_EITHER_EDGE 0xb
	60	#define PORT_INT_LOGIC_ONE 0xc
	61
fd968115 SA	62	static struct irq_chip vf610_gpio_irq_chip;
fd968115 SA	63
7f2691a1 SA	64	static const struct of_device_id vf610_gpio_dt_ids[] = {
	65	{ .compatible = "fsl,vf610-gpio" },
	66	{ /* sentinel */ }
	67	};
	68
	69	static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
	70	{
	71	writel_relaxed(val, reg);
	72	}
	73
	74	static inline u32 vf610_gpio_readl(void __iomem *reg)
	75	{
	76	return readl_relaxed(reg);
	77	}
	78
7f2691a1 SA	79	static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
7f2691a1 SA	80	{
65389b49	81	struct vf610_gpio_port *port = gpiochip_get_data(gc);
7f2691a1 SA	82
	83	return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR) & BIT(gpio));
	84	}
	85
	86	static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	87	{
65389b49	88	struct vf610_gpio_port *port = gpiochip_get_data(gc);
7f2691a1 SA	89	unsigned long mask = BIT(gpio);
	90
	91	if (val)
	92	vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR);
	93	else
	94	vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR);
	95	}
	96
	97	static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
	98	{
	99	return pinctrl_gpio_direction_input(chip->base + gpio);
	100	}
	101
	102	static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
	103	int value)
	104	{
	105	vf610_gpio_set(chip, gpio, value);
	106
	107	return pinctrl_gpio_direction_output(chip->base + gpio);
	108	}
	109
bd0b9ac4	110	static void vf610_gpio_irq_handler(struct irq_desc *desc)
7f2691a1	111	{
2f930643	112	struct vf610_gpio_port *port =
65389b49	113	gpiochip_get_data(irq_desc_get_handler_data(desc));
7f2691a1 SA	114	struct irq_chip *chip = irq_desc_get_chip(desc);
	115	int pin;
	116	unsigned long irq_isfr;
	117
	118	chained_irq_enter(chip, desc);
	119
	120	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
	121
	122	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
	123	vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
	124
	125	generic_handle_irq(irq_find_mapping(port->gc.irqdomain, pin));
	126	}
	127
	128	chained_irq_exit(chip, desc);
	129	}
	130
	131	static void vf610_gpio_irq_ack(struct irq_data *d)
	132	{
2f930643	133	struct vf610_gpio_port *port =
65389b49	134	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	135	int gpio = d->hwirq;
	136
	137	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
	138	}
	139
	140	static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
	141	{
2f930643	142	struct vf610_gpio_port *port =
65389b49	143	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	144	u8 irqc;
	145
	146	switch (type) {
	147	case IRQ_TYPE_EDGE_RISING:
	148	irqc = PORT_INT_RISING_EDGE;
	149	break;
	150	case IRQ_TYPE_EDGE_FALLING:
	151	irqc = PORT_INT_FALLING_EDGE;
	152	break;
	153	case IRQ_TYPE_EDGE_BOTH:
	154	irqc = PORT_INT_EITHER_EDGE;
	155	break;
	156	case IRQ_TYPE_LEVEL_LOW:
	157	irqc = PORT_INT_LOGIC_ZERO;
	158	break;
	159	case IRQ_TYPE_LEVEL_HIGH:
	160	irqc = PORT_INT_LOGIC_ONE;
	161	break;
	162	default:
	163	return -EINVAL;
	164	}
	165
	166	port->irqc[d->hwirq] = irqc;
	167
fd968115	168	if (type & IRQ_TYPE_LEVEL_MASK)
a7147db0	169	irq_set_handler_locked(d, handle_level_irq);
fd968115	170	else
a7147db0	171	irq_set_handler_locked(d, handle_edge_irq);
fd968115	172
7f2691a1 SA	173	return 0;
	174	}
	175
	176	static void vf610_gpio_irq_mask(struct irq_data *d)
	177	{
2f930643	178	struct vf610_gpio_port *port =
65389b49	179	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	180	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
	181
	182	vf610_gpio_writel(0, pcr_base);
	183	}
	184
	185	static void vf610_gpio_irq_unmask(struct irq_data *d)
	186	{
2f930643	187	struct vf610_gpio_port *port =
65389b49	188	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	189	void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq);
	190
	191	vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET,
	192	pcr_base);
	193	}
	194
	195	static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
	196	{
2f930643	197	struct vf610_gpio_port *port =
65389b49	198	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	199
	200	if (enable)
	201	enable_irq_wake(port->irq);
	202	else
	203	disable_irq_wake(port->irq);
	204
	205	return 0;
	206	}
	207
	208	static struct irq_chip vf610_gpio_irq_chip = {
	209	.name = "gpio-vf610",
	210	.irq_ack = vf610_gpio_irq_ack,
	211	.irq_mask = vf610_gpio_irq_mask,
	212	.irq_unmask = vf610_gpio_irq_unmask,
	213	.irq_set_type = vf610_gpio_irq_set_type,
	214	.irq_set_wake = vf610_gpio_irq_set_wake,
	215	};
	216
	217	static int vf610_gpio_probe(struct platform_device *pdev)
	218	{
	219	struct device *dev = &pdev->dev;
	220	struct device_node *np = dev->of_node;
	221	struct vf610_gpio_port *port;
	222	struct resource *iores;
	223	struct gpio_chip *gc;
	224	int ret;
	225
	226	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	227	if (!port)
	228	return -ENOMEM;
	229
	230	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	231	port->base = devm_ioremap_resource(dev, iores);
	232	if (IS_ERR(port->base))
	233	return PTR_ERR(port->base);
	234
	235	iores = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	236	port->gpio_base = devm_ioremap_resource(dev, iores);
	237	if (IS_ERR(port->gpio_base))
	238	return PTR_ERR(port->gpio_base);
	239
	240	port->irq = platform_get_irq(pdev, 0);
	241	if (port->irq < 0)
	242	return port->irq;
	243
	244	gc = &port->gc;
	245	gc->of_node = np;
58383c78	246	gc->parent = dev;
d32efe37 AL	247	gc->label = "vf610-gpio";
d32efe37 AL	248	gc->ngpio = VF610_GPIO_PER_PORT;
7f2691a1 SA	249	gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT;
7f2691a1 SA	250
203f0daa JG	251	gc->request = gpiochip_generic_request;
203f0daa JG	252	gc->free = gpiochip_generic_free;
d32efe37 AL	253	gc->direction_input = vf610_gpio_direction_input;
	254	gc->get = vf610_gpio_get;
	255	gc->direction_output = vf610_gpio_direction_output;
	256	gc->set = vf610_gpio_set;
7f2691a1	257
65389b49	258	ret = gpiochip_add_data(gc, port);
7f2691a1 SA	259	if (ret < 0)
	260	return ret;
	261
	262	/* Clear the interrupt status register for all GPIO's */
	263	vf610_gpio_writel(~0, port->base + PORT_ISFR);
	264
	265	ret = gpiochip_irqchip_add(gc, &vf610_gpio_irq_chip, 0,
fd968115	266	handle_edge_irq, IRQ_TYPE_NONE);
7f2691a1 SA	267	if (ret) {
	268	dev_err(dev, "failed to add irqchip\n");
	269	gpiochip_remove(gc);
	270	return ret;
	271	}
	272	gpiochip_set_chained_irqchip(gc, &vf610_gpio_irq_chip, port->irq,
	273	vf610_gpio_irq_handler);
	274
	275	return 0;
	276	}
	277
	278	static struct platform_driver vf610_gpio_driver = {
	279	.driver = {
	280	.name = "gpio-vf610",
7f2691a1 SA	281	.of_match_table = vf610_gpio_dt_ids,
	282	},
	283	.probe = vf610_gpio_probe,
	284	};
	285
df950da1	286	builtin_platform_driver(vf610_gpio_driver);