[linux.git] / drivers / pwm / pwm-hibvt.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * PWM Controller Driver for HiSilicon BVT SoCs
 *
 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/reset.h>

#define PWM_CFG0_ADDR(x)    (((x) * 0x20) + 0x0)
#define PWM_CFG1_ADDR(x)    (((x) * 0x20) + 0x4)
#define PWM_CFG2_ADDR(x)    (((x) * 0x20) + 0x8)
#define PWM_CTRL_ADDR(x)    (((x) * 0x20) + 0xC)

#define PWM_ENABLE_SHIFT    0
#define PWM_ENABLE_MASK     BIT(0)

#define PWM_POLARITY_SHIFT  1
#define PWM_POLARITY_MASK   BIT(1)

#define PWM_KEEP_SHIFT      2
#define PWM_KEEP_MASK       BIT(2)

#define PWM_PERIOD_MASK     GENMASK(31, 0)
#define PWM_DUTY_MASK       GENMASK(31, 0)

struct hibvt_pwm_chip {
	struct pwm_chip	chip;
	struct clk *clk;
	void __iomem *base;
	struct reset_control *rstc;
	const struct hibvt_pwm_soc *soc;
};

struct hibvt_pwm_soc {
	u32 num_pwms;
	bool quirk_force_enable;
};

static const struct hibvt_pwm_soc hi3516cv300_soc_info = {
	.num_pwms = 4,
};

static const struct hibvt_pwm_soc hi3519v100_soc_info = {
	.num_pwms = 8,
};

static const struct hibvt_pwm_soc hi3559v100_shub_soc_info = {
	.num_pwms = 8,
	.quirk_force_enable = true,
};

static const struct hibvt_pwm_soc hi3559v100_soc_info = {
	.num_pwms = 2,
	.quirk_force_enable = true,
};

static inline struct hibvt_pwm_chip *to_hibvt_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct hibvt_pwm_chip, chip);
}

static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,
					u32 mask, u32 data)
{
	void __iomem *address = base + offset;
	u32 value;

	value = readl(address);
	value &= ~mask;
	value |= (data & mask);
	writel(value, address);
}

static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);

	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
			PWM_ENABLE_MASK, 0x1);
}

static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);

	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
			PWM_ENABLE_MASK, 0x0);
}

static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
					int duty_cycle_ns, int period_ns)
{
	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
	u32 freq, period, duty;

	freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);

	period = div_u64(freq * period_ns, 1000);
	duty = div_u64(period * duty_cycle_ns, period_ns);

	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
			PWM_PERIOD_MASK, period);

	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
			PWM_DUTY_MASK, duty);
}

static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
					struct pwm_device *pwm,
					enum pwm_polarity polarity)
{
	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);

	if (polarity == PWM_POLARITY_INVERSED)
		hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
				PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT));
	else
		hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
				PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
}

static void hibvt_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				struct pwm_state *state)
{
	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
	void __iomem *base;
	u32 freq, value;

	freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
	base = hi_pwm_chip->base;

	value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
	state->period = div_u64(value * 1000, freq);

	value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
	state->duty_cycle = div_u64(value * 1000, freq);

	value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
	state->enabled = (PWM_ENABLE_MASK & value);
}

static int hibvt_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);

	if (state->polarity != pwm->state.polarity)
		hibvt_pwm_set_polarity(chip, pwm, state->polarity);

	if (state->period != pwm->state.period ||
	    state->duty_cycle != pwm->state.duty_cycle) {
		hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);

		/*
		 * Some implementations require the PWM to be enabled twice
		 * each time the duty cycle is refreshed.
		 */
		if (hi_pwm_chip->soc->quirk_force_enable && state->enabled)
			hibvt_pwm_enable(chip, pwm);
	}

	if (state->enabled != pwm->state.enabled) {
		if (state->enabled)
			hibvt_pwm_enable(chip, pwm);
		else
			hibvt_pwm_disable(chip, pwm);
	}

	return 0;
}

static const struct pwm_ops hibvt_pwm_ops = {
	.get_state = hibvt_pwm_get_state,
	.apply = hibvt_pwm_apply,

	.owner = THIS_MODULE,
};

static int hibvt_pwm_probe(struct platform_device *pdev)
{
	const struct hibvt_pwm_soc *soc =
				of_device_get_match_data(&pdev->dev);
	struct hibvt_pwm_chip *pwm_chip;
	int ret, i;

	pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);
	if (pwm_chip == NULL)
		return -ENOMEM;

	pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pwm_chip->clk)) {
		dev_err(&pdev->dev, "getting clock failed with %ld\n",
				PTR_ERR(pwm_chip->clk));
		return PTR_ERR(pwm_chip->clk);
	}

	pwm_chip->chip.ops = &hibvt_pwm_ops;
	pwm_chip->chip.dev = &pdev->dev;
	pwm_chip->chip.npwm = soc->num_pwms;
	pwm_chip->soc = soc;

	pwm_chip->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pwm_chip->base))
		return PTR_ERR(pwm_chip->base);

	ret = clk_prepare_enable(pwm_chip->clk);
	if (ret < 0)
		return ret;

	pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	if (IS_ERR(pwm_chip->rstc)) {
		clk_disable_unprepare(pwm_chip->clk);
		return PTR_ERR(pwm_chip->rstc);
	}

	reset_control_assert(pwm_chip->rstc);
	msleep(30);
	reset_control_deassert(pwm_chip->rstc);

	ret = pwmchip_add(&pwm_chip->chip);
	if (ret < 0) {
		clk_disable_unprepare(pwm_chip->clk);
		return ret;
	}

	for (i = 0; i < pwm_chip->chip.npwm; i++) {
		hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),
				PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT));
	}

	platform_set_drvdata(pdev, pwm_chip);

	return 0;
}

static int hibvt_pwm_remove(struct platform_device *pdev)
{
	struct hibvt_pwm_chip *pwm_chip;

	pwm_chip = platform_get_drvdata(pdev);

	pwmchip_remove(&pwm_chip->chip);

	reset_control_assert(pwm_chip->rstc);
	msleep(30);
	reset_control_deassert(pwm_chip->rstc);

	clk_disable_unprepare(pwm_chip->clk);

	return 0;
}

static const struct of_device_id hibvt_pwm_of_match[] = {
	{ .compatible = "hisilicon,hi3516cv300-pwm",
	  .data = &hi3516cv300_soc_info },
	{ .compatible = "hisilicon,hi3519v100-pwm",
	  .data = &hi3519v100_soc_info },
	{ .compatible = "hisilicon,hi3559v100-shub-pwm",
	  .data = &hi3559v100_shub_soc_info },
	{ .compatible = "hisilicon,hi3559v100-pwm",
	  .data = &hi3559v100_soc_info },
	{  }
};
MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match);

static struct platform_driver hibvt_pwm_driver = {
	.driver = {
		.name = "hibvt-pwm",
		.of_match_table = hibvt_pwm_of_match,
	},
	.probe = hibvt_pwm_probe,
	.remove	= hibvt_pwm_remove,
};
module_platform_driver(hibvt_pwm_driver);

MODULE_AUTHOR("Jian Yuan");
MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1ccea77e	1	// SPDX-License-Identifier: GPL-2.0-or-later
d09f0081	2	/*
	3	* PWM Controller Driver for HiSilicon BVT SoCs
	4	*
	5	* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
d09f0081	6	*/
	7
	8	#include <linux/bitops.h>
	9	#include <linux/clk.h>
	10	#include <linux/delay.h>
	11	#include <linux/io.h>
	12	#include <linux/module.h>
	13	#include <linux/of_device.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pwm.h>
	16	#include <linux/reset.h>
	17
	18	#define PWM_CFG0_ADDR(x) (((x) * 0x20) + 0x0)
	19	#define PWM_CFG1_ADDR(x) (((x) * 0x20) + 0x4)
	20	#define PWM_CFG2_ADDR(x) (((x) * 0x20) + 0x8)
	21	#define PWM_CTRL_ADDR(x) (((x) * 0x20) + 0xC)
	22
	23	#define PWM_ENABLE_SHIFT 0
	24	#define PWM_ENABLE_MASK BIT(0)
	25
	26	#define PWM_POLARITY_SHIFT 1
	27	#define PWM_POLARITY_MASK BIT(1)
	28
	29	#define PWM_KEEP_SHIFT 2
	30	#define PWM_KEEP_MASK BIT(2)
	31
	32	#define PWM_PERIOD_MASK GENMASK(31, 0)
	33	#define PWM_DUTY_MASK GENMASK(31, 0)
	34
	35	struct hibvt_pwm_chip {
	36	struct pwm_chip chip;
	37	struct clk *clk;
	38	void __iomem *base;
	39	struct reset_control *rstc;
77c3edde	40	const struct hibvt_pwm_soc *soc;
d09f0081	41	};
	42
	43	struct hibvt_pwm_soc {
	44	u32 num_pwms;
7a58fc54	45	bool quirk_force_enable;
d09f0081	46	};
d09f0081	47
77c3edde MO	48	static const struct hibvt_pwm_soc hi3516cv300_soc_info = {
	49	.num_pwms = 4,
	50	};
	51
	52	static const struct hibvt_pwm_soc hi3519v100_soc_info = {
	53	.num_pwms = 8,
d09f0081	54	};
d09f0081	55
7a58fc54 MO	56	static const struct hibvt_pwm_soc hi3559v100_shub_soc_info = {
	57	.num_pwms = 8,
	58	.quirk_force_enable = true,
	59	};
	60
	61	static const struct hibvt_pwm_soc hi3559v100_soc_info = {
	62	.num_pwms = 2,
	63	.quirk_force_enable = true,
	64	};
	65
d09f0081	66	static inline struct hibvt_pwm_chip to_hibvt_pwm_chip(struct pwm_chip chip)
	67	{
	68	return container_of(chip, struct hibvt_pwm_chip, chip);
	69	}
	70
	71	static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,
	72	u32 mask, u32 data)
	73	{
	74	void __iomem *address = base + offset;
	75	u32 value;
	76
	77	value = readl(address);
	78	value &= ~mask;
	79	value \|= (data & mask);
	80	writel(value, address);
	81	}
	82
	83	static void hibvt_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	84	{
	85	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
	86
	87	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
	88	PWM_ENABLE_MASK, 0x1);
	89	}
	90
	91	static void hibvt_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	92	{
	93	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
	94
	95	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
	96	PWM_ENABLE_MASK, 0x0);
	97	}
	98
	99	static void hibvt_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	100	int duty_cycle_ns, int period_ns)
	101	{
	102	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
	103	u32 freq, period, duty;
	104
	105	freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
	106
	107	period = div_u64(freq * period_ns, 1000);
	108	duty = div_u64(period * duty_cycle_ns, period_ns);
	109
	110	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),
	111	PWM_PERIOD_MASK, period);
	112
	113	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),
	114	PWM_DUTY_MASK, duty);
	115	}
	116
	117	static void hibvt_pwm_set_polarity(struct pwm_chip *chip,
	118	struct pwm_device *pwm,
	119	enum pwm_polarity polarity)
	120	{
	121	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
	122
	123	if (polarity == PWM_POLARITY_INVERSED)
	124	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
	125	PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT));
	126	else
	127	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),
	128	PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT));
	129	}
130
131	static void hibvt_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
132	struct pwm_state *state)
133	{
134	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
135	void __iomem *base;
136	u32 freq, value;
137
138	freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);
139	base = hi_pwm_chip->base;
140
141	value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));
142	state->period = div_u64(value * 1000, freq);
143
144	value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));
145	state->duty_cycle = div_u64(value * 1000, freq);
146
147	value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));
148	state->enabled = (PWM_ENABLE_MASK & value);
149	}
150
151	static int hibvt_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	152	const struct pwm_state *state)
d09f0081	153	{
7a58fc54 MO	154	struct hibvt_pwm_chip *hi_pwm_chip = to_hibvt_pwm_chip(chip);
7a58fc54 MO	155
d09f0081	156	if (state->polarity != pwm->state.polarity)
	157	hibvt_pwm_set_polarity(chip, pwm, state->polarity);
	158
	159	if (state->period != pwm->state.period \|\|
7a58fc54	160	state->duty_cycle != pwm->state.duty_cycle) {
d09f0081	161	hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);
d09f0081	162
7a58fc54 MO	163	/*
	164	* Some implementations require the PWM to be enabled twice
	165	* each time the duty cycle is refreshed.
	166	*/
	167	if (hi_pwm_chip->soc->quirk_force_enable && state->enabled)
	168	hibvt_pwm_enable(chip, pwm);
	169	}
	170
d09f0081	171	if (state->enabled != pwm->state.enabled) {
	172	if (state->enabled)
	173	hibvt_pwm_enable(chip, pwm);
	174	else
	175	hibvt_pwm_disable(chip, pwm);
	176	}
	177
	178	return 0;
	179	}
	180
c034a6fd	181	static const struct pwm_ops hibvt_pwm_ops = {
d09f0081	182	.get_state = hibvt_pwm_get_state,
	183	.apply = hibvt_pwm_apply,
	184
	185	.owner = THIS_MODULE,
	186	};
	187
	188	static int hibvt_pwm_probe(struct platform_device *pdev)
	189	{
	190	const struct hibvt_pwm_soc *soc =
	191	of_device_get_match_data(&pdev->dev);
	192	struct hibvt_pwm_chip *pwm_chip;
cecccd8d	193	int ret, i;
d09f0081	194
	195	pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);
	196	if (pwm_chip == NULL)
	197	return -ENOMEM;
	198
	199	pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);
	200	if (IS_ERR(pwm_chip->clk)) {
	201	dev_err(&pdev->dev, "getting clock failed with %ld\n",
	202	PTR_ERR(pwm_chip->clk));
	203	return PTR_ERR(pwm_chip->clk);
	204	}
	205
	206	pwm_chip->chip.ops = &hibvt_pwm_ops;
	207	pwm_chip->chip.dev = &pdev->dev;
d09f0081	208	pwm_chip->chip.npwm = soc->num_pwms;
77c3edde	209	pwm_chip->soc = soc;
d09f0081	210
cecccd8d	211	pwm_chip->base = devm_platform_ioremap_resource(pdev, 0);
d09f0081	212	if (IS_ERR(pwm_chip->base))
	213	return PTR_ERR(pwm_chip->base);
	214
	215	ret = clk_prepare_enable(pwm_chip->clk);
	216	if (ret < 0)
	217	return ret;
	218
0fd3b93f	219	pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
d09f0081	220	if (IS_ERR(pwm_chip->rstc)) {
	221	clk_disable_unprepare(pwm_chip->clk);
	222	return PTR_ERR(pwm_chip->rstc);
	223	}
	224
	225	reset_control_assert(pwm_chip->rstc);
	226	msleep(30);
	227	reset_control_deassert(pwm_chip->rstc);
	228
	229	ret = pwmchip_add(&pwm_chip->chip);
	230	if (ret < 0) {
	231	clk_disable_unprepare(pwm_chip->clk);
	232	return ret;
	233	}
	234
	235	for (i = 0; i < pwm_chip->chip.npwm; i++) {
	236	hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),
	237	PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT));
	238	}
	239
	240	platform_set_drvdata(pdev, pwm_chip);
	241
	242	return 0;
	243	}
	244
	245	static int hibvt_pwm_remove(struct platform_device *pdev)
	246	{
	247	struct hibvt_pwm_chip *pwm_chip;
	248
	249	pwm_chip = platform_get_drvdata(pdev);
	250
04d77521 UKK	251	pwmchip_remove(&pwm_chip->chip);
04d77521 UKK	252
d09f0081	253	reset_control_assert(pwm_chip->rstc);
	254	msleep(30);
	255	reset_control_deassert(pwm_chip->rstc);
	256
	257	clk_disable_unprepare(pwm_chip->clk);
	258
04d77521	259	return 0;
d09f0081	260	}
	261
	262	static const struct of_device_id hibvt_pwm_of_match[] = {
77c3edde MO	263	{ .compatible = "hisilicon,hi3516cv300-pwm",
	264	.data = &hi3516cv300_soc_info },
	265	{ .compatible = "hisilicon,hi3519v100-pwm",
	266	.data = &hi3519v100_soc_info },
7a58fc54 MO	267	{ .compatible = "hisilicon,hi3559v100-shub-pwm",
	268	.data = &hi3559v100_shub_soc_info },
	269	{ .compatible = "hisilicon,hi3559v100-pwm",
	270	.data = &hi3559v100_soc_info },
d09f0081	271	{ }
	272	};
	273	MODULE_DEVICE_TABLE(of, hibvt_pwm_of_match);
	274
	275	static struct platform_driver hibvt_pwm_driver = {
	276	.driver = {
	277	.name = "hibvt-pwm",
	278	.of_match_table = hibvt_pwm_of_match,
	279	},
	280	.probe = hibvt_pwm_probe,
	281	.remove = hibvt_pwm_remove,
	282	};
	283	module_platform_driver(hibvt_pwm_driver);
	284
	285	MODULE_AUTHOR("Jian Yuan");
	286	MODULE_DESCRIPTION("HiSilicon BVT SoCs PWM driver");
	287	MODULE_LICENSE("GPL");