[linux.git] / drivers / clk / samsung / clk-exynos-clkout.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 * Author: Tomasz Figa <t.figa@samsung.com>
 *
 * Clock driver for Exynos clock output
 */

#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>

#define EXYNOS_CLKOUT_NR_CLKS		1
#define EXYNOS_CLKOUT_PARENTS		32

#define EXYNOS_PMU_DEBUG_REG		0xa00
#define EXYNOS_CLKOUT_DISABLE_SHIFT	0
#define EXYNOS_CLKOUT_MUX_SHIFT		8
#define EXYNOS4_CLKOUT_MUX_MASK		0xf
#define EXYNOS5_CLKOUT_MUX_MASK		0x1f

struct exynos_clkout {
	struct clk_gate gate;
	struct clk_mux mux;
	spinlock_t slock;
	void __iomem *reg;
	struct device_node *np;
	u32 pmu_debug_save;
	struct clk_hw_onecell_data data;
};

struct exynos_clkout_variant {
	u32 mux_mask;
};

static const struct exynos_clkout_variant exynos_clkout_exynos4 = {
	.mux_mask	= EXYNOS4_CLKOUT_MUX_MASK,
};

static const struct exynos_clkout_variant exynos_clkout_exynos5 = {
	.mux_mask	= EXYNOS5_CLKOUT_MUX_MASK,
};

static const struct of_device_id exynos_clkout_ids[] = {
	{
		.compatible = "samsung,exynos3250-pmu",
		.data = &exynos_clkout_exynos4,
	}, {
		.compatible = "samsung,exynos4210-pmu",
		.data = &exynos_clkout_exynos4,
	}, {
		.compatible = "samsung,exynos4212-pmu",
		.data = &exynos_clkout_exynos4,
	}, {
		.compatible = "samsung,exynos4412-pmu",
		.data = &exynos_clkout_exynos4,
	}, {
		.compatible = "samsung,exynos5250-pmu",
		.data = &exynos_clkout_exynos5,
	}, {
		.compatible = "samsung,exynos5410-pmu",
		.data = &exynos_clkout_exynos5,
	}, {
		.compatible = "samsung,exynos5420-pmu",
		.data = &exynos_clkout_exynos5,
	}, {
		.compatible = "samsung,exynos5433-pmu",
		.data = &exynos_clkout_exynos5,
	}, { }
};
MODULE_DEVICE_TABLE(of, exynos_clkout_ids);

/*
 * Device will be instantiated as child of PMU device without its own
 * device node.  Therefore match compatibles against parent.
 */
static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask)
{
	const struct exynos_clkout_variant *variant;
	const struct of_device_id *match;

	if (!dev->parent) {
		dev_err(dev, "not instantiated from MFD\n");
		return -EINVAL;
	}

	/*
	 * 'exynos_clkout_ids' arrays is not the ids array matched by
	 * the dev->parent driver, so of_device_get_match_data() or
	 * device_get_match_data() cannot be used here.
	 */
	match = of_match_device(exynos_clkout_ids, dev->parent);
	if (!match) {
		dev_err(dev, "cannot match parent device\n");
		return -EINVAL;
	}
	variant = match->data;

	*mux_mask = variant->mux_mask;

	return 0;
}

static int exynos_clkout_probe(struct platform_device *pdev)
{
	const char *parent_names[EXYNOS_CLKOUT_PARENTS];
	struct clk *parents[EXYNOS_CLKOUT_PARENTS];
	struct exynos_clkout *clkout;
	int parent_count, ret, i;
	u32 mux_mask;

	clkout = devm_kzalloc(&pdev->dev,
			      struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
			      GFP_KERNEL);
	if (!clkout)
		return -ENOMEM;

	ret = exynos_clkout_match_parent_dev(&pdev->dev, &mux_mask);
	if (ret)
		return ret;

	clkout->np = pdev->dev.of_node;
	if (!clkout->np) {
		/*
		 * pdev->dev.parent was checked by exynos_clkout_match_parent_dev()
		 * so it is not NULL.
		 */
		clkout->np = pdev->dev.parent->of_node;
	}

	platform_set_drvdata(pdev, clkout);

	spin_lock_init(&clkout->slock);

	parent_count = 0;
	for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
		char name[] = "clkoutXX";

		snprintf(name, sizeof(name), "clkout%d", i);
		parents[i] = of_clk_get_by_name(clkout->np, name);
		if (IS_ERR(parents[i])) {
			parent_names[i] = "none";
			continue;
		}

		parent_names[i] = __clk_get_name(parents[i]);
		parent_count = i + 1;
	}

	if (!parent_count)
		return -EINVAL;

	clkout->reg = of_iomap(clkout->np, 0);
	if (!clkout->reg) {
		ret = -ENODEV;
		goto clks_put;
	}

	clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
	clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
	clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
	clkout->gate.lock = &clkout->slock;

	clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
	clkout->mux.mask = mux_mask;
	clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
	clkout->mux.lock = &clkout->slock;

	clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
				parent_names, parent_count, &clkout->mux.hw,
				&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
				&clk_gate_ops, CLK_SET_RATE_PARENT
				| CLK_SET_RATE_NO_REPARENT);
	if (IS_ERR(clkout->data.hws[0])) {
		ret = PTR_ERR(clkout->data.hws[0]);
		goto err_unmap;
	}

	clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
	ret = of_clk_add_hw_provider(clkout->np, of_clk_hw_onecell_get, &clkout->data);
	if (ret)
		goto err_clk_unreg;

	return 0;

err_clk_unreg:
	clk_hw_unregister(clkout->data.hws[0]);
err_unmap:
	iounmap(clkout->reg);
clks_put:
	for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
		if (!IS_ERR(parents[i]))
			clk_put(parents[i]);

	dev_err(&pdev->dev, "failed to register clkout clock\n");

	return ret;
}

static void exynos_clkout_remove(struct platform_device *pdev)
{
	struct exynos_clkout *clkout = platform_get_drvdata(pdev);

	of_clk_del_provider(clkout->np);
	clk_hw_unregister(clkout->data.hws[0]);
	iounmap(clkout->reg);
}

static int __maybe_unused exynos_clkout_suspend(struct device *dev)
{
	struct exynos_clkout *clkout = dev_get_drvdata(dev);

	clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);

	return 0;
}

static int __maybe_unused exynos_clkout_resume(struct device *dev)
{
	struct exynos_clkout *clkout = dev_get_drvdata(dev);

	writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);

	return 0;
}

static SIMPLE_DEV_PM_OPS(exynos_clkout_pm_ops, exynos_clkout_suspend,
			 exynos_clkout_resume);

static struct platform_driver exynos_clkout_driver = {
	.driver = {
		.name = "exynos-clkout",
		.of_match_table = exynos_clkout_ids,
		.pm = &exynos_clkout_pm_ops,
	},
	.probe = exynos_clkout_probe,
	.remove_new = exynos_clkout_remove,
};
module_platform_driver(exynos_clkout_driver);

MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
MODULE_DESCRIPTION("Samsung Exynos clock output driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1e832e51 TF	2	/*
	3	* Copyright (c) 2014 Samsung Electronics Co., Ltd.
	4	* Author: Tomasz Figa <t.figa@samsung.com>
	5	*
1e832e51 TF	6	* Clock driver for Exynos clock output
	7	*/
	8
6f1ed07a	9	#include <linux/slab.h>
1e832e51	10	#include <linux/clk.h>
1e832e51	11	#include <linux/clk-provider.h>
9484f2cb	12	#include <linux/module.h>
62e59c4e	13	#include <linux/io.h>
1e832e51 TF	14	#include <linux/of.h>
1e832e51 TF	15	#include <linux/of_address.h>
aacb99de	16	#include <linux/of_device.h>
9484f2cb KK	17	#include <linux/platform_device.h>
9484f2cb KK	18	#include <linux/pm.h>
1e832e51 TF	19
	20	#define EXYNOS_CLKOUT_NR_CLKS 1
	21	#define EXYNOS_CLKOUT_PARENTS 32
	22
	23	#define EXYNOS_PMU_DEBUG_REG 0xa00
	24	#define EXYNOS_CLKOUT_DISABLE_SHIFT 0
	25	#define EXYNOS_CLKOUT_MUX_SHIFT 8
	26	#define EXYNOS4_CLKOUT_MUX_MASK 0xf
	27	#define EXYNOS5_CLKOUT_MUX_MASK 0x1f
	28
	29	struct exynos_clkout {
	30	struct clk_gate gate;
	31	struct clk_mux mux;
	32	spinlock_t slock;
1e832e51	33	void __iomem *reg;
9484f2cb	34	struct device_node *np;
1e832e51	35	u32 pmu_debug_save;
cf139514	36	struct clk_hw_onecell_data data;
1e832e51 TF	37	};
1e832e51 TF	38
9484f2cb KK	39	struct exynos_clkout_variant {
	40	u32 mux_mask;
	41	};
1e832e51	42
9484f2cb KK	43	static const struct exynos_clkout_variant exynos_clkout_exynos4 = {
	44	.mux_mask = EXYNOS4_CLKOUT_MUX_MASK,
	45	};
1e832e51	46
9484f2cb KK	47	static const struct exynos_clkout_variant exynos_clkout_exynos5 = {
	48	.mux_mask = EXYNOS5_CLKOUT_MUX_MASK,
	49	};
1e832e51	50
9484f2cb KK	51	static const struct of_device_id exynos_clkout_ids[] = {
	52	{
	53	.compatible = "samsung,exynos3250-pmu",
	54	.data = &exynos_clkout_exynos4,
	55	}, {
	56	.compatible = "samsung,exynos4210-pmu",
	57	.data = &exynos_clkout_exynos4,
48b35973 AW	58	}, {
	59	.compatible = "samsung,exynos4212-pmu",
	60	.data = &exynos_clkout_exynos4,
9484f2cb KK	61	}, {
	62	.compatible = "samsung,exynos4412-pmu",
	63	.data = &exynos_clkout_exynos4,
	64	}, {
	65	.compatible = "samsung,exynos5250-pmu",
	66	.data = &exynos_clkout_exynos5,
	67	}, {
	68	.compatible = "samsung,exynos5410-pmu",
	69	.data = &exynos_clkout_exynos5,
	70	}, {
	71	.compatible = "samsung,exynos5420-pmu",
	72	.data = &exynos_clkout_exynos5,
	73	}, {
	74	.compatible = "samsung,exynos5433-pmu",
	75	.data = &exynos_clkout_exynos5,
	76	}, { }
	77	};
124f0353	78	MODULE_DEVICE_TABLE(of, exynos_clkout_ids);
9484f2cb KK	79
	80	/*
	81	* Device will be instantiated as child of PMU device without its own
	82	* device node. Therefore match compatibles against parent.
	83	*/
	84	static int exynos_clkout_match_parent_dev(struct device dev, u32 mux_mask)
1e832e51	85	{
9484f2cb	86	const struct exynos_clkout_variant *variant;
aacb99de	87	const struct of_device_id *match;
1e832e51	88
9484f2cb KK	89	if (!dev->parent) {
	90	dev_err(dev, "not instantiated from MFD\n");
	91	return -EINVAL;
	92	}
	93
aacb99de MS	94	/*
	95	* 'exynos_clkout_ids' arrays is not the ids array matched by
	96	* the dev->parent driver, so of_device_get_match_data() or
	97	* device_get_match_data() cannot be used here.
	98	*/
	99	match = of_match_device(exynos_clkout_ids, dev->parent);
	100	if (!match) {
9484f2cb KK	101	dev_err(dev, "cannot match parent device\n");
	102	return -EINVAL;
	103	}
aacb99de	104	variant = match->data;
1e832e51	105
9484f2cb KK	106	*mux_mask = variant->mux_mask;
	107
	108	return 0;
	109	}
	110
	111	static int exynos_clkout_probe(struct platform_device *pdev)
1e832e51 TF	112	{
	113	const char *parent_names[EXYNOS_CLKOUT_PARENTS];
	114	struct clk *parents[EXYNOS_CLKOUT_PARENTS];
9484f2cb KK	115	struct exynos_clkout *clkout;
	116	int parent_count, ret, i;
	117	u32 mux_mask;
1e832e51	118
9484f2cb KK	119	clkout = devm_kzalloc(&pdev->dev,
	120	struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
	121	GFP_KERNEL);
1e832e51	122	if (!clkout)
9484f2cb KK	123	return -ENOMEM;
	124
	125	ret = exynos_clkout_match_parent_dev(&pdev->dev, &mux_mask);
	126	if (ret)
	127	return ret;
	128
	129	clkout->np = pdev->dev.of_node;
	130	if (!clkout->np) {
	131	/*
	132	* pdev->dev.parent was checked by exynos_clkout_match_parent_dev()
	133	* so it is not NULL.
	134	*/
	135	clkout->np = pdev->dev.parent->of_node;
	136	}
	137
	138	platform_set_drvdata(pdev, clkout);
1e832e51 TF	139
	140	spin_lock_init(&clkout->slock);
	141
	142	parent_count = 0;
	143	for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
	144	char name[] = "clkoutXX";
	145
	146	snprintf(name, sizeof(name), "clkout%d", i);
9484f2cb	147	parents[i] = of_clk_get_by_name(clkout->np, name);
1e832e51 TF	148	if (IS_ERR(parents[i])) {
	149	parent_names[i] = "none";
	150	continue;
	151	}
	152
	153	parent_names[i] = __clk_get_name(parents[i]);
	154	parent_count = i + 1;
	155	}
	156
	157	if (!parent_count)
9484f2cb	158	return -EINVAL;
1e832e51	159
9484f2cb KK	160	clkout->reg = of_iomap(clkout->np, 0);
	161	if (!clkout->reg) {
	162	ret = -ENODEV;
1e832e51	163	goto clks_put;
9484f2cb	164	}
1e832e51 TF	165
	166	clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
	167	clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
	168	clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
	169	clkout->gate.lock = &clkout->slock;
	170
	171	clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
	172	clkout->mux.mask = mux_mask;
	173	clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
	174	clkout->mux.lock = &clkout->slock;
	175
cf139514	176	clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
1e832e51 TF	177	parent_names, parent_count, &clkout->mux.hw,
	178	&clk_mux_ops, NULL, NULL, &clkout->gate.hw,
	179	&clk_gate_ops, CLK_SET_RATE_PARENT
	180	\| CLK_SET_RATE_NO_REPARENT);
9484f2cb KK	181	if (IS_ERR(clkout->data.hws[0])) {
9484f2cb KK	182	ret = PTR_ERR(clkout->data.hws[0]);
1e832e51	183	goto err_unmap;
9484f2cb	184	}
1e832e51	185
cf139514	186	clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
9484f2cb	187	ret = of_clk_add_hw_provider(clkout->np, of_clk_hw_onecell_get, &clkout->data);
1e832e51 TF	188	if (ret)
	189	goto err_clk_unreg;
	190
9484f2cb	191	return 0;
1e832e51 TF	192
1e832e51 TF	193	err_clk_unreg:
cf139514	194	clk_hw_unregister(clkout->data.hws[0]);
1e832e51 TF	195	err_unmap:
	196	iounmap(clkout->reg);
	197	clks_put:
	198	for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
	199	if (!IS_ERR(parents[i]))
	200	clk_put(parents[i]);
1e832e51	201
9484f2cb KK	202	dev_err(&pdev->dev, "failed to register clkout clock\n");
	203
	204	return ret;
1e832e51 TF	205	}
1e832e51 TF	206
e853fb18	207	static void exynos_clkout_remove(struct platform_device *pdev)
9484f2cb KK	208	{
	209	struct exynos_clkout *clkout = platform_get_drvdata(pdev);
	210
	211	of_clk_del_provider(clkout->np);
	212	clk_hw_unregister(clkout->data.hws[0]);
	213	iounmap(clkout->reg);
9484f2cb	214	}
5c4a9129	215
4c44274e	216	static int __maybe_unused exynos_clkout_suspend(struct device *dev)
1e832e51	217	{
9484f2cb KK	218	struct exynos_clkout *clkout = dev_get_drvdata(dev);
	219
	220	clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
	221
	222	return 0;
1e832e51	223	}
9484f2cb	224
4c44274e	225	static int __maybe_unused exynos_clkout_resume(struct device *dev)
1e832e51	226	{
9484f2cb KK	227	struct exynos_clkout *clkout = dev_get_drvdata(dev);
	228
	229	writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
	230
	231	return 0;
1e832e51	232	}
9484f2cb KK	233
	234	static SIMPLE_DEV_PM_OPS(exynos_clkout_pm_ops, exynos_clkout_suspend,
	235	exynos_clkout_resume);
	236
	237	static struct platform_driver exynos_clkout_driver = {
	238	.driver = {
	239	.name = "exynos-clkout",
	240	.of_match_table = exynos_clkout_ids,
	241	.pm = &exynos_clkout_pm_ops,
	242	},
	243	.probe = exynos_clkout_probe,
e853fb18	244	.remove_new = exynos_clkout_remove,
9484f2cb KK	245	};
	246	module_platform_driver(exynos_clkout_driver);
	247
	248	MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
	249	MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
	250	MODULE_DESCRIPTION("Samsung Exynos clock output driver");
	251	MODULE_LICENSE("GPL");