]> Git Repo - linux.git/blame - arch/arm/mach-shmobile/intc-sh7372.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branches 'ib-mfd-gpio-i2c-3.19', 'ib-mfd-iio-3.19' and 'ib-mfd-regulator-v3...
[linux.git] / arch / arm / mach-shmobile / intc-sh7372.c
CommitLineData
e4e430c6
MD		 1/*
2 * sh7372 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
012f825f 22#include <linux/module.h>
e4e430c6
MD		 23#include <linux/irq.h>
24#include <linux/io.h>
e4e430c6
MD		 25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
6200e2c1 27#include "intc.h"
b6bab126 28#include "irqs.h"
e4e430c6
MD		 29
30enum {
31 UNUSED_INTCA = 0,
32
33 /* interrupt sources INTCA */
e4e430c6
MD		 34 DIRC,
35 CRYPT_STD,
36 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
37 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
38 MFI_MFIM, MFI_MFIS,
39 BBIF1, BBIF2,
deded435 40 USBHSDMAC0_USHDMI,
e4e430c6
MD		 41 _3DG_SGX540,
42 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
43 KEYSC_KEY,
44 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
45 MSIOF2, MSIOF1,
46 SCIFA4, SCIFA5, SCIFB,
47 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
2007aea1
SH		 48 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
49 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
e4e430c6
MD		 50 IRREM,
51 IRDA,
52 TPU0,
53 TTI20,
54 DDM,
2007aea1 55 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
e4e430c6 56 RWDT0,
deded435
KM		 57 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
58 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
e4e430c6
MD		 59 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
60 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
61 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
62 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
63 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
64 HDMI,
65 SPU2_SPU0, SPU2_SPU1,
66 FSI, FMSI,
67 MIPI_HSI,
68 IPMMU_IPMMUD,
deded435 69 CEC_1, CEC_2,
e4e430c6
MD		 70 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
71 MFIS2,
72 CPORTR2S,
73 CMT14, CMT15,
74 MMC_MMC_ERR, MMC_MMC_NOR,
75 IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
76 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
77 USB0_USB0I1, USB0_USB0I0,
78 USB1_USB1I1, USB1_USB1I0,
deded435 79 USBHSDMAC1_USHDMI,
e4e430c6
MD		 80
81 /* interrupt groups INTCA */
deded435 82 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
2007aea1 83 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
e4e430c6
MD		 84};
85
deded435 86static struct intc_vect intca_vectors[] __initdata = {
e4e430c6
MD		 87 INTC_VECT(DIRC, 0x0560),
88 INTC_VECT(CRYPT_STD, 0x0700),
89 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
90 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
91 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
92 INTC_VECT(AP_ARM_COMMRX, 0x0860),
93 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
94 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
deded435 95 INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
e4e430c6
MD		 96 INTC_VECT(_3DG_SGX540, 0x0a60),
97 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
98 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
99 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
100 INTC_VECT(KEYSC_KEY, 0x0be0),
101 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
102 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
103 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
104 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
105 INTC_VECT(SCIFB, 0x0d60),
106 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
107 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
2007aea1
SH		 108 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
109 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
110 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
111 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
e4e430c6
MD		 112 INTC_VECT(IRREM, 0x0f60),
113 INTC_VECT(IRDA, 0x0480),
114 INTC_VECT(TPU0, 0x04a0),
115 INTC_VECT(TTI20, 0x1100),
116 INTC_VECT(DDM, 0x1140),
2007aea1
SH		 117 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
118 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
e4e430c6 119 INTC_VECT(RWDT0, 0x1280),
deded435
KM		 120 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
121 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
122 INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
123 INTC_VECT(DMAC1_2_DADERR, 0x20c0),
e4e430c6
MD		 124 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
125 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
126 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
127 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
128 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
129 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
130 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
131 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
deded435 132 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
e4e430c6
MD		 133 INTC_VECT(SHWYSTAT_COM, 0x1340),
134 INTC_VECT(HDMI, 0x17e0),
135 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
136 INTC_VECT(FSI, 0x1840),
137 INTC_VECT(FMSI, 0x1860),
138 INTC_VECT(MIPI_HSI, 0x18e0),
139 INTC_VECT(IPMMU_IPMMUD, 0x1920),
deded435 140 INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
e4e430c6
MD		 141 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
142 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
143 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
144 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
145 INTC_VECT(MFIS2, 0x1a00),
146 INTC_VECT(CPORTR2S, 0x1a20),
147 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
148 INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
149 INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
150 INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
151 INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
152 INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
153 INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
154 INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
deded435 155 INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
e4e430c6
MD		 156};
157
158static struct intc_group intca_groups[] __initdata = {
deded435
KM		 159 INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
160 DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
161 INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
162 DMAC1_2_DEI5, DMAC1_2_DADERR),
e4e430c6
MD		 163 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
164 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
165 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
166 DMAC2_2_DEI5, DMAC2_2_DADERR),
167 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
168 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
169 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
170 DMAC3_2_DEI5, DMAC3_2_DADERR),
deded435
KM		 171 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
172 INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
173 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
e4e430c6
MD		 174 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
175 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
176 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
177 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
2007aea1
SH		 178 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
179 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
180 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
181 SDHI1_SDHI1I2),
182 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
183 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
e4e430c6
MD		 184 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
185};
186
deded435 187static struct intc_mask_reg intca_mask_registers[] __initdata = {
e4e430c6
MD		 188 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
189 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
190 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
191 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
192 { 0, CRYPT_STD, DIRC, 0,
deded435 193 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
e4e430c6
MD		 194 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
195 { 0, 0, 0, 0,
196 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
197 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
198 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
199 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
200 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
201 { DDM, 0, 0, 0,
202 0, 0, 0, 0 } },
203 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
deded435 204 { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
e4e430c6
MD		 205 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
206 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
207 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
208 0, 0, MSIOF2, 0 } },
209 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
2007aea1 210 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
e4e430c6
MD		 211 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
212 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
2007aea1 213 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
deded435 214 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
e4e430c6
MD		 215 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
216 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
217 CMT2, 0, 0, _3DG_SGX540 } },
218 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
219 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
220 0, 0, 0, 0 } },
221 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
222 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
223 0, 0, IRREM, 0 } },
224 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
225 { 0, 0, TPU0, 0,
226 0, 0, 0, 0 } },
227 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
2007aea1 228 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
e4e430c6
MD		 229 0, CMT3, 0, RWDT0 } },
230 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
231 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
232 0, 0, 0, 0 } },
233 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
234 { 0, 0, 0, 0,
235 0, 0, 0, HDMI } },
236 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
237 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
238 0, 0, 0, MIPI_HSI } },
239 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
deded435 240 { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
e4e430c6
MD		 241 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
242 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
243 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
244 { MFIS2, CPORTR2S, CMT14, CMT15,
245 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
246 { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
247 { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
248 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
249 { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
250 { 0, 0, 0, 0,
251 USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
252 { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
deded435 253 { USBHSDMAC1_USHDMI, 0, 0, 0,
e4e430c6
MD		 254 0, 0, 0, 0 } },
255};
256
deded435 257static struct intc_prio_reg intca_prio_registers[] __initdata = {
e4e430c6
MD		 258 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
259 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
260 { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
261 CMT1_CMT11, AP_ARM1 } },
262 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
263 CMT1_CMT12, 0 } },
deded435 264 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
e4e430c6 265 MFI_MFIM, 0 } },
deded435 266 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
e4e430c6
MD		 267 _3DG_SGX540, CMT1_CMT10 } },
268 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
269 SCIFA2, SCIFA3 } },
deded435 270 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
e4e430c6 271 FLCTL, SDHI0 } },
deded435
KM		 272 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
273 0/* MSU */, IIC1 } },
274 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
275 0/* MSUG */, TTI20 } },
e4e430c6
MD		 276 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
277 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
278 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
279 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
280 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
281 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
282 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
283 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
284 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
285 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
deded435 286 CEC_1, CEC_2 } },
e4e430c6
MD		 287 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
288 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
289 CMT14, CMT15 } },
0fff9ec1 290 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
e4e430c6 291 MMC_MMC_ERR, MMC_MMC_NOR } },
0fff9ec1 292 { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
e4e430c6 293 IIC4_WAITI4, IIC4_DTEI4 } },
0fff9ec1 294 { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
e4e430c6 295 IIC3_WAITI3, IIC3_DTEI3 } },
0fff9ec1 296 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
deded435 297 0/*TXI*/, 0/*TEI*/} },
0fff9ec1 298 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
e4e430c6 299 USB1_USB1I1, USB1_USB1I0 } },
0fff9ec1 300 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
e4e430c6
MD		 301};
302
da5713ef
MD		 303static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
304 intca_vectors, intca_groups,
305 intca_mask_registers, intca_prio_registers,
306 NULL);
e4e430c6 307
2ff6530c
MD		 308INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000,
309 INTC_VECT, "sh7372-intca-irq-lo");
310
311INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000,
312 INTC_VECT, "sh7372-intca-irq-hi");
313
f4dd6185
MD		 314enum {
315 UNUSED_INTCS = 0,
a2bc19e5 316 ENABLED_INTCS,
f4dd6185 317
f4dd6185 318 /* interrupt sources INTCS */
7923ac13
KM		 319
320 /* IRQ0S - IRQ31S */
f4dd6185
MD		 321 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
322 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
323 CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
7923ac13
KM		 324 /* MFI */
325 /* BBIF2 */
f4dd6185
MD		 326 VPU,
327 TSIF1,
4861da4f 328 /* 3DG */
f4dd6185
MD		 329 _2DDMAC,
330 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
331 IPMMU_IPMMUR, IPMMU_IPMMUR2,
332 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
7923ac13
KM		 333 /* KEYSC */
334 /* TTI20 */
f4dd6185
MD		 335 MSIOF,
336 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
337 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
338 CMT0,
339 TSIF0,
7923ac13 340 /* CMT2 */
f4dd6185
MD		 341 LMB,
342 CTI,
7923ac13 343 /* RWDT0 */
f4dd6185
MD		 344 ICB,
345 JPU_JPEG,
346 LCDC,
347 LCRC,
348 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
349 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
350 ISP,
351 LCDC1,
352 CSIRX,
353 DSITX_DSITX0,
354 DSITX_DSITX1,
7923ac13
KM		 355 /* SPU2 */
356 /* FSI */
357 /* FMSI */
358 /* HDMI */
f4dd6185
MD		 359 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
360 CMT4,
361 DSITX1_DSITX1_0,
362 DSITX1_DSITX1_1,
a2bc19e5 363 MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
f4dd6185 364 CPORTS2R,
7923ac13 365 /* CEC */
f4dd6185
MD		 366 JPU6E,
367
368 /* interrupt groups INTCS */
369 RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
370 RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
371};
372
373static struct intc_vect intcs_vectors[] = {
7923ac13 374 /* IRQ0S - IRQ31S */
f4dd6185
MD		 375 INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
376 INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
377 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
378 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
379 INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
380 INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
7923ac13
KM		 381 /* MFI */
382 /* BBIF2 */
f4dd6185
MD		 383 INTCS_VECT(VPU, 0x980),
384 INTCS_VECT(TSIF1, 0x9a0),
4861da4f 385 /* 3DG */
f4dd6185
MD		 386 INTCS_VECT(_2DDMAC, 0xa00),
387 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
388 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
389 INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
390 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
391 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
7923ac13
KM		 392 /* KEYSC */
393 /* TTI20 */
394 INTCS_VECT(MSIOF, 0x0d20),
f4dd6185
MD		 395 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
396 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
397 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
398 INTCS_VECT(TMU_TUNI2, 0xec0),
399 INTCS_VECT(CMT0, 0xf00),
400 INTCS_VECT(TSIF0, 0xf20),
7923ac13 401 /* CMT2 */
f4dd6185
MD		 402 INTCS_VECT(LMB, 0xf60),
403 INTCS_VECT(CTI, 0x400),
7923ac13 404 /* RWDT0 */
f4dd6185
MD		 405 INTCS_VECT(ICB, 0x480),
406 INTCS_VECT(JPU_JPEG, 0x560),
407 INTCS_VECT(LCDC, 0x580),
408 INTCS_VECT(LCRC, 0x5a0),
409 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
410 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
411 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
412 INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
413 INTCS_VECT(ISP, 0x1720),
414 INTCS_VECT(LCDC1, 0x1780),
415 INTCS_VECT(CSIRX, 0x17a0),
416 INTCS_VECT(DSITX_DSITX0, 0x17c0),
417 INTCS_VECT(DSITX_DSITX1, 0x17e0),
7923ac13
KM		 418 /* SPU2 */
419 /* FSI */
420 /* FMSI */
421 /* HDMI */
f4dd6185
MD		 422 INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
423 INTCS_VECT(TMU1_TUNI2, 0x1940),
424 INTCS_VECT(CMT4, 0x1980),
425 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
426 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
a2bc19e5 427 INTCS_VECT(MFIS2_INTCS, 0x1a00),
f4dd6185 428 INTCS_VECT(CPORTS2R, 0x1a20),
7923ac13 429 /* CEC */
f4dd6185 430 INTCS_VECT(JPU6E, 0x1a80),
f4dd6185
MD		 431};
432
433static struct intc_group intcs_groups[] __initdata = {
434 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
435 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
436 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
437 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
438 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
439 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
440 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
441 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
442 INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
443 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
444 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
445 RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
446 INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
447 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
448};
449
450static struct intc_mask_reg intcs_mask_registers[] = {
451 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
452 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
453 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
454 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
455 { 0, 0, 0, VPU,
456 0, 0, 0, 0 } },
457 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
458 { 0, 0, 0, _2DDMAC,
459 0, 0, 0, ICB } },
460 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
461 { 0, 0, 0, CTI,
462 JPU_JPEG, 0, LCRC, LCDC } },
463 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
464 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
465 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
466 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
467 { 0, 0, MSIOF, 0,
4861da4f 468 0, 0, 0, 0 } },
f4dd6185
MD		 469 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
470 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
471 0, 0, 0, 0 } },
472 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
473 { 0, 0, 0, CMT0,
474 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
475 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
476 { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
477 0, 0, 0, 0 } },
478 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
479 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
480 0, TSIF1, LMB, TSIF0 } },
481 { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
482 { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
483 RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
484 { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
485 { 0, ISP, 0, 0,
486 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
487 { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
488 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
489 CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
490 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
a2bc19e5 491 { MFIS2_INTCS, CPORTS2R, 0, 0,
f4dd6185 492 JPU6E, 0, 0, 0 } },
f4dd6185
MD		 493};
494
495/* Priority is needed for INTCA to receive the INTCS interrupt */
496static struct intc_prio_reg intcs_prio_registers[] = {
497 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
498 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
499 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
500 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
501 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
502 TMU_TUNI2, TSIF1 } },
503 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
504 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
f4dd6185
MD		 505 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
506 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
507 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
508 { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
509 { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
510 { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
511 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
512 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
513 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
514 DSITX1_DSITX1_1, 0 } },
a2bc19e5
MD		 515 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
516 0, 0 } },
f4dd6185
MD		 517 { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
518};
519
520static struct resource intcs_resources[] __initdata = {
521 [0] = {
522 .start = 0xffd20000,
523 .end = 0xffd201ff,
524 .flags = IORESOURCE_MEM,
525 },
526 [1] = {
527 .start = 0xffd50000,
528 .end = 0xffd501ff,
529 .flags = IORESOURCE_MEM,
530 }
531};
532
533static struct intc_desc intcs_desc __initdata = {
534 .name = "sh7372-intcs",
a2bc19e5 535 .force_enable = ENABLED_INTCS,
0f966d74 536 .skip_syscore_suspend = true,
f4dd6185
MD		 537 .resource = intcs_resources,
538 .num_resources = ARRAY_SIZE(intcs_resources),
539 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
540 intcs_prio_registers, NULL, NULL),
541};
542
543static void intcs_demux(unsigned int irq, struct irq_desc *desc)
544{
6845664a 545 void __iomem *reg = (void *)irq_get_handler_data(irq);
f4dd6185
MD		 546 unsigned int evtcodeas = ioread32(reg);
547
548 generic_handle_irq(intcs_evt2irq(evtcodeas));
549}
550
382414b9
MD		 551static void __iomem *intcs_ffd2;
552static void __iomem *intcs_ffd5;
553
e4e430c6
MD		 554void __init sh7372_init_irq(void)
555{
382414b9 556 void __iomem *intevtsa;
012f825f 557 int n;
382414b9
MD		 558
559 intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
560 intevtsa = intcs_ffd2 + 0x100;
561 intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
f4dd6185 562
e4e430c6 563 register_intc_controller(&intca_desc);
2ff6530c
MD		 564 register_intc_controller(&intca_irq_pins_lo_desc);
565 register_intc_controller(&intca_irq_pins_hi_desc);
f4dd6185
MD		 566 register_intc_controller(&intcs_desc);
567
012f825f
MD		 568 /* setup dummy cascade chip for INTCS */
569 n = evt2irq(0xf80);
570 irq_alloc_desc_at(n, numa_node_id());
571 irq_set_chip_and_handler_name(n, &dummy_irq_chip,
572 handle_level_irq, "level");
573 set_irq_flags(n, IRQF_VALID); /* yuck */
574
f4dd6185 575 /* demux using INTEVTSA */
012f825f
MD		 576 irq_set_handler_data(n, (void *)intevtsa);
577 irq_set_chained_handler(n, intcs_demux);
578
579 /* unmask INTCS in INTAMASK */
580 iowrite16(0, intcs_ffd2 + 0x104);
e4e430c6 581}
382414b9
MD		 582
583static unsigned short ffd2[0x200];
584static unsigned short ffd5[0x100];
585
586void sh7372_intcs_suspend(void)
587{
588 int k;
589
590 for (k = 0x00; k <= 0x30; k += 4)
591 ffd2[k] = __raw_readw(intcs_ffd2 + k);
592
593 for (k = 0x80; k <= 0xb0; k += 4)
594 ffd2[k] = __raw_readb(intcs_ffd2 + k);
595
596 for (k = 0x180; k <= 0x188; k += 4)
597 ffd2[k] = __raw_readb(intcs_ffd2 + k);
598
599 for (k = 0x00; k <= 0x3c; k += 4)
600 ffd5[k] = __raw_readw(intcs_ffd5 + k);
601
602 for (k = 0x80; k <= 0x9c; k += 4)
603 ffd5[k] = __raw_readb(intcs_ffd5 + k);
604}
605
606void sh7372_intcs_resume(void)
607{
608 int k;
609
610 for (k = 0x00; k <= 0x30; k += 4)
611 __raw_writew(ffd2[k], intcs_ffd2 + k);
612
613 for (k = 0x80; k <= 0xb0; k += 4)
614 __raw_writeb(ffd2[k], intcs_ffd2 + k);
615
616 for (k = 0x180; k <= 0x188; k += 4)
617 __raw_writeb(ffd2[k], intcs_ffd2 + k);
618
619 for (k = 0x00; k <= 0x3c; k += 4)
620 __raw_writew(ffd5[k], intcs_ffd5 + k);
621
622 for (k = 0x80; k <= 0x9c; k += 4)
623 __raw_writeb(ffd5[k], intcs_ffd5 + k);
624}
f7dadb37 625
0a4b04dc
AB		 626#define E694_BASE IOMEM(0xe6940000)
627#define E695_BASE IOMEM(0xe6950000)
628
f7dadb37
MD		 629static unsigned short e694[0x200];
630static unsigned short e695[0x200];
631
632void sh7372_intca_suspend(void)
633{
634 int k;
635
636 for (k = 0x00; k <= 0x38; k += 4)
0a4b04dc 637 e694[k] = __raw_readw(E694_BASE + k);
f7dadb37
MD		 638
639 for (k = 0x80; k <= 0xb4; k += 4)
0a4b04dc 640 e694[k] = __raw_readb(E694_BASE + k);
f7dadb37
MD		 641
642 for (k = 0x180; k <= 0x1b4; k += 4)
0a4b04dc 643 e694[k] = __raw_readb(E694_BASE + k);
f7dadb37
MD		 644
645 for (k = 0x00; k <= 0x50; k += 4)
0a4b04dc 646 e695[k] = __raw_readw(E695_BASE + k);
f7dadb37
MD		 647
648 for (k = 0x80; k <= 0xa8; k += 4)
0a4b04dc 649 e695[k] = __raw_readb(E695_BASE + k);
f7dadb37
MD		 650
651 for (k = 0x180; k <= 0x1a8; k += 4)
0a4b04dc 652 e695[k] = __raw_readb(E695_BASE + k);
f7dadb37
MD		 653}
654
655void sh7372_intca_resume(void)
656{
657 int k;
658
659 for (k = 0x00; k <= 0x38; k += 4)
0a4b04dc 660 __raw_writew(e694[k], E694_BASE + k);
f7dadb37
MD		 661
662 for (k = 0x80; k <= 0xb4; k += 4)
0a4b04dc 663 __raw_writeb(e694[k], E694_BASE + k);
f7dadb37
MD		 664
665 for (k = 0x180; k <= 0x1b4; k += 4)
0a4b04dc 666 __raw_writeb(e694[k], E694_BASE + k);
f7dadb37
MD		 667
668 for (k = 0x00; k <= 0x50; k += 4)
0a4b04dc 669 __raw_writew(e695[k], E695_BASE + k);
f7dadb37
MD		 670
671 for (k = 0x80; k <= 0xa8; k += 4)
0a4b04dc 672 __raw_writeb(e695[k], E695_BASE + k);
f7dadb37
MD		 673
674 for (k = 0x180; k <= 0x1a8; k += 4)
0a4b04dc 675 __raw_writeb(e695[k], E695_BASE + k);
f7dadb37 676}
Empty description
This page took 0.329567 seconds and 4 git commands to generate.