[linux.git] / arch / arm / mach-shmobile / clock-r8a7778.c

/*
 * r8a7778 clock framework support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Kuninori Morimoto <[email protected]>
 *
 * based on r8a7779
 *
 * Copyright (C) 2011  Renesas Solutions Corp.
 * Copyright (C) 2011  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/*
 *     MD      MD      MD      MD       PLLA   PLLB    EXTAL   clki    clkz
 *     19      18      12      11                      (HMz)   (MHz)   (MHz)
 *----------------------------------------------------------------------------
 *     1       0       0       0       x21     x21     38.00   800     800
 *     1       0       0       1       x24     x24     33.33   800     800
 *     1       0       1       0       x28     x28     28.50   800     800
 *     1       0       1       1       x32     x32     25.00   800     800
 *     1       1       0       1       x24     x21     33.33   800     700
 *     1       1       1       0       x28     x21     28.50   800     600
 *     1       1       1       1       x32     x24     25.00   800     600
 */

#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include "clock.h"
#include "common.h"

#define MSTPCR0		IOMEM(0xffc80030)
#define MSTPCR1		IOMEM(0xffc80034)
#define MSTPCR3		IOMEM(0xffc8003c)
#define MSTPSR1		IOMEM(0xffc80044)
#define MSTPSR4		IOMEM(0xffc80048)
#define MSTPSR6		IOMEM(0xffc8004c)
#define MSTPCR4		IOMEM(0xffc80050)
#define MSTPCR5		IOMEM(0xffc80054)
#define MSTPCR6		IOMEM(0xffc80058)
#define MODEMR		0xFFCC0020

#define MD(nr)	BIT(nr)

/* ioremap() through clock mapping mandatory to avoid
 * collision with ARM coherent DMA virtual memory range.
 */

static struct clk_mapping cpg_mapping = {
	.phys	= 0xffc80000,
	.len	= 0x80,
};

static struct clk extal_clk = {
	/* .rate will be updated on r8a7778_clock_init() */
	.mapping = &cpg_mapping,
};

static struct clk audio_clk_a = {
};

static struct clk audio_clk_b = {
};

static struct clk audio_clk_c = {
};

/*
 * clock ratio of these clock will be updated
 * on r8a7778_clock_init()
 */
SH_FIXED_RATIO_CLK_SET(plla_clk,	extal_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(pllb_clk,	extal_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(i_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(s_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(s1_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(s3_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(s4_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(b_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(out_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(p_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(g_clk,		plla_clk,  1, 1);
SH_FIXED_RATIO_CLK_SET(z_clk,		pllb_clk,  1, 1);

static struct clk *main_clks[] = {
	&extal_clk,
	&plla_clk,
	&pllb_clk,
	&i_clk,
	&s_clk,
	&s1_clk,
	&s3_clk,
	&s4_clk,
	&b_clk,
	&out_clk,
	&p_clk,
	&g_clk,
	&z_clk,
	&audio_clk_a,
	&audio_clk_b,
	&audio_clk_c,
};

enum {
	MSTP531, MSTP530,
	MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
	MSTP331,
	MSTP323, MSTP322, MSTP321,
	MSTP311, MSTP310,
	MSTP309, MSTP308, MSTP307,
	MSTP114,
	MSTP110, MSTP109,
	MSTP100,
	MSTP030,
	MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
	MSTP016, MSTP015, MSTP012, MSTP011, MSTP010,
	MSTP009, MSTP008, MSTP007,
	MSTP_NR };

static struct clk mstp_clks[MSTP_NR] = {
	[MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
	[MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
	[MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
	[MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
	[MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
	[MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
	[MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
	[MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
	[MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
	[MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
	[MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
	[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
	[MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
	[MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */
	[MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */
	[MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3,  9, 0), /* SSI6 */
	[MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3,  8, 0), /* SSI7 */
	[MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3,  7, 0), /* SSI8 */
	[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
	[MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
	[MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1,  9, 0), /* VIN1 */
	[MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1,  0, 0), /* USB0/1 */
	[MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */
	[MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */
	[MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */
	[MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */
	[MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
	[MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
	[MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
	[MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
	[MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
	[MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
	[MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
	[MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
	[MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */
	[MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */
	[MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */
	[MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0,  9, 0), /* SSI3 */
	[MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0,  8, 0), /* SRU */
	[MSTP007] = SH_CLK_MSTP32(&s_clk, MSTPCR0,  7, 0), /* HSPI */
};

static struct clk_lookup lookups[] = {
	/* main */
	CLKDEV_CON_ID("shyway_clk",	&s_clk),
	CLKDEV_CON_ID("peripheral_clk",	&p_clk),

	/* MSTP32 clocks */
	CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
	CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */
	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
	CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
	CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
	CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
	CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
	CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
	CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
	CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
	CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
	CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
	CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
	CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
	CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
	CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
	CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
	CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
	CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
	CLKDEV_DEV_ID("ffe40000.serial", &mstp_clks[MSTP026]), /* SCIF0 */
	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
	CLKDEV_DEV_ID("ffe41000.serial", &mstp_clks[MSTP025]), /* SCIF1 */
	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
	CLKDEV_DEV_ID("ffe42000.serial", &mstp_clks[MSTP024]), /* SCIF2 */
	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
	CLKDEV_DEV_ID("ffe43000.serial", &mstp_clks[MSTP023]), /* SCIF3 */
	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
	CLKDEV_DEV_ID("ffe44000.serial", &mstp_clks[MSTP022]), /* SCIF4 */
	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
	CLKDEV_DEV_ID("ffe45000.serial", &mstp_clks[MSTP021]), /* SCIF5 */
	CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
	CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
	CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
	CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
	CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
	CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
	CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */

	CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
	CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
	CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
	CLKDEV_ICK_ID("clk_i", "rcar_sound", &s1_clk),
	CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
	CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
	CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
	CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]),
	CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]),
	CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]),
	CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
	CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
	CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
	CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP531]),
	CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP530]),
	CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP529]),
	CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP528]),
	CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP527]),
	CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP526]),
	CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP525]),
	CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]),
	CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]),
	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]),
	CLKDEV_ICK_ID("fck", "ffd80000.timer", &mstp_clks[MSTP016]),
	CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]),
	CLKDEV_ICK_ID("fck", "ffd81000.timer", &mstp_clks[MSTP015]),
};

void __init r8a7778_clock_init(void)
{
	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
	u32 mode;
	int k, ret = 0;

	BUG_ON(!modemr);
	mode = ioread32(modemr);
	iounmap(modemr);

	switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
	case MD(19):
		extal_clk.rate = 38000000;
		SH_CLK_SET_RATIO(&plla_clk_ratio,	21, 1);
		SH_CLK_SET_RATIO(&pllb_clk_ratio,	21, 1);
		break;
	case MD(19) | MD(11):
		extal_clk.rate = 33333333;
		SH_CLK_SET_RATIO(&plla_clk_ratio,	24, 1);
		SH_CLK_SET_RATIO(&pllb_clk_ratio,	24, 1);
		break;
	case MD(19) | MD(12):
		extal_clk.rate = 28500000;
		SH_CLK_SET_RATIO(&plla_clk_ratio,	28, 1);
		SH_CLK_SET_RATIO(&pllb_clk_ratio,	28, 1);
		break;
	case MD(19) | MD(12) | MD(11):
		extal_clk.rate = 25000000;
		SH_CLK_SET_RATIO(&plla_clk_ratio,	32, 1);
		SH_CLK_SET_RATIO(&pllb_clk_ratio,	32, 1);
		break;
	case MD(19) | MD(18) | MD(11):
		extal_clk.rate = 33333333;
		SH_CLK_SET_RATIO(&plla_clk_ratio,	24, 1);
		SH_CLK_SET_RATIO(&pllb_clk_ratio,	21, 1);
		break;
	case MD(19) | MD(18) | MD(12):
		extal_clk.rate = 28500000;
		SH_CLK_SET_RATIO(&plla_clk_ratio,	28, 1);
		SH_CLK_SET_RATIO(&pllb_clk_ratio,	21, 1);
		break;
	case MD(19) | MD(18) | MD(12) | MD(11):
		extal_clk.rate = 25000000;
		SH_CLK_SET_RATIO(&plla_clk_ratio,	32, 1);
		SH_CLK_SET_RATIO(&pllb_clk_ratio,	24, 1);
		break;
	default:
		BUG();
	}

	if (mode & MD(1)) {
		SH_CLK_SET_RATIO(&i_clk_ratio,	1, 1);
		SH_CLK_SET_RATIO(&s_clk_ratio,	1, 3);
		SH_CLK_SET_RATIO(&s1_clk_ratio,	1, 6);
		SH_CLK_SET_RATIO(&s3_clk_ratio,	1, 4);
		SH_CLK_SET_RATIO(&s4_clk_ratio,	1, 8);
		SH_CLK_SET_RATIO(&p_clk_ratio,	1, 12);
		SH_CLK_SET_RATIO(&g_clk_ratio,	1, 12);
		if (mode & MD(2)) {
			SH_CLK_SET_RATIO(&b_clk_ratio,		1, 18);
			SH_CLK_SET_RATIO(&out_clk_ratio,	1, 18);
		} else {
			SH_CLK_SET_RATIO(&b_clk_ratio,		1, 12);
			SH_CLK_SET_RATIO(&out_clk_ratio,	1, 12);
		}
	} else {
		SH_CLK_SET_RATIO(&i_clk_ratio,	1, 1);
		SH_CLK_SET_RATIO(&s_clk_ratio,	1, 4);
		SH_CLK_SET_RATIO(&s1_clk_ratio,	1, 8);
		SH_CLK_SET_RATIO(&s3_clk_ratio,	1, 4);
		SH_CLK_SET_RATIO(&s4_clk_ratio,	1, 8);
		SH_CLK_SET_RATIO(&p_clk_ratio,	1, 16);
		SH_CLK_SET_RATIO(&g_clk_ratio,	1, 12);
		if (mode & MD(2)) {
			SH_CLK_SET_RATIO(&b_clk_ratio,		1, 16);
			SH_CLK_SET_RATIO(&out_clk_ratio,	1, 16);
		} else {
			SH_CLK_SET_RATIO(&b_clk_ratio,		1, 12);
			SH_CLK_SET_RATIO(&out_clk_ratio,	1, 12);
		}
	}

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	if (!ret)
		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		shmobile_clk_init();
	else
		panic("failed to setup r8a7778 clocks\n");
}
Commit	Line	Data
ccb7cc74 KM	1	/*
	2	* r8a7778 clock framework support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Kuninori Morimoto <[email protected]>
	6	*
	7	* based on r8a7779
	8	*
	9	* Copyright (C) 2011 Renesas Solutions Corp.
	10	* Copyright (C) 2011 Magnus Damm
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2 of the License
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	24	*/
	25
08b93ec1 KM	26	/*
	27	* MD MD MD MD PLLA PLLB EXTAL clki clkz
	28	* 19 18 12 11 (HMz) (MHz) (MHz)
	29	*----------------------------------------------------------------------------
	30	* 1 0 0 0 x21 x21 38.00 800 800
	31	* 1 0 0 1 x24 x24 33.33 800 800
	32	* 1 0 1 0 x28 x28 28.50 800 800
	33	* 1 0 1 1 x32 x32 25.00 800 800
	34	* 1 1 0 1 x24 x21 33.33 800 700
	35	* 1 1 1 0 x28 x21 28.50 800 600
	36	* 1 1 1 1 x32 x24 25.00 800 600
	37	*/
	38
ccb7cc74 KM	39	#include <linux/io.h>
	40	#include <linux/sh_clk.h>
	41	#include <linux/clkdev.h>
ad6ffa0b	42	#include "clock.h"
fd44aa5e	43	#include "common.h"
ccb7cc74 KM	44
	45	#define MSTPCR0 IOMEM(0xffc80030)
	46	#define MSTPCR1 IOMEM(0xffc80034)
	47	#define MSTPCR3 IOMEM(0xffc8003c)
	48	#define MSTPSR1 IOMEM(0xffc80044)
	49	#define MSTPSR4 IOMEM(0xffc80048)
	50	#define MSTPSR6 IOMEM(0xffc8004c)
	51	#define MSTPCR4 IOMEM(0xffc80050)
	52	#define MSTPCR5 IOMEM(0xffc80054)
	53	#define MSTPCR6 IOMEM(0xffc80058)
08b93ec1 KM	54	#define MODEMR 0xFFCC0020
	55
	56	#define MD(nr) BIT(nr)
ccb7cc74 KM	57
	58	/* ioremap() through clock mapping mandatory to avoid
	59	* collision with ARM coherent DMA virtual memory range.
	60	*/
	61
	62	static struct clk_mapping cpg_mapping = {
	63	.phys = 0xffc80000,
	64	.len = 0x80,
	65	};
	66
08b93ec1 KM	67	static struct clk extal_clk = {
08b93ec1 KM	68	/* .rate will be updated on r8a7778_clock_init() */
ccb7cc74 KM	69	.mapping = &cpg_mapping,
	70	};
	71
a93c2aaf KM	72	static struct clk audio_clk_a = {
	73	};
	74
	75	static struct clk audio_clk_b = {
	76	};
	77
	78	static struct clk audio_clk_c = {
	79	};
	80
08b93ec1 KM	81	/*
	82	* clock ratio of these clock will be updated
	83	* on r8a7778_clock_init()
	84	*/
	85	SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1);
	86	SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1);
	87	SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1);
	88	SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1);
	89	SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1);
	90	SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1);
	91	SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1);
	92	SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1);
	93	SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1);
	94	SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1);
	95	SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1);
	96	SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1);
	97
ccb7cc74	98	static struct clk *main_clks[] = {
08b93ec1 KM	99	&extal_clk,
	100	&plla_clk,
	101	&pllb_clk,
	102	&i_clk,
	103	&s_clk,
	104	&s1_clk,
	105	&s3_clk,
	106	&s4_clk,
	107	&b_clk,
	108	&out_clk,
	109	&p_clk,
	110	&g_clk,
	111	&z_clk,
a93c2aaf KM	112	&audio_clk_a,
	113	&audio_clk_b,
	114	&audio_clk_c,
ccb7cc74 KM	115	};
	116
	117	enum {
950c4477 KM	118	MSTP531, MSTP530,
950c4477 KM	119	MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
2ad3c8eb	120	MSTP331,
1189b1cb	121	MSTP323, MSTP322, MSTP321,
a93c2aaf KM	122	MSTP311, MSTP310,
a93c2aaf KM	123	MSTP309, MSTP308, MSTP307,
52421914	124	MSTP114,
803c2df2	125	MSTP110, MSTP109,
02474a41	126	MSTP100,
b6bb9a64 KM	127	MSTP030,
b6bb9a64 KM	128	MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
a93c2aaf KM	129	MSTP016, MSTP015, MSTP012, MSTP011, MSTP010,
a93c2aaf KM	130	MSTP009, MSTP008, MSTP007,
ccb7cc74 KM	131	MSTP_NR };
	132
	133	static struct clk mstp_clks[MSTP_NR] = {
950c4477 KM	134	[MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
	135	[MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
	136	[MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
	137	[MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
	138	[MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
	139	[MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
	140	[MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
	141	[MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
	142	[MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
2ad3c8eb	143	[MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
1189b1cb KM	144	[MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
	145	[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
	146	[MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
a93c2aaf KM	147	[MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */
	148	[MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */
	149	[MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 9, 0), /* SSI6 */
	150	[MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 8, 0), /* SSI7 */
	151	[MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 7, 0), /* SSI8 */
08b93ec1	152	[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
803c2df2 VB	153	[MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
803c2df2 VB	154	[MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */
02474a41	155	[MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */
b6bb9a64 KM	156	[MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */
	157	[MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */
	158	[MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */
	159	[MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */
08b93ec1 KM	160	[MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
	161	[MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
	162	[MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
	163	[MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
	164	[MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
	165	[MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
	166	[MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
	167	[MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
a93c2aaf KM	168	[MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */
	169	[MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */
	170	[MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */
	171	[MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */
	172	[MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */
3dedc5f5	173	[MSTP007] = SH_CLK_MSTP32(&s_clk, MSTPCR0, 7, 0), /* HSPI */
ccb7cc74 KM	174	};
	175
	176	static struct clk_lookup lookups[] = {
b6bb9a64	177	/* main */
3dd691ef	178	CLKDEV_CON_ID("shyway_clk", &s_clk),
b6bb9a64 KM	179	CLKDEV_CON_ID("peripheral_clk", &p_clk),
b6bb9a64 KM	180
ccb7cc74	181	/* MSTP32 clocks */
2ad3c8eb	182	CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
14e1d914	183	CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */
1189b1cb	184	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
14e1d914	185	CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
1189b1cb	186	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
14e1d914	187	CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
1189b1cb	188	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
14e1d914	189	CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
589ebdef	190	CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
803c2df2 VB	191	CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
803c2df2 VB	192	CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
02474a41 SS	193	CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
02474a41 SS	194	CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
84ea5288	195	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
b6bb9a64	196	CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
10ef80fa	197	CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
b6bb9a64	198	CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
10ef80fa	199	CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
b6bb9a64	200	CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
10ef80fa	201	CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
b6bb9a64	202	CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
10ef80fa	203	CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
db331fc8	204	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
7a0c9947	205	CLKDEV_DEV_ID("ffe40000.serial", &mstp_clks[MSTP026]), /* SCIF0 */
db331fc8	206	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
7a0c9947	207	CLKDEV_DEV_ID("ffe41000.serial", &mstp_clks[MSTP025]), /* SCIF1 */
db331fc8	208	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
7a0c9947	209	CLKDEV_DEV_ID("ffe42000.serial", &mstp_clks[MSTP024]), /* SCIF2 */
db331fc8	210	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
7a0c9947	211	CLKDEV_DEV_ID("ffe43000.serial", &mstp_clks[MSTP023]), /* SCIF3 */
db331fc8	212	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
7a0c9947	213	CLKDEV_DEV_ID("ffe44000.serial", &mstp_clks[MSTP022]), /* SCIF4 */
db331fc8	214	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
7a0c9947	215	CLKDEV_DEV_ID("ffe45000.serial", &mstp_clks[MSTP021]), /* SCIF5 */
3dd691ef	216	CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
6c334d23	217	CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
3dd691ef	218	CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
6c334d23	219	CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
3dd691ef	220	CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
6c334d23	221	CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
a93c2aaf KM	222	CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
a93c2aaf KM	223
ba349c08 KM	224	CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
	225	CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
	226	CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
	227	CLKDEV_ICK_ID("clk_i", "rcar_sound", &s1_clk),
a93c2aaf KM	228	CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
	229	CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
	230	CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
	231	CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]),
	232	CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]),
	233	CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]),
	234	CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
	235	CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
	236	CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
a9d83bd6 KM	237	CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP531]),
	238	CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP530]),
	239	CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP529]),
	240	CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP528]),
	241	CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP527]),
	242	CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP526]),
	243	CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP525]),
	244	CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]),
	245	CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]),
535ef0d9	246	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]),
0985f38d	247	CLKDEV_ICK_ID("fck", "ffd80000.timer", &mstp_clks[MSTP016]),
535ef0d9	248	CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]),
0985f38d	249	CLKDEV_ICK_ID("fck", "ffd81000.timer", &mstp_clks[MSTP015]),
ccb7cc74 KM	250	};
	251
	252	void __init r8a7778_clock_init(void)
	253	{
08b93ec1 KM	254	void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
08b93ec1 KM	255	u32 mode;
ccb7cc74 KM	256	int k, ret = 0;
ccb7cc74 KM	257
08b93ec1 KM	258	BUG_ON(!modemr);
	259	mode = ioread32(modemr);
	260	iounmap(modemr);
	261
	262	switch (mode & (MD(19) \| MD(18) \| MD(12) \| MD(11))) {
	263	case MD(19):
	264	extal_clk.rate = 38000000;
	265	SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1);
	266	SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
	267	break;
	268	case MD(19) \| MD(11):
	269	extal_clk.rate = 33333333;
	270	SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
	271	SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
	272	break;
	273	case MD(19) \| MD(12):
	274	extal_clk.rate = 28500000;
	275	SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
	276	SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1);
	277	break;
	278	case MD(19) \| MD(12) \| MD(11):
	279	extal_clk.rate = 25000000;
	280	SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
	281	SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1);
	282	break;
	283	case MD(19) \| MD(18) \| MD(11):
	284	extal_clk.rate = 33333333;
	285	SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
	286	SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
	287	break;
	288	case MD(19) \| MD(18) \| MD(12):
	289	extal_clk.rate = 28500000;
	290	SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
	291	SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
	292	break;
	293	case MD(19) \| MD(18) \| MD(12) \| MD(11):
	294	extal_clk.rate = 25000000;
	295	SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
	296	SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
	297	break;
	298	default:
	299	BUG();
	300	}
	301
	302	if (mode & MD(1)) {
	303	SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
	304	SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3);
	305	SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
	306	SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
	307	SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
	308	SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12);
	309	SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
	310	if (mode & MD(2)) {
	311	SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18);
	312	SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18);
	313	} else {
	314	SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
	315	SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
	316	}
	317	} else {
	318	SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
	319	SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4);
	320	SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
	321	SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
322	SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
323	SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16);
324	SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
325	if (mode & MD(2)) {
326	SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16);
327	SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16);
328	} else {
329	SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
330	SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
331	}
332	}
333
ccb7cc74 KM	334	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	335	ret = clk_register(main_clks[k]);
	336
	337	if (!ret)
	338	ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
	339
	340	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	341
	342	if (!ret)
	343	shmobile_clk_init();
	344	else
	345	panic("failed to setup r8a7778 clocks\n");
	346	}