[linux.git] / drivers / media / dvb / frontends / stv0297.c

/*
    Driver for STV0297 demodulator

    Copyright (C) 2004 Andrew de Quincey <[email protected]>
    Copyright (C) 2003-2004 Dennis Noermann <[email protected]>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/slab.h>

#include "dvb_frontend.h"
#include "stv0297.h"

struct stv0297_state {
	struct i2c_adapter *i2c;
	struct dvb_frontend_ops ops;
	const struct stv0297_config *config;
	struct dvb_frontend frontend;

	unsigned long base_freq;
};

#if 1
#define dprintk(x...) printk(x)
#else
#define dprintk(x...)
#endif

#define STV0297_CLOCK_KHZ   28900


static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
{
	int ret;
	u8 buf[] = { reg, data };
	struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };

	ret = i2c_transfer(state->i2c, &msg, 1);

	if (ret != 1)
		dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
			"ret == %i)\n", __FUNCTION__, reg, data, ret);

	return (ret != 1) ? -1 : 0;
}

static int stv0297_readreg(struct stv0297_state *state, u8 reg)
{
	int ret;
	u8 b0[] = { reg };
	u8 b1[] = { 0 };
	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len =
				  1},
	{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
	};

	// this device needs a STOP between the register and data
	if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
		dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
		return -1;
	}
	if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
		dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
		return -1;
	}

	return b1[0];
}

static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
{
	int val;

	val = stv0297_readreg(state, reg);
	val &= ~mask;
	val |= (data & mask);
	stv0297_writereg(state, reg, val);

	return 0;
}

static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len)
{
	int ret;
	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
				  &reg1,.len = 1},
	{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
	};

	// this device needs a STOP between the register and data
	if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
		dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
		return -1;
	}
	if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
		dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
		return -1;
	}

	return 0;
}

static u32 stv0297_get_symbolrate(struct stv0297_state *state)
{
	u64 tmp;

	tmp = stv0297_readreg(state, 0x55);
	tmp |= stv0297_readreg(state, 0x56) << 8;
	tmp |= stv0297_readreg(state, 0x57) << 16;
	tmp |= stv0297_readreg(state, 0x58) << 24;

	tmp *= STV0297_CLOCK_KHZ;
	tmp >>= 32;

	return (u32) tmp;
}

static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
{
	long tmp;

	tmp = 131072L * srate;	/* 131072 = 2^17  */
	tmp = tmp / (STV0297_CLOCK_KHZ / 4);	/* 1/4 = 2^-2 */
	tmp = tmp * 8192L;	/* 8192 = 2^13 */

	stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
	stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
	stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
	stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
}

static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
{
	long tmp;

	tmp = (long) fshift *262144L;	/* 262144 = 2*18 */
	tmp /= symrate;
	tmp *= 1024;		/* 1024 = 2*10   */

	// adjust
	if (tmp >= 0) {
		tmp += 500000;
	} else {
		tmp -= 500000;
	}
	tmp /= 1000000;

	stv0297_writereg(state, 0x60, tmp & 0xFF);
	stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
}

static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
{
	long tmp;

	/* symrate is hardcoded to 10000 */
	tmp = offset * 26844L;	/* (2**28)/10000 */
	if (tmp < 0)
		tmp += 0x10000000;
	tmp &= 0x0FFFFFFF;

	stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
	stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
	stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
	stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
}

/*
static long stv0297_get_carrieroffset(struct stv0297_state *state)
{
	s64 tmp;

	stv0297_writereg(state, 0x6B, 0x00);

	tmp = stv0297_readreg(state, 0x66);
	tmp |= (stv0297_readreg(state, 0x67) << 8);
	tmp |= (stv0297_readreg(state, 0x68) << 16);
	tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;

	tmp *= stv0297_get_symbolrate(state);
	tmp >>= 28;

	return (s32) tmp;
}
*/

static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
{
	s32 tmp;

	if (freq > 10000)
		freq -= STV0297_CLOCK_KHZ;

	tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
	tmp = (freq * 1000) / tmp;
	if (tmp > 0xffff)
		tmp = 0xffff;

	stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
	stv0297_writereg(state, 0x21, tmp >> 8);
	stv0297_writereg(state, 0x20, tmp);
}

static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
{
	int val = 0;

	switch (modulation) {
	case QAM_16:
		val = 0;
		break;

	case QAM_32:
		val = 1;
		break;

	case QAM_64:
		val = 4;
		break;

	case QAM_128:
		val = 2;
		break;

	case QAM_256:
		val = 3;
		break;

	default:
		return -EINVAL;
	}

	stv0297_writereg_mask(state, 0x00, 0x70, val << 4);

	return 0;
}

static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
{
	int val = 0;

	switch (inversion) {
	case INVERSION_OFF:
		val = 0;
		break;

	case INVERSION_ON:
		val = 1;
		break;

	default:
		return -EINVAL;
	}

	stv0297_writereg_mask(state, 0x83, 0x08, val << 3);

	return 0;
}

int stv0297_enable_plli2c(struct dvb_frontend *fe)
{
	struct stv0297_state *state = fe->demodulator_priv;

	stv0297_writereg(state, 0x87, 0x78);
	stv0297_writereg(state, 0x86, 0xc8);

	return 0;
}

static int stv0297_init(struct dvb_frontend *fe)
{
	struct stv0297_state *state = fe->demodulator_priv;
	int i;

	/* load init table */
	for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
		stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
	msleep(200);

	if (state->config->pll_init)
		state->config->pll_init(fe);

	return 0;
}

static int stv0297_sleep(struct dvb_frontend *fe)
{
	struct stv0297_state *state = fe->demodulator_priv;

	stv0297_writereg_mask(state, 0x80, 1, 1);

	return 0;
}

static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status)
{
	struct stv0297_state *state = fe->demodulator_priv;

	u8 sync = stv0297_readreg(state, 0xDF);

	*status = 0;
	if (sync & 0x80)
		*status |=
			FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK;
	return 0;
}

static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber)
{
	struct stv0297_state *state = fe->demodulator_priv;
	u8 BER[3];

	stv0297_writereg(state, 0xA0, 0x80);	// Start Counting bit errors for 4096 Bytes
	mdelay(25);		// Hopefully got 4096 Bytes
	stv0297_readregs(state, 0xA0, BER, 3);
	mdelay(25);
	*ber = (BER[2] << 8 | BER[1]) / (8 * 4096);

	return 0;
}


static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
{
	struct stv0297_state *state = fe->demodulator_priv;
	u8 STRENGTH[2];

	stv0297_readregs(state, 0x41, STRENGTH, 2);
	*strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0];

	return 0;
}

static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr)
{
	struct stv0297_state *state = fe->demodulator_priv;
	u8 SNR[2];

	stv0297_readregs(state, 0x07, SNR, 2);
	*snr = SNR[1] << 8 | SNR[0];

	return 0;
}

static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
	struct stv0297_state *state = fe->demodulator_priv;

	*ucblocks = (stv0297_readreg(state, 0xD5) << 8)
		| stv0297_readreg(state, 0xD4);

	return 0;
}

static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
{
	struct stv0297_state *state = fe->demodulator_priv;
	int u_threshold;
	int initial_u;
	int blind_u;
	int delay;
	int sweeprate;
	int carrieroffset;
	unsigned long starttime;
	unsigned long timeout;
	fe_spectral_inversion_t inversion;

	switch (p->u.qam.modulation) {
	case QAM_16:
	case QAM_32:
	case QAM_64:
		delay = 100;
		sweeprate = 1500;
		break;

	case QAM_128:
	case QAM_256:
		delay = 200;
		sweeprate = 500;
		break;

	default:
		return -EINVAL;
	}

	// determine inversion dependant parameters
	inversion = p->inversion;
	if (state->config->invert)
		inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
	carrieroffset = -330;
	switch (inversion) {
	case INVERSION_OFF:
		break;

	case INVERSION_ON:
		sweeprate = -sweeprate;
		carrieroffset = -carrieroffset;
		break;

	default:
		return -EINVAL;
	}

	stv0297_init(fe);
	state->config->pll_set(fe, p);

	/* clear software interrupts */
	stv0297_writereg(state, 0x82, 0x0);

	/* set initial demodulation frequency */
	stv0297_set_initialdemodfreq(state, 7250);

	/* setup AGC */
	stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
	stv0297_writereg(state, 0x41, 0x00);
	stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
	stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
	stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
	stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
	stv0297_writereg(state, 0x72, 0x00);
	stv0297_writereg(state, 0x73, 0x00);
	stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
	stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
	stv0297_writereg_mask(state, 0x71, 0x80, 0x00);

	/* setup STL */
	stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
	stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
	stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
	stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
	stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);

	/* disable frequency sweep */
	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);

	/* reset deinterleaver */
	stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
	stv0297_writereg_mask(state, 0x81, 0x01, 0x00);

	/* ??? */
	stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
	stv0297_writereg_mask(state, 0x83, 0x20, 0x00);

	/* reset equaliser */
	u_threshold = stv0297_readreg(state, 0x00) & 0xf;
	initial_u = stv0297_readreg(state, 0x01) >> 4;
	blind_u = stv0297_readreg(state, 0x01) & 0xf;
	stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
	stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
	stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
	stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
	stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);

	/* data comes from internal A/D */
	stv0297_writereg_mask(state, 0x87, 0x80, 0x00);

	/* clear phase registers */
	stv0297_writereg(state, 0x63, 0x00);
	stv0297_writereg(state, 0x64, 0x00);
	stv0297_writereg(state, 0x65, 0x00);
	stv0297_writereg(state, 0x66, 0x00);
	stv0297_writereg(state, 0x67, 0x00);
	stv0297_writereg(state, 0x68, 0x00);
	stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);

	/* set parameters */
	stv0297_set_qam(state, p->u.qam.modulation);
	stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000);
	stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
	stv0297_set_carrieroffset(state, carrieroffset);
	stv0297_set_inversion(state, inversion);

	/* kick off lock */
	/* Disable corner detection for higher QAMs */
	if (p->u.qam.modulation == QAM_128 ||
		p->u.qam.modulation == QAM_256)
		stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
	else
		stv0297_writereg_mask(state, 0x88, 0x08, 0x08);

	stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
	stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
	stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
	stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
	stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
	stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
	stv0297_writereg_mask(state, 0x43, 0x10, 0x10);

	/* wait for WGAGC lock */
	starttime = jiffies;
	timeout = jiffies + msecs_to_jiffies(2000);
	while (time_before(jiffies, timeout)) {
		msleep(10);
		if (stv0297_readreg(state, 0x43) & 0x08)
			break;
	}
	if (time_after(jiffies, timeout)) {
		goto timeout;
	}
	msleep(20);

	/* wait for equaliser partial convergence */
	timeout = jiffies + msecs_to_jiffies(500);
	while (time_before(jiffies, timeout)) {
		msleep(10);

		if (stv0297_readreg(state, 0x82) & 0x04) {
			break;
		}
	}
	if (time_after(jiffies, timeout)) {
		goto timeout;
	}

	/* wait for equaliser full convergence */
	timeout = jiffies + msecs_to_jiffies(delay);
	while (time_before(jiffies, timeout)) {
		msleep(10);

		if (stv0297_readreg(state, 0x82) & 0x08) {
			break;
		}
	}
	if (time_after(jiffies, timeout)) {
		goto timeout;
	}

	/* disable sweep */
	stv0297_writereg_mask(state, 0x6a, 1, 0);
	stv0297_writereg_mask(state, 0x88, 8, 0);

	/* wait for main lock */
	timeout = jiffies + msecs_to_jiffies(20);
	while (time_before(jiffies, timeout)) {
		msleep(10);

		if (stv0297_readreg(state, 0xDF) & 0x80) {
			break;
		}
	}
	if (time_after(jiffies, timeout)) {
		goto timeout;
	}
	msleep(100);

	/* is it still locked after that delay? */
	if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
		goto timeout;
	}

	/* success!! */
	stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
	state->base_freq = p->frequency;
	return 0;

timeout:
	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
	return 0;
}

static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
{
	struct stv0297_state *state = fe->demodulator_priv;
	int reg_00, reg_83;

	reg_00 = stv0297_readreg(state, 0x00);
	reg_83 = stv0297_readreg(state, 0x83);

	p->frequency = state->base_freq;
	p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
	if (state->config->invert)
		p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
	p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000;
	p->u.qam.fec_inner = FEC_NONE;

	switch ((reg_00 >> 4) & 0x7) {
	case 0:
		p->u.qam.modulation = QAM_16;
		break;
	case 1:
		p->u.qam.modulation = QAM_32;
		break;
	case 2:
		p->u.qam.modulation = QAM_128;
		break;
	case 3:
		p->u.qam.modulation = QAM_256;
		break;
	case 4:
		p->u.qam.modulation = QAM_64;
		break;
	}

	return 0;
}

static void stv0297_release(struct dvb_frontend *fe)
{
	struct stv0297_state *state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops stv0297_ops;

struct dvb_frontend *stv0297_attach(const struct stv0297_config *config,
				    struct i2c_adapter *i2c)
{
	struct stv0297_state *state = NULL;

	/* allocate memory for the internal state */
	state = kmalloc(sizeof(struct stv0297_state), GFP_KERNEL);
	if (state == NULL)
		goto error;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	memcpy(&state->ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
	state->base_freq = 0;

	/* check if the demod is there */
	if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
		goto error;

	/* create dvb_frontend */
	state->frontend.ops = &state->ops;
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);
	return NULL;
}

static struct dvb_frontend_ops stv0297_ops = {

	.info = {
		 .name = "ST STV0297 DVB-C",
		 .type = FE_QAM,
		 .frequency_min = 64000000,
		 .frequency_max = 1300000000,
		 .frequency_stepsize = 62500,
		 .symbol_rate_min = 870000,
		 .symbol_rate_max = 11700000,
		 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
		 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},

	.release = stv0297_release,

	.init = stv0297_init,
	.sleep = stv0297_sleep,

	.set_frontend = stv0297_set_frontend,
	.get_frontend = stv0297_get_frontend,

	.read_status = stv0297_read_status,
	.read_ber = stv0297_read_ber,
	.read_signal_strength = stv0297_read_signal_strength,
	.read_snr = stv0297_read_snr,
	.read_ucblocks = stv0297_read_ucblocks,
};

MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(stv0297_attach);
EXPORT_SYMBOL(stv0297_enable_plli2c);
Commit	Line	Data
1da177e4 LT	1	/*
	2	Driver for STV0297 demodulator
	3
	4	Copyright (C) 2004 Andrew de Quincey <[email protected]>
	5	Copyright (C) 2003-2004 Dennis Noermann <[email protected]>
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*/
	21
	22	#include <linux/init.h>
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/string.h>
	26	#include <linux/delay.h>
4e57b681 TS	27	#include <linux/jiffies.h>
4e57b681 TS	28	#include <linux/slab.h>
1da177e4 LT	29
	30	#include "dvb_frontend.h"
	31	#include "stv0297.h"
	32
	33	struct stv0297_state {
	34	struct i2c_adapter *i2c;
	35	struct dvb_frontend_ops ops;
	36	const struct stv0297_config *config;
	37	struct dvb_frontend frontend;
	38
	39	unsigned long base_freq;
1da177e4 LT	40	};
	41
	42	#if 1
	43	#define dprintk(x...) printk(x)
	44	#else
	45	#define dprintk(x...)
	46	#endif
	47
	48	#define STV0297_CLOCK_KHZ 28900
	49
1da177e4 LT	50
	51	static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data)
	52	{
	53	int ret;
	54	u8 buf[] = { reg, data };
	55	struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 };
	56
	57	ret = i2c_transfer(state->i2c, &msg, 1);
	58
	59	if (ret != 1)
	60	dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
	61	"ret == %i)\n", __FUNCTION__, reg, data, ret);
	62
	63	return (ret != 1) ? -1 : 0;
	64	}
	65
	66	static int stv0297_readreg(struct stv0297_state *state, u8 reg)
	67	{
	68	int ret;
	69	u8 b0[] = { reg };
	70	u8 b1[] = { 0 };
	71	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len =
	72	1},
	73	{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
	74	};
	75
	76	// this device needs a STOP between the register and data
	77	if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
	78	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
	79	return -1;
	80	}
	81	if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
	82	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret);
	83	return -1;
	84	}
	85
	86	return b1[0];
	87	}
	88
	89	static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data)
	90	{
	91	int val;
	92
	93	val = stv0297_readreg(state, reg);
	94	val &= ~mask;
	95	val \|= (data & mask);
	96	stv0297_writereg(state, reg, val);
	97
	98	return 0;
	99	}
	100
	101	static int stv0297_readregs(struct stv0297_state state, u8 reg1, u8 b, u8 len)
	102	{
	103	int ret;
	104	struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf =
	105	&reg1,.len = 1},
	106	{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len}
	107	};
	108
	109	// this device needs a STOP between the register and data
	110	if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) {
	111	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
	112	return -1;
	113	}
114	if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) {
115	dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret);
116	return -1;
117	}
118
119	return 0;
120	}
121
122	static u32 stv0297_get_symbolrate(struct stv0297_state *state)
123	{
124	u64 tmp;
125
126	tmp = stv0297_readreg(state, 0x55);
127	tmp \|= stv0297_readreg(state, 0x56) << 8;
128	tmp \|= stv0297_readreg(state, 0x57) << 16;
129	tmp \|= stv0297_readreg(state, 0x58) << 24;
130
131	tmp *= STV0297_CLOCK_KHZ;
132	tmp >>= 32;
133
134	return (u32) tmp;
135	}
136
137	static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate)
138	{
139	long tmp;
140
141	tmp = 131072L * srate; /* 131072 = 2^17 */
142	tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */
143	tmp = tmp * 8192L; /* 8192 = 2^13 */
144
145	stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF));
146	stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8));
147	stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16));
148	stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24));
149	}
150
151	static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate)
152	{
153	long tmp;
154
155	tmp = (long) fshift 262144L; / 262144 = 218 /
156	tmp /= symrate;
157	tmp = 1024; / 1024 = 210 /
158
159	// adjust
160	if (tmp >= 0) {
161	tmp += 500000;
162	} else {
163	tmp -= 500000;
164	}
165	tmp /= 1000000;
166
167	stv0297_writereg(state, 0x60, tmp & 0xFF);
168	stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0);
169	}
170
171	static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset)
172	{
173	long tmp;
174
175	/* symrate is hardcoded to 10000 */
176	tmp = offset * 26844L; /* (2*28)/10000 /
177	if (tmp < 0)
178	tmp += 0x10000000;
179	tmp &= 0x0FFFFFFF;
180
181	stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF));
182	stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8));
183	stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16));
184	stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f);
185	}
186
187	/*
188	static long stv0297_get_carrieroffset(struct stv0297_state *state)
189	{
190	s64 tmp;
191
192	stv0297_writereg(state, 0x6B, 0x00);
193
194	tmp = stv0297_readreg(state, 0x66);
195	tmp \|= (stv0297_readreg(state, 0x67) << 8);
196	tmp \|= (stv0297_readreg(state, 0x68) << 16);
197	tmp \|= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
198
199	tmp *= stv0297_get_symbolrate(state);
200	tmp >>= 28;
201
202	return (s32) tmp;
203	}
204	*/
205
206	static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq)
207	{
208	s32 tmp;
209
210	if (freq > 10000)
211	freq -= STV0297_CLOCK_KHZ;
212
213	tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16);
214	tmp = (freq * 1000) / tmp;
215	if (tmp > 0xffff)
216	tmp = 0xffff;
217
218	stv0297_writereg_mask(state, 0x25, 0x80, 0x80);
219	stv0297_writereg(state, 0x21, tmp >> 8);
220	stv0297_writereg(state, 0x20, tmp);
221	}
222
223	static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation)
224	{
225	int val = 0;
226
227	switch (modulation) {
228	case QAM_16:
229	val = 0;
230	break;
231
232	case QAM_32:
233	val = 1;
234	break;
235
236	case QAM_64:
237	val = 4;
238	break;
239
240	case QAM_128:
241	val = 2;
242	break;
243
244	case QAM_256:
245	val = 3;
246	break;
247
248	default:
249	return -EINVAL;
250	}
251
252	stv0297_writereg_mask(state, 0x00, 0x70, val << 4);
253
254	return 0;
255	}
256
257	static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion)
258	{
259	int val = 0;
260
261	switch (inversion) {
262	case INVERSION_OFF:
263	val = 0;
264	break;
265
266	case INVERSION_ON:
267	val = 1;
268	break;
269
270	default:
271	return -EINVAL;
272	}
273
274	stv0297_writereg_mask(state, 0x83, 0x08, val << 3);
275
276	return 0;
277	}
278
279	int stv0297_enable_plli2c(struct dvb_frontend *fe)
280	{
b8742700	281	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	282
	283	stv0297_writereg(state, 0x87, 0x78);
	284	stv0297_writereg(state, 0x86, 0xc8);
	285
	286	return 0;
	287	}
	288
	289	static int stv0297_init(struct dvb_frontend *fe)
	290	{
b8742700	291	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	292	int i;
1da177e4 LT	293
1da177e4	294	/* load init table */
dc27a169 AQ	295	for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2)
dc27a169 AQ	296	stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]);
1da177e4 LT	297	msleep(200);
	298
	299	if (state->config->pll_init)
	300	state->config->pll_init(fe);
	301
	302	return 0;
	303	}
	304
	305	static int stv0297_sleep(struct dvb_frontend *fe)
	306	{
b8742700	307	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	308
	309	stv0297_writereg_mask(state, 0x80, 1, 1);
	310
	311	return 0;
	312	}
	313
	314	static int stv0297_read_status(struct dvb_frontend fe, fe_status_t status)
	315	{
b8742700	316	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	317
	318	u8 sync = stv0297_readreg(state, 0xDF);
	319
	320	*status = 0;
	321	if (sync & 0x80)
	322	*status \|=
	323	FE_HAS_SYNC \| FE_HAS_SIGNAL \| FE_HAS_CARRIER \| FE_HAS_VITERBI \| FE_HAS_LOCK;
	324	return 0;
	325	}
	326
	327	static int stv0297_read_ber(struct dvb_frontend fe, u32 ber)
	328	{
b8742700	329	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	330	u8 BER[3];
	331
	332	stv0297_writereg(state, 0xA0, 0x80); // Start Counting bit errors for 4096 Bytes
	333	mdelay(25); // Hopefully got 4096 Bytes
	334	stv0297_readregs(state, 0xA0, BER, 3);
	335	mdelay(25);
	336	ber = (BER[2] << 8 \| BER[1]) / (8 4096);
	337
	338	return 0;
	339	}
	340
	341
	342	static int stv0297_read_signal_strength(struct dvb_frontend fe, u16 strength)
	343	{
b8742700	344	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	345	u8 STRENGTH[2];
	346
	347	stv0297_readregs(state, 0x41, STRENGTH, 2);
	348	*strength = (STRENGTH[1] & 0x03) << 8 \| STRENGTH[0];
	349
	350	return 0;
	351	}
	352
	353	static int stv0297_read_snr(struct dvb_frontend fe, u16 snr)
	354	{
b8742700	355	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	356	u8 SNR[2];
	357
	358	stv0297_readregs(state, 0x07, SNR, 2);
	359	*snr = SNR[1] << 8 \| SNR[0];
	360
	361	return 0;
	362	}
	363
	364	static int stv0297_read_ucblocks(struct dvb_frontend fe, u32 ucblocks)
	365	{
b8742700	366	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	367
	368	*ucblocks = (stv0297_readreg(state, 0xD5) << 8)
	369	\| stv0297_readreg(state, 0xD4);
	370
	371	return 0;
	372	}
	373
	374	static int stv0297_set_frontend(struct dvb_frontend fe, struct dvb_frontend_parameters p)
	375	{
b8742700	376	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	377	int u_threshold;
	378	int initial_u;
	379	int blind_u;
	380	int delay;
	381	int sweeprate;
	382	int carrieroffset;
	383	unsigned long starttime;
	384	unsigned long timeout;
	385	fe_spectral_inversion_t inversion;
	386
	387	switch (p->u.qam.modulation) {
	388	case QAM_16:
	389	case QAM_32:
	390	case QAM_64:
	391	delay = 100;
	392	sweeprate = 1500;
	393	break;
	394
	395	case QAM_128:
1da177e4 LT	396	case QAM_256:
	397	delay = 200;
	398	sweeprate = 500;
	399	break;
	400
	401	default:
	402	return -EINVAL;
	403	}
	404
	405	// determine inversion dependant parameters
	406	inversion = p->inversion;
	407	if (state->config->invert)
	408	inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
	409	carrieroffset = -330;
	410	switch (inversion) {
	411	case INVERSION_OFF:
	412	break;
	413
	414	case INVERSION_ON:
	415	sweeprate = -sweeprate;
	416	carrieroffset = -carrieroffset;
	417	break;
	418
	419	default:
	420	return -EINVAL;
	421	}
	422
	423	stv0297_init(fe);
	424	state->config->pll_set(fe, p);
	425
	426	/* clear software interrupts */
	427	stv0297_writereg(state, 0x82, 0x0);
	428
	429	/* set initial demodulation frequency */
	430	stv0297_set_initialdemodfreq(state, 7250);
	431
	432	/* setup AGC */
	433	stv0297_writereg_mask(state, 0x43, 0x10, 0x00);
	434	stv0297_writereg(state, 0x41, 0x00);
	435	stv0297_writereg_mask(state, 0x42, 0x03, 0x01);
	436	stv0297_writereg_mask(state, 0x36, 0x60, 0x00);
	437	stv0297_writereg_mask(state, 0x36, 0x18, 0x00);
	438	stv0297_writereg_mask(state, 0x71, 0x80, 0x80);
	439	stv0297_writereg(state, 0x72, 0x00);
	440	stv0297_writereg(state, 0x73, 0x00);
	441	stv0297_writereg_mask(state, 0x74, 0x0F, 0x00);
	442	stv0297_writereg_mask(state, 0x43, 0x08, 0x00);
	443	stv0297_writereg_mask(state, 0x71, 0x80, 0x00);
	444
	445	/* setup STL */
	446	stv0297_writereg_mask(state, 0x5a, 0x20, 0x20);
	447	stv0297_writereg_mask(state, 0x5b, 0x02, 0x02);
	448	stv0297_writereg_mask(state, 0x5b, 0x02, 0x00);
	449	stv0297_writereg_mask(state, 0x5b, 0x01, 0x00);
	450	stv0297_writereg_mask(state, 0x5a, 0x40, 0x40);
	451
	452	/* disable frequency sweep */
	453	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
	454
	455	/* reset deinterleaver */
	456	stv0297_writereg_mask(state, 0x81, 0x01, 0x01);
	457	stv0297_writereg_mask(state, 0x81, 0x01, 0x00);
	458
	459	/* ??? */
460	stv0297_writereg_mask(state, 0x83, 0x20, 0x20);
461	stv0297_writereg_mask(state, 0x83, 0x20, 0x00);
462
463	/* reset equaliser */
464	u_threshold = stv0297_readreg(state, 0x00) & 0xf;
465	initial_u = stv0297_readreg(state, 0x01) >> 4;
466	blind_u = stv0297_readreg(state, 0x01) & 0xf;
467	stv0297_writereg_mask(state, 0x84, 0x01, 0x01);
468	stv0297_writereg_mask(state, 0x84, 0x01, 0x00);
469	stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold);
470	stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4);
471	stv0297_writereg_mask(state, 0x01, 0x0f, blind_u);
472
473	/* data comes from internal A/D */
474	stv0297_writereg_mask(state, 0x87, 0x80, 0x00);
475
476	/* clear phase registers */
477	stv0297_writereg(state, 0x63, 0x00);
478	stv0297_writereg(state, 0x64, 0x00);
479	stv0297_writereg(state, 0x65, 0x00);
480	stv0297_writereg(state, 0x66, 0x00);
481	stv0297_writereg(state, 0x67, 0x00);
482	stv0297_writereg(state, 0x68, 0x00);
483	stv0297_writereg_mask(state, 0x69, 0x0f, 0x00);
484
485	/* set parameters */
486	stv0297_set_qam(state, p->u.qam.modulation);
487	stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000);
488	stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000);
489	stv0297_set_carrieroffset(state, carrieroffset);
490	stv0297_set_inversion(state, inversion);
491
492	/* kick off lock */
593cbf3d PB	493	/* Disable corner detection for higher QAMs */
	494	if (p->u.qam.modulation == QAM_128 \|\|
	495	p->u.qam.modulation == QAM_256)
	496	stv0297_writereg_mask(state, 0x88, 0x08, 0x00);
	497	else
	498	stv0297_writereg_mask(state, 0x88, 0x08, 0x08);
	499
1da177e4 LT	500	stv0297_writereg_mask(state, 0x5a, 0x20, 0x00);
	501	stv0297_writereg_mask(state, 0x6a, 0x01, 0x01);
	502	stv0297_writereg_mask(state, 0x43, 0x40, 0x40);
	503	stv0297_writereg_mask(state, 0x5b, 0x30, 0x00);
	504	stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c);
	505	stv0297_writereg_mask(state, 0x03, 0x03, 0x03);
	506	stv0297_writereg_mask(state, 0x43, 0x10, 0x10);
	507
	508	/* wait for WGAGC lock */
	509	starttime = jiffies;
48e4cc2d	510	timeout = jiffies + msecs_to_jiffies(2000);
1da177e4 LT	511	while (time_before(jiffies, timeout)) {
	512	msleep(10);
	513	if (stv0297_readreg(state, 0x43) & 0x08)
	514	break;
	515	}
	516	if (time_after(jiffies, timeout)) {
	517	goto timeout;
	518	}
	519	msleep(20);
	520
	521	/* wait for equaliser partial convergence */
48e4cc2d	522	timeout = jiffies + msecs_to_jiffies(500);
1da177e4 LT	523	while (time_before(jiffies, timeout)) {
	524	msleep(10);
	525
	526	if (stv0297_readreg(state, 0x82) & 0x04) {
	527	break;
	528	}
	529	}
	530	if (time_after(jiffies, timeout)) {
	531	goto timeout;
	532	}
	533
	534	/* wait for equaliser full convergence */
48e4cc2d	535	timeout = jiffies + msecs_to_jiffies(delay);
1da177e4 LT	536	while (time_before(jiffies, timeout)) {
	537	msleep(10);
	538
	539	if (stv0297_readreg(state, 0x82) & 0x08) {
	540	break;
	541	}
	542	}
	543	if (time_after(jiffies, timeout)) {
	544	goto timeout;
	545	}
	546
	547	/* disable sweep */
	548	stv0297_writereg_mask(state, 0x6a, 1, 0);
	549	stv0297_writereg_mask(state, 0x88, 8, 0);
	550
	551	/* wait for main lock */
48e4cc2d	552	timeout = jiffies + msecs_to_jiffies(20);
1da177e4 LT	553	while (time_before(jiffies, timeout)) {
	554	msleep(10);
	555
	556	if (stv0297_readreg(state, 0xDF) & 0x80) {
	557	break;
	558	}
	559	}
	560	if (time_after(jiffies, timeout)) {
	561	goto timeout;
	562	}
	563	msleep(100);
	564
	565	/* is it still locked after that delay? */
	566	if (!(stv0297_readreg(state, 0xDF) & 0x80)) {
	567	goto timeout;
	568	}
	569
	570	/* success!! */
	571	stv0297_writereg_mask(state, 0x5a, 0x40, 0x00);
	572	state->base_freq = p->frequency;
	573	return 0;
	574
	575	timeout:
	576	stv0297_writereg_mask(state, 0x6a, 0x01, 0x00);
	577	return 0;
	578	}
	579
	580	static int stv0297_get_frontend(struct dvb_frontend fe, struct dvb_frontend_parameters p)
	581	{
b8742700	582	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	583	int reg_00, reg_83;
	584
	585	reg_00 = stv0297_readreg(state, 0x00);
	586	reg_83 = stv0297_readreg(state, 0x83);
	587
	588	p->frequency = state->base_freq;
	589	p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF;
	590	if (state->config->invert)
	591	p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON;
	592	p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000;
	593	p->u.qam.fec_inner = FEC_NONE;
	594
	595	switch ((reg_00 >> 4) & 0x7) {
	596	case 0:
	597	p->u.qam.modulation = QAM_16;
	598	break;
	599	case 1:
	600	p->u.qam.modulation = QAM_32;
	601	break;
	602	case 2:
	603	p->u.qam.modulation = QAM_128;
	604	break;
	605	case 3:
	606	p->u.qam.modulation = QAM_256;
	607	break;
	608	case 4:
	609	p->u.qam.modulation = QAM_64;
	610	break;
	611	}
	612
	613	return 0;
	614	}
	615
	616	static void stv0297_release(struct dvb_frontend *fe)
	617	{
b8742700	618	struct stv0297_state *state = fe->demodulator_priv;
1da177e4 LT	619	kfree(state);
	620	}
	621
	622	static struct dvb_frontend_ops stv0297_ops;
	623
	624	struct dvb_frontend stv0297_attach(const struct stv0297_config config,
dc27a169	625	struct i2c_adapter *i2c)
1da177e4 LT	626	{
	627	struct stv0297_state *state = NULL;
	628
	629	/* allocate memory for the internal state */
b8742700	630	state = kmalloc(sizeof(struct stv0297_state), GFP_KERNEL);
1da177e4 LT	631	if (state == NULL)
	632	goto error;
	633
	634	/* setup the state */
	635	state->config = config;
	636	state->i2c = i2c;
	637	memcpy(&state->ops, &stv0297_ops, sizeof(struct dvb_frontend_ops));
	638	state->base_freq = 0;
1da177e4 LT	639
	640	/* check if the demod is there */
	641	if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20)
	642	goto error;
	643
	644	/* create dvb_frontend */
	645	state->frontend.ops = &state->ops;
	646	state->frontend.demodulator_priv = state;
	647	return &state->frontend;
	648
	649	error:
	650	kfree(state);
	651	return NULL;
	652	}
	653
	654	static struct dvb_frontend_ops stv0297_ops = {
	655
	656	.info = {
	657	.name = "ST STV0297 DVB-C",
	658	.type = FE_QAM,
	659	.frequency_min = 64000000,
	660	.frequency_max = 1300000000,
	661	.frequency_stepsize = 62500,
	662	.symbol_rate_min = 870000,
	663	.symbol_rate_max = 11700000,
	664	.caps = FE_CAN_QAM_16 \| FE_CAN_QAM_32 \| FE_CAN_QAM_64 \|
	665	FE_CAN_QAM_128 \| FE_CAN_QAM_256 \| FE_CAN_FEC_AUTO},
	666
	667	.release = stv0297_release,
	668
	669	.init = stv0297_init,
	670	.sleep = stv0297_sleep,
	671
	672	.set_frontend = stv0297_set_frontend,
	673	.get_frontend = stv0297_get_frontend,
	674
	675	.read_status = stv0297_read_status,
	676	.read_ber = stv0297_read_ber,
	677	.read_signal_strength = stv0297_read_signal_strength,
	678	.read_snr = stv0297_read_snr,
	679	.read_ucblocks = stv0297_read_ucblocks,
	680	};
	681
	682	MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
	683	MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
	684	MODULE_LICENSE("GPL");
	685
	686	EXPORT_SYMBOL(stv0297_attach);
	687	EXPORT_SYMBOL(stv0297_enable_plli2c);