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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <[email protected]> | |
7 | * Copyright (C) 2000 Goutham Rao <[email protected]> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <[email protected]> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
1da177e4 LT |
17 | */ |
18 | ||
19 | #include <linux/cache.h> | |
17e5ad6c | 20 | #include <linux/dma-mapping.h> |
1da177e4 LT |
21 | #include <linux/mm.h> |
22 | #include <linux/module.h> | |
1da177e4 LT |
23 | #include <linux/spinlock.h> |
24 | #include <linux/string.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/ctype.h> | |
27 | ||
28 | #include <asm/io.h> | |
1da177e4 | 29 | #include <asm/dma.h> |
17e5ad6c | 30 | #include <asm/scatterlist.h> |
1da177e4 LT |
31 | |
32 | #include <linux/init.h> | |
33 | #include <linux/bootmem.h> | |
a8522509 | 34 | #include <linux/iommu-helper.h> |
1da177e4 LT |
35 | |
36 | #define OFFSET(val,align) ((unsigned long) \ | |
37 | ( (val) & ( (align) - 1))) | |
38 | ||
f9527f12 | 39 | #define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg))) |
93fbff63 | 40 | #define SG_ENT_PHYS_ADDRESS(sg) virt_to_bus(SG_ENT_VIRT_ADDRESS(sg)) |
1da177e4 LT |
41 | |
42 | /* | |
43 | * Maximum allowable number of contiguous slabs to map, | |
44 | * must be a power of 2. What is the appropriate value ? | |
45 | * The complexity of {map,unmap}_single is linearly dependent on this value. | |
46 | */ | |
47 | #define IO_TLB_SEGSIZE 128 | |
48 | ||
49 | /* | |
50 | * log of the size of each IO TLB slab. The number of slabs is command line | |
51 | * controllable. | |
52 | */ | |
53 | #define IO_TLB_SHIFT 11 | |
54 | ||
0b9afede AW |
55 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
56 | ||
57 | /* | |
58 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
59 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
60 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
61 | */ | |
62 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
63 | ||
de69e0f0 JL |
64 | /* |
65 | * Enumeration for sync targets | |
66 | */ | |
67 | enum dma_sync_target { | |
68 | SYNC_FOR_CPU = 0, | |
69 | SYNC_FOR_DEVICE = 1, | |
70 | }; | |
71 | ||
1da177e4 LT |
72 | int swiotlb_force; |
73 | ||
74 | /* | |
75 | * Used to do a quick range check in swiotlb_unmap_single and | |
76 | * swiotlb_sync_single_*, to see if the memory was in fact allocated by this | |
77 | * API. | |
78 | */ | |
79 | static char *io_tlb_start, *io_tlb_end; | |
80 | ||
81 | /* | |
82 | * The number of IO TLB blocks (in groups of 64) betweeen io_tlb_start and | |
83 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. | |
84 | */ | |
85 | static unsigned long io_tlb_nslabs; | |
86 | ||
87 | /* | |
88 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
89 | */ | |
90 | static unsigned long io_tlb_overflow = 32*1024; | |
91 | ||
92 | void *io_tlb_overflow_buffer; | |
93 | ||
94 | /* | |
95 | * This is a free list describing the number of free entries available from | |
96 | * each index | |
97 | */ | |
98 | static unsigned int *io_tlb_list; | |
99 | static unsigned int io_tlb_index; | |
100 | ||
101 | /* | |
102 | * We need to save away the original address corresponding to a mapped entry | |
103 | * for the sync operations. | |
104 | */ | |
25667d67 | 105 | static unsigned char **io_tlb_orig_addr; |
1da177e4 LT |
106 | |
107 | /* | |
108 | * Protect the above data structures in the map and unmap calls | |
109 | */ | |
110 | static DEFINE_SPINLOCK(io_tlb_lock); | |
111 | ||
112 | static int __init | |
113 | setup_io_tlb_npages(char *str) | |
114 | { | |
115 | if (isdigit(*str)) { | |
e8579e72 | 116 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
117 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
118 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
119 | } | |
120 | if (*str == ',') | |
121 | ++str; | |
122 | if (!strcmp(str, "force")) | |
123 | swiotlb_force = 1; | |
124 | return 1; | |
125 | } | |
126 | __setup("swiotlb=", setup_io_tlb_npages); | |
127 | /* make io_tlb_overflow tunable too? */ | |
128 | ||
129 | /* | |
130 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
17e5ad6c | 131 | * structures for the software IO TLB used to implement the DMA API. |
1da177e4 | 132 | */ |
563aaf06 JB |
133 | void __init |
134 | swiotlb_init_with_default_size(size_t default_size) | |
1da177e4 | 135 | { |
563aaf06 | 136 | unsigned long i, bytes; |
1da177e4 LT |
137 | |
138 | if (!io_tlb_nslabs) { | |
e8579e72 | 139 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); |
1da177e4 LT |
140 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); |
141 | } | |
142 | ||
563aaf06 JB |
143 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
144 | ||
1da177e4 LT |
145 | /* |
146 | * Get IO TLB memory from the low pages | |
147 | */ | |
563aaf06 | 148 | io_tlb_start = alloc_bootmem_low_pages(bytes); |
1da177e4 LT |
149 | if (!io_tlb_start) |
150 | panic("Cannot allocate SWIOTLB buffer"); | |
563aaf06 | 151 | io_tlb_end = io_tlb_start + bytes; |
1da177e4 LT |
152 | |
153 | /* | |
154 | * Allocate and initialize the free list array. This array is used | |
155 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
156 | * between io_tlb_start and io_tlb_end. | |
157 | */ | |
158 | io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int)); | |
25667d67 | 159 | for (i = 0; i < io_tlb_nslabs; i++) |
1da177e4 LT |
160 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); |
161 | io_tlb_index = 0; | |
25667d67 | 162 | io_tlb_orig_addr = alloc_bootmem(io_tlb_nslabs * sizeof(char *)); |
1da177e4 LT |
163 | |
164 | /* | |
165 | * Get the overflow emergency buffer | |
166 | */ | |
167 | io_tlb_overflow_buffer = alloc_bootmem_low(io_tlb_overflow); | |
563aaf06 JB |
168 | if (!io_tlb_overflow_buffer) |
169 | panic("Cannot allocate SWIOTLB overflow buffer!\n"); | |
170 | ||
25667d67 TL |
171 | printk(KERN_INFO "Placing software IO TLB between 0x%lx - 0x%lx\n", |
172 | virt_to_bus(io_tlb_start), virt_to_bus(io_tlb_end)); | |
1da177e4 LT |
173 | } |
174 | ||
563aaf06 JB |
175 | void __init |
176 | swiotlb_init(void) | |
1da177e4 | 177 | { |
25667d67 | 178 | swiotlb_init_with_default_size(64 * (1<<20)); /* default to 64MB */ |
1da177e4 LT |
179 | } |
180 | ||
0b9afede AW |
181 | /* |
182 | * Systems with larger DMA zones (those that don't support ISA) can | |
183 | * initialize the swiotlb later using the slab allocator if needed. | |
184 | * This should be just like above, but with some error catching. | |
185 | */ | |
186 | int | |
563aaf06 | 187 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 188 | { |
563aaf06 | 189 | unsigned long i, bytes, req_nslabs = io_tlb_nslabs; |
0b9afede AW |
190 | unsigned int order; |
191 | ||
192 | if (!io_tlb_nslabs) { | |
193 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
194 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
195 | } | |
196 | ||
197 | /* | |
198 | * Get IO TLB memory from the low pages | |
199 | */ | |
563aaf06 | 200 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 201 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 202 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
203 | |
204 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
205 | io_tlb_start = (char *)__get_free_pages(GFP_DMA | __GFP_NOWARN, | |
206 | order); | |
207 | if (io_tlb_start) | |
208 | break; | |
209 | order--; | |
210 | } | |
211 | ||
212 | if (!io_tlb_start) | |
213 | goto cleanup1; | |
214 | ||
563aaf06 | 215 | if (order != get_order(bytes)) { |
0b9afede AW |
216 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
217 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
218 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
563aaf06 | 219 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede | 220 | } |
563aaf06 JB |
221 | io_tlb_end = io_tlb_start + bytes; |
222 | memset(io_tlb_start, 0, bytes); | |
0b9afede AW |
223 | |
224 | /* | |
225 | * Allocate and initialize the free list array. This array is used | |
226 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
227 | * between io_tlb_start and io_tlb_end. | |
228 | */ | |
229 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
230 | get_order(io_tlb_nslabs * sizeof(int))); | |
231 | if (!io_tlb_list) | |
232 | goto cleanup2; | |
233 | ||
234 | for (i = 0; i < io_tlb_nslabs; i++) | |
235 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
236 | io_tlb_index = 0; | |
237 | ||
25667d67 TL |
238 | io_tlb_orig_addr = (unsigned char **)__get_free_pages(GFP_KERNEL, |
239 | get_order(io_tlb_nslabs * sizeof(char *))); | |
0b9afede AW |
240 | if (!io_tlb_orig_addr) |
241 | goto cleanup3; | |
242 | ||
25667d67 | 243 | memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(char *)); |
0b9afede AW |
244 | |
245 | /* | |
246 | * Get the overflow emergency buffer | |
247 | */ | |
248 | io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
249 | get_order(io_tlb_overflow)); | |
250 | if (!io_tlb_overflow_buffer) | |
251 | goto cleanup4; | |
252 | ||
25667d67 TL |
253 | printk(KERN_INFO "Placing %luMB software IO TLB between 0x%lx - " |
254 | "0x%lx\n", bytes >> 20, | |
255 | virt_to_bus(io_tlb_start), virt_to_bus(io_tlb_end)); | |
0b9afede AW |
256 | |
257 | return 0; | |
258 | ||
259 | cleanup4: | |
25667d67 TL |
260 | free_pages((unsigned long)io_tlb_orig_addr, get_order(io_tlb_nslabs * |
261 | sizeof(char *))); | |
0b9afede AW |
262 | io_tlb_orig_addr = NULL; |
263 | cleanup3: | |
25667d67 TL |
264 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
265 | sizeof(int))); | |
0b9afede | 266 | io_tlb_list = NULL; |
0b9afede | 267 | cleanup2: |
563aaf06 | 268 | io_tlb_end = NULL; |
0b9afede AW |
269 | free_pages((unsigned long)io_tlb_start, order); |
270 | io_tlb_start = NULL; | |
271 | cleanup1: | |
272 | io_tlb_nslabs = req_nslabs; | |
273 | return -ENOMEM; | |
274 | } | |
275 | ||
be6b0267 | 276 | static int |
2797982e | 277 | address_needs_mapping(struct device *hwdev, dma_addr_t addr, size_t size) |
1da177e4 | 278 | { |
07a2c01a | 279 | return !is_buffer_dma_capable(dma_get_mask(hwdev), addr, size); |
1da177e4 LT |
280 | } |
281 | ||
640aebfe FT |
282 | static int is_swiotlb_buffer(char *addr) |
283 | { | |
284 | return addr >= io_tlb_start && addr < io_tlb_end; | |
285 | } | |
286 | ||
1da177e4 LT |
287 | /* |
288 | * Allocates bounce buffer and returns its kernel virtual address. | |
289 | */ | |
290 | static void * | |
25667d67 | 291 | map_single(struct device *hwdev, char *buffer, size_t size, int dir) |
1da177e4 LT |
292 | { |
293 | unsigned long flags; | |
294 | char *dma_addr; | |
295 | unsigned int nslots, stride, index, wrap; | |
296 | int i; | |
681cc5cd FT |
297 | unsigned long start_dma_addr; |
298 | unsigned long mask; | |
299 | unsigned long offset_slots; | |
300 | unsigned long max_slots; | |
301 | ||
302 | mask = dma_get_seg_boundary(hwdev); | |
303 | start_dma_addr = virt_to_bus(io_tlb_start) & mask; | |
304 | ||
305 | offset_slots = ALIGN(start_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
b15a3891 JB |
306 | max_slots = mask + 1 |
307 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
308 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
309 | |
310 | /* | |
311 | * For mappings greater than a page, we limit the stride (and | |
312 | * hence alignment) to a page size. | |
313 | */ | |
314 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
315 | if (size > PAGE_SIZE) | |
316 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); | |
317 | else | |
318 | stride = 1; | |
319 | ||
34814545 | 320 | BUG_ON(!nslots); |
1da177e4 LT |
321 | |
322 | /* | |
323 | * Find suitable number of IO TLB entries size that will fit this | |
324 | * request and allocate a buffer from that IO TLB pool. | |
325 | */ | |
326 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
327 | index = ALIGN(io_tlb_index, stride); |
328 | if (index >= io_tlb_nslabs) | |
329 | index = 0; | |
330 | wrap = index; | |
331 | ||
332 | do { | |
a8522509 FT |
333 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
334 | max_slots)) { | |
b15a3891 JB |
335 | index += stride; |
336 | if (index >= io_tlb_nslabs) | |
337 | index = 0; | |
a7133a15 AM |
338 | if (index == wrap) |
339 | goto not_found; | |
340 | } | |
341 | ||
342 | /* | |
343 | * If we find a slot that indicates we have 'nslots' number of | |
344 | * contiguous buffers, we allocate the buffers from that slot | |
345 | * and mark the entries as '0' indicating unavailable. | |
346 | */ | |
347 | if (io_tlb_list[index] >= nslots) { | |
348 | int count = 0; | |
349 | ||
350 | for (i = index; i < (int) (index + nslots); i++) | |
351 | io_tlb_list[i] = 0; | |
352 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
353 | io_tlb_list[i] = ++count; | |
354 | dma_addr = io_tlb_start + (index << IO_TLB_SHIFT); | |
1da177e4 | 355 | |
a7133a15 AM |
356 | /* |
357 | * Update the indices to avoid searching in the next | |
358 | * round. | |
359 | */ | |
360 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
361 | ? (index + nslots) : 0); | |
362 | ||
363 | goto found; | |
364 | } | |
365 | index += stride; | |
366 | if (index >= io_tlb_nslabs) | |
367 | index = 0; | |
368 | } while (index != wrap); | |
369 | ||
370 | not_found: | |
371 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
372 | return NULL; | |
373 | found: | |
1da177e4 LT |
374 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
375 | ||
376 | /* | |
377 | * Save away the mapping from the original address to the DMA address. | |
378 | * This is needed when we sync the memory. Then we sync the buffer if | |
379 | * needed. | |
380 | */ | |
df336d1c KF |
381 | for (i = 0; i < nslots; i++) |
382 | io_tlb_orig_addr[index+i] = buffer + (i << IO_TLB_SHIFT); | |
1da177e4 | 383 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
25667d67 | 384 | memcpy(dma_addr, buffer, size); |
1da177e4 LT |
385 | |
386 | return dma_addr; | |
387 | } | |
388 | ||
389 | /* | |
390 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
391 | */ | |
392 | static void | |
393 | unmap_single(struct device *hwdev, char *dma_addr, size_t size, int dir) | |
394 | { | |
395 | unsigned long flags; | |
396 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
397 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; | |
25667d67 | 398 | char *buffer = io_tlb_orig_addr[index]; |
1da177e4 LT |
399 | |
400 | /* | |
401 | * First, sync the memory before unmapping the entry | |
402 | */ | |
25667d67 | 403 | if (buffer && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
1da177e4 LT |
404 | /* |
405 | * bounce... copy the data back into the original buffer * and | |
406 | * delete the bounce buffer. | |
407 | */ | |
25667d67 | 408 | memcpy(buffer, dma_addr, size); |
1da177e4 LT |
409 | |
410 | /* | |
411 | * Return the buffer to the free list by setting the corresponding | |
412 | * entries to indicate the number of contigous entries available. | |
413 | * While returning the entries to the free list, we merge the entries | |
414 | * with slots below and above the pool being returned. | |
415 | */ | |
416 | spin_lock_irqsave(&io_tlb_lock, flags); | |
417 | { | |
418 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
419 | io_tlb_list[index + nslots] : 0); | |
420 | /* | |
421 | * Step 1: return the slots to the free list, merging the | |
422 | * slots with superceeding slots | |
423 | */ | |
424 | for (i = index + nslots - 1; i >= index; i--) | |
425 | io_tlb_list[i] = ++count; | |
426 | /* | |
427 | * Step 2: merge the returned slots with the preceding slots, | |
428 | * if available (non zero) | |
429 | */ | |
430 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
431 | io_tlb_list[i] = ++count; | |
432 | } | |
433 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
434 | } | |
435 | ||
436 | static void | |
de69e0f0 JL |
437 | sync_single(struct device *hwdev, char *dma_addr, size_t size, |
438 | int dir, int target) | |
1da177e4 LT |
439 | { |
440 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; | |
25667d67 | 441 | char *buffer = io_tlb_orig_addr[index]; |
1da177e4 | 442 | |
df336d1c KF |
443 | buffer += ((unsigned long)dma_addr & ((1 << IO_TLB_SHIFT) - 1)); |
444 | ||
de69e0f0 JL |
445 | switch (target) { |
446 | case SYNC_FOR_CPU: | |
447 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
25667d67 | 448 | memcpy(buffer, dma_addr, size); |
34814545 ES |
449 | else |
450 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
451 | break; |
452 | case SYNC_FOR_DEVICE: | |
453 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
25667d67 | 454 | memcpy(dma_addr, buffer, size); |
34814545 ES |
455 | else |
456 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
457 | break; |
458 | default: | |
1da177e4 | 459 | BUG(); |
de69e0f0 | 460 | } |
1da177e4 LT |
461 | } |
462 | ||
463 | void * | |
464 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 465 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 466 | { |
563aaf06 | 467 | dma_addr_t dev_addr; |
1da177e4 LT |
468 | void *ret; |
469 | int order = get_order(size); | |
1e74f300 FT |
470 | u64 dma_mask = DMA_32BIT_MASK; |
471 | ||
472 | if (hwdev && hwdev->coherent_dma_mask) | |
473 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 474 | |
25667d67 | 475 | ret = (void *)__get_free_pages(flags, order); |
1e74f300 | 476 | if (ret && !is_buffer_dma_capable(dma_mask, virt_to_bus(ret), size)) { |
1da177e4 LT |
477 | /* |
478 | * The allocated memory isn't reachable by the device. | |
479 | * Fall back on swiotlb_map_single(). | |
480 | */ | |
481 | free_pages((unsigned long) ret, order); | |
482 | ret = NULL; | |
483 | } | |
484 | if (!ret) { | |
485 | /* | |
486 | * We are either out of memory or the device can't DMA | |
487 | * to GFP_DMA memory; fall back on | |
488 | * swiotlb_map_single(), which will grab memory from | |
489 | * the lowest available address range. | |
490 | */ | |
9dfda12b FT |
491 | ret = map_single(hwdev, NULL, size, DMA_FROM_DEVICE); |
492 | if (!ret) | |
1da177e4 | 493 | return NULL; |
1da177e4 LT |
494 | } |
495 | ||
496 | memset(ret, 0, size); | |
93fbff63 | 497 | dev_addr = virt_to_bus(ret); |
1da177e4 LT |
498 | |
499 | /* Confirm address can be DMA'd by device */ | |
1e74f300 | 500 | if (!is_buffer_dma_capable(dma_mask, dev_addr, size)) { |
563aaf06 | 501 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", |
1e74f300 | 502 | (unsigned long long)dma_mask, |
563aaf06 | 503 | (unsigned long long)dev_addr); |
a2b89b59 FT |
504 | |
505 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
506 | unmap_single(hwdev, ret, size, DMA_TO_DEVICE); | |
507 | return NULL; | |
1da177e4 LT |
508 | } |
509 | *dma_handle = dev_addr; | |
510 | return ret; | |
511 | } | |
512 | ||
513 | void | |
514 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
515 | dma_addr_t dma_handle) | |
516 | { | |
aa24886e | 517 | WARN_ON(irqs_disabled()); |
640aebfe | 518 | if (!is_swiotlb_buffer(vaddr)) |
1da177e4 LT |
519 | free_pages((unsigned long) vaddr, get_order(size)); |
520 | else | |
521 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
21f6c4de | 522 | unmap_single(hwdev, vaddr, size, DMA_TO_DEVICE); |
1da177e4 LT |
523 | } |
524 | ||
525 | static void | |
526 | swiotlb_full(struct device *dev, size_t size, int dir, int do_panic) | |
527 | { | |
528 | /* | |
529 | * Ran out of IOMMU space for this operation. This is very bad. | |
530 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 531 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
532 | * When the mapping is small enough return a static buffer to limit |
533 | * the damage, or panic when the transfer is too big. | |
534 | */ | |
563aaf06 | 535 | printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at " |
1da177e4 LT |
536 | "device %s\n", size, dev ? dev->bus_id : "?"); |
537 | ||
538 | if (size > io_tlb_overflow && do_panic) { | |
17e5ad6c TL |
539 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
540 | panic("DMA: Memory would be corrupted\n"); | |
541 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) | |
542 | panic("DMA: Random memory would be DMAed\n"); | |
1da177e4 LT |
543 | } |
544 | } | |
545 | ||
546 | /* | |
547 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 548 | * physical address to use is returned. |
1da177e4 LT |
549 | * |
550 | * Once the device is given the dma address, the device owns this memory until | |
551 | * either swiotlb_unmap_single or swiotlb_dma_sync_single is performed. | |
552 | */ | |
553 | dma_addr_t | |
309df0c5 AK |
554 | swiotlb_map_single_attrs(struct device *hwdev, void *ptr, size_t size, |
555 | int dir, struct dma_attrs *attrs) | |
1da177e4 | 556 | { |
563aaf06 | 557 | dma_addr_t dev_addr = virt_to_bus(ptr); |
1da177e4 LT |
558 | void *map; |
559 | ||
34814545 | 560 | BUG_ON(dir == DMA_NONE); |
1da177e4 LT |
561 | /* |
562 | * If the pointer passed in happens to be in the device's DMA window, | |
563 | * we can safely return the device addr and not worry about bounce | |
564 | * buffering it. | |
565 | */ | |
2797982e | 566 | if (!address_needs_mapping(hwdev, dev_addr, size) && !swiotlb_force) |
1da177e4 LT |
567 | return dev_addr; |
568 | ||
569 | /* | |
570 | * Oh well, have to allocate and map a bounce buffer. | |
571 | */ | |
25667d67 | 572 | map = map_single(hwdev, ptr, size, dir); |
1da177e4 LT |
573 | if (!map) { |
574 | swiotlb_full(hwdev, size, dir, 1); | |
575 | map = io_tlb_overflow_buffer; | |
576 | } | |
577 | ||
93fbff63 | 578 | dev_addr = virt_to_bus(map); |
1da177e4 LT |
579 | |
580 | /* | |
581 | * Ensure that the address returned is DMA'ble | |
582 | */ | |
2797982e | 583 | if (address_needs_mapping(hwdev, dev_addr, size)) |
1da177e4 LT |
584 | panic("map_single: bounce buffer is not DMA'ble"); |
585 | ||
586 | return dev_addr; | |
587 | } | |
309df0c5 AK |
588 | EXPORT_SYMBOL(swiotlb_map_single_attrs); |
589 | ||
590 | dma_addr_t | |
591 | swiotlb_map_single(struct device *hwdev, void *ptr, size_t size, int dir) | |
592 | { | |
593 | return swiotlb_map_single_attrs(hwdev, ptr, size, dir, NULL); | |
594 | } | |
1da177e4 | 595 | |
1da177e4 LT |
596 | /* |
597 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
598 | * match what was provided for in a previous swiotlb_map_single call. All | |
599 | * other usages are undefined. | |
600 | * | |
601 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
602 | * whatever the device wrote there. | |
603 | */ | |
604 | void | |
309df0c5 AK |
605 | swiotlb_unmap_single_attrs(struct device *hwdev, dma_addr_t dev_addr, |
606 | size_t size, int dir, struct dma_attrs *attrs) | |
1da177e4 | 607 | { |
93fbff63 | 608 | char *dma_addr = bus_to_virt(dev_addr); |
1da177e4 | 609 | |
34814545 | 610 | BUG_ON(dir == DMA_NONE); |
640aebfe | 611 | if (is_swiotlb_buffer(dma_addr)) |
1da177e4 LT |
612 | unmap_single(hwdev, dma_addr, size, dir); |
613 | else if (dir == DMA_FROM_DEVICE) | |
cde14bbf | 614 | dma_mark_clean(dma_addr, size); |
1da177e4 | 615 | } |
309df0c5 | 616 | EXPORT_SYMBOL(swiotlb_unmap_single_attrs); |
1da177e4 | 617 | |
309df0c5 AK |
618 | void |
619 | swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr, size_t size, | |
620 | int dir) | |
621 | { | |
622 | return swiotlb_unmap_single_attrs(hwdev, dev_addr, size, dir, NULL); | |
623 | } | |
1da177e4 LT |
624 | /* |
625 | * Make physical memory consistent for a single streaming mode DMA translation | |
626 | * after a transfer. | |
627 | * | |
628 | * If you perform a swiotlb_map_single() but wish to interrogate the buffer | |
17e5ad6c TL |
629 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
630 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
631 | * address back to the card, you must first perform a |
632 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
633 | */ | |
be6b0267 | 634 | static void |
8270f3f1 | 635 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 | 636 | size_t size, int dir, int target) |
1da177e4 | 637 | { |
93fbff63 | 638 | char *dma_addr = bus_to_virt(dev_addr); |
1da177e4 | 639 | |
34814545 | 640 | BUG_ON(dir == DMA_NONE); |
640aebfe | 641 | if (is_swiotlb_buffer(dma_addr)) |
de69e0f0 | 642 | sync_single(hwdev, dma_addr, size, dir, target); |
1da177e4 | 643 | else if (dir == DMA_FROM_DEVICE) |
cde14bbf | 644 | dma_mark_clean(dma_addr, size); |
1da177e4 LT |
645 | } |
646 | ||
8270f3f1 JL |
647 | void |
648 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
649 | size_t size, int dir) | |
650 | { | |
de69e0f0 | 651 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 JL |
652 | } |
653 | ||
1da177e4 LT |
654 | void |
655 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
656 | size_t size, int dir) | |
657 | { | |
de69e0f0 | 658 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 LT |
659 | } |
660 | ||
878a97cf JL |
661 | /* |
662 | * Same as above, but for a sub-range of the mapping. | |
663 | */ | |
be6b0267 | 664 | static void |
878a97cf | 665 | swiotlb_sync_single_range(struct device *hwdev, dma_addr_t dev_addr, |
de69e0f0 JL |
666 | unsigned long offset, size_t size, |
667 | int dir, int target) | |
878a97cf | 668 | { |
93fbff63 | 669 | char *dma_addr = bus_to_virt(dev_addr) + offset; |
878a97cf | 670 | |
34814545 | 671 | BUG_ON(dir == DMA_NONE); |
640aebfe | 672 | if (is_swiotlb_buffer(dma_addr)) |
de69e0f0 | 673 | sync_single(hwdev, dma_addr, size, dir, target); |
878a97cf | 674 | else if (dir == DMA_FROM_DEVICE) |
cde14bbf | 675 | dma_mark_clean(dma_addr, size); |
878a97cf JL |
676 | } |
677 | ||
678 | void | |
679 | swiotlb_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
680 | unsigned long offset, size_t size, int dir) | |
681 | { | |
de69e0f0 JL |
682 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
683 | SYNC_FOR_CPU); | |
878a97cf JL |
684 | } |
685 | ||
686 | void | |
687 | swiotlb_sync_single_range_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
688 | unsigned long offset, size_t size, int dir) | |
689 | { | |
de69e0f0 JL |
690 | swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir, |
691 | SYNC_FOR_DEVICE); | |
878a97cf JL |
692 | } |
693 | ||
309df0c5 AK |
694 | void swiotlb_unmap_sg_attrs(struct device *, struct scatterlist *, int, int, |
695 | struct dma_attrs *); | |
1da177e4 LT |
696 | /* |
697 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
698 | * This is the scatter-gather version of the above swiotlb_map_single | |
699 | * interface. Here the scatter gather list elements are each tagged with the | |
700 | * appropriate dma address and length. They are obtained via | |
701 | * sg_dma_{address,length}(SG). | |
702 | * | |
703 | * NOTE: An implementation may be able to use a smaller number of | |
704 | * DMA address/length pairs than there are SG table elements. | |
705 | * (for example via virtual mapping capabilities) | |
706 | * The routine returns the number of addr/length pairs actually | |
707 | * used, at most nents. | |
708 | * | |
709 | * Device ownership issues as mentioned above for swiotlb_map_single are the | |
710 | * same here. | |
711 | */ | |
712 | int | |
309df0c5 AK |
713 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
714 | int dir, struct dma_attrs *attrs) | |
1da177e4 | 715 | { |
dbfd49fe | 716 | struct scatterlist *sg; |
25667d67 | 717 | void *addr; |
563aaf06 | 718 | dma_addr_t dev_addr; |
1da177e4 LT |
719 | int i; |
720 | ||
34814545 | 721 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 722 | |
dbfd49fe | 723 | for_each_sg(sgl, sg, nelems, i) { |
25667d67 TL |
724 | addr = SG_ENT_VIRT_ADDRESS(sg); |
725 | dev_addr = virt_to_bus(addr); | |
2797982e FT |
726 | if (swiotlb_force || |
727 | address_needs_mapping(hwdev, dev_addr, sg->length)) { | |
25667d67 | 728 | void *map = map_single(hwdev, addr, sg->length, dir); |
7e870233 | 729 | if (!map) { |
1da177e4 LT |
730 | /* Don't panic here, we expect map_sg users |
731 | to do proper error handling. */ | |
732 | swiotlb_full(hwdev, sg->length, dir, 0); | |
309df0c5 AK |
733 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
734 | attrs); | |
dbfd49fe | 735 | sgl[0].dma_length = 0; |
1da177e4 LT |
736 | return 0; |
737 | } | |
cde14bbf | 738 | sg->dma_address = virt_to_bus(map); |
1da177e4 LT |
739 | } else |
740 | sg->dma_address = dev_addr; | |
741 | sg->dma_length = sg->length; | |
742 | } | |
743 | return nelems; | |
744 | } | |
309df0c5 AK |
745 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
746 | ||
747 | int | |
748 | swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
749 | int dir) | |
750 | { | |
751 | return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
752 | } | |
1da177e4 LT |
753 | |
754 | /* | |
755 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
756 | * concerning calls here are the same as for swiotlb_unmap_single() above. | |
757 | */ | |
758 | void | |
309df0c5 AK |
759 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
760 | int nelems, int dir, struct dma_attrs *attrs) | |
1da177e4 | 761 | { |
dbfd49fe | 762 | struct scatterlist *sg; |
1da177e4 LT |
763 | int i; |
764 | ||
34814545 | 765 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 766 | |
dbfd49fe | 767 | for_each_sg(sgl, sg, nelems, i) { |
1da177e4 | 768 | if (sg->dma_address != SG_ENT_PHYS_ADDRESS(sg)) |
93fbff63 JB |
769 | unmap_single(hwdev, bus_to_virt(sg->dma_address), |
770 | sg->dma_length, dir); | |
1da177e4 | 771 | else if (dir == DMA_FROM_DEVICE) |
cde14bbf | 772 | dma_mark_clean(SG_ENT_VIRT_ADDRESS(sg), sg->dma_length); |
dbfd49fe | 773 | } |
1da177e4 | 774 | } |
309df0c5 AK |
775 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
776 | ||
777 | void | |
778 | swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
779 | int dir) | |
780 | { | |
781 | return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
782 | } | |
1da177e4 LT |
783 | |
784 | /* | |
785 | * Make physical memory consistent for a set of streaming mode DMA translations | |
786 | * after a transfer. | |
787 | * | |
788 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
789 | * and usage. | |
790 | */ | |
be6b0267 | 791 | static void |
dbfd49fe | 792 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
de69e0f0 | 793 | int nelems, int dir, int target) |
1da177e4 | 794 | { |
dbfd49fe | 795 | struct scatterlist *sg; |
1da177e4 LT |
796 | int i; |
797 | ||
34814545 | 798 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 799 | |
dbfd49fe | 800 | for_each_sg(sgl, sg, nelems, i) { |
1da177e4 | 801 | if (sg->dma_address != SG_ENT_PHYS_ADDRESS(sg)) |
93fbff63 | 802 | sync_single(hwdev, bus_to_virt(sg->dma_address), |
de69e0f0 | 803 | sg->dma_length, dir, target); |
cde14bbf JB |
804 | else if (dir == DMA_FROM_DEVICE) |
805 | dma_mark_clean(SG_ENT_VIRT_ADDRESS(sg), sg->dma_length); | |
dbfd49fe | 806 | } |
1da177e4 LT |
807 | } |
808 | ||
8270f3f1 JL |
809 | void |
810 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
811 | int nelems, int dir) | |
812 | { | |
de69e0f0 | 813 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 JL |
814 | } |
815 | ||
1da177e4 LT |
816 | void |
817 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
818 | int nelems, int dir) | |
819 | { | |
de69e0f0 | 820 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 LT |
821 | } |
822 | ||
823 | int | |
8d8bb39b | 824 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 825 | { |
93fbff63 | 826 | return (dma_addr == virt_to_bus(io_tlb_overflow_buffer)); |
1da177e4 LT |
827 | } |
828 | ||
829 | /* | |
17e5ad6c | 830 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 831 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 832 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
833 | * this function. |
834 | */ | |
835 | int | |
563aaf06 | 836 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 837 | { |
25667d67 | 838 | return virt_to_bus(io_tlb_end - 1) <= mask; |
1da177e4 LT |
839 | } |
840 | ||
1da177e4 LT |
841 | EXPORT_SYMBOL(swiotlb_map_single); |
842 | EXPORT_SYMBOL(swiotlb_unmap_single); | |
843 | EXPORT_SYMBOL(swiotlb_map_sg); | |
844 | EXPORT_SYMBOL(swiotlb_unmap_sg); | |
845 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); | |
846 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); | |
878a97cf JL |
847 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_cpu); |
848 | EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_device); | |
1da177e4 LT |
849 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
850 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); | |
851 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); | |
25667d67 TL |
852 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
853 | EXPORT_SYMBOL(swiotlb_free_coherent); | |
1da177e4 | 854 | EXPORT_SYMBOL(swiotlb_dma_supported); |