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IB/qib: Use a single txselect module parameter for serdes tuning
[linux.git] / drivers / infiniband / hw / qib / qib_iba7322.c
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f931551b
RC		 1/*
2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33/*
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/io.h>
42#include <linux/jiffies.h>
43#include <rdma/ib_verbs.h>
44#include <rdma/ib_smi.h>
45#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
46#include <linux/dca.h>
47#endif
48
49#include "qib.h"
50#include "qib_7322_regs.h"
51#include "qib_qsfp.h"
52
53#include "qib_mad.h"
54
55static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
56static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
57static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
58static irqreturn_t qib_7322intr(int irq, void *data);
59static irqreturn_t qib_7322bufavail(int irq, void *data);
60static irqreturn_t sdma_intr(int irq, void *data);
61static irqreturn_t sdma_idle_intr(int irq, void *data);
62static irqreturn_t sdma_progress_intr(int irq, void *data);
63static irqreturn_t sdma_cleanup_intr(int irq, void *data);
64static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
65 struct qib_ctxtdata *rcd);
66static u8 qib_7322_phys_portstate(u64);
67static u32 qib_7322_iblink_state(u64);
68static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
69 u16 linitcmd);
70static void force_h1(struct qib_pportdata *);
71static void adj_tx_serdes(struct qib_pportdata *);
72static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
73static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
74
75static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
76static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
77
78#define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
79
80/* LE2 serdes values for different cases */
81#define LE2_DEFAULT 5
82#define LE2_5m 4
83#define LE2_QME 0
84
85/* Below is special-purpose, so only really works for the IB SerDes blocks. */
86#define IBSD(hw_pidx) (hw_pidx + 2)
87
88/* these are variables for documentation and experimentation purposes */
89static const unsigned rcv_int_timeout = 375;
90static const unsigned rcv_int_count = 16;
91static const unsigned sdma_idle_cnt = 64;
92
93/* Time to stop altering Rx Equalization parameters, after link up. */
94#define RXEQ_DISABLE_MSECS 2500
95
96/*
97 * Number of VLs we are configured to use (to allow for more
98 * credits per vl, etc.)
99 */
100ushort qib_num_cfg_vls = 2;
101module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
102MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
103
104static ushort qib_chase = 1;
105module_param_named(chase, qib_chase, ushort, S_IRUGO);
106MODULE_PARM_DESC(chase, "Enable state chase handling");
107
108static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
109module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
110MODULE_PARM_DESC(long_attenuation, \
111 "attenuation cutoff (dB) for long copper cable setup");
112
113static ushort qib_singleport;
114module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
115MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
116
f931551b
RC		 117#define MAX_ATTEN_LEN 64 /* plenty for any real system */
118/* for read back, default index is ~5m copper cable */
a77fcf89
RC		 119static char txselect_list[MAX_ATTEN_LEN] = "10";
120static struct kparam_string kp_txselect = {
121 .string = txselect_list,
f931551b
RC		 122 .maxlen = MAX_ATTEN_LEN
123};
a77fcf89
RC		 124static int setup_txselect(const char *, struct kernel_param *);
125module_param_call(txselect, setup_txselect, param_get_string,
126 &kp_txselect, S_IWUSR | S_IRUGO);
127MODULE_PARM_DESC(txselect, \
128 "Tx serdes indices (for no QSFP or invalid QSFP data)");
f931551b
RC		 129
130#define BOARD_QME7342 5
131#define BOARD_QMH7342 6
132#define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
133 BOARD_QMH7342)
134#define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
135 BOARD_QME7342)
136
137#define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
138
139#define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
140
141#define MASK_ACROSS(lsb, msb) \
142 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
143
144#define SYM_RMASK(regname, fldname) ((u64) \
145 QIB_7322_##regname##_##fldname##_RMASK)
146
147#define SYM_MASK(regname, fldname) ((u64) \
148 QIB_7322_##regname##_##fldname##_RMASK << \
149 QIB_7322_##regname##_##fldname##_LSB)
150
151#define SYM_FIELD(value, regname, fldname) ((u64) \
152 (((value) >> SYM_LSB(regname, fldname)) & \
153 SYM_RMASK(regname, fldname)))
154
155/* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
156#define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
157 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
158
159#define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
160#define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
161#define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
162#define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
163#define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
164/* Below because most, but not all, fields of IntMask have that full suffix */
165#define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
166
167
168#define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
169
170/*
171 * the size bits give us 2^N, in KB units. 0 marks as invalid,
172 * and 7 is reserved. We currently use only 2KB and 4KB
173 */
174#define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
175#define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
176#define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
177#define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
178
179#define SendIBSLIDAssignMask \
180 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
181#define SendIBSLMCMask \
182 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
183
184#define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
185#define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
186#define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
187#define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
188#define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
189#define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
190
191#define _QIB_GPIO_SDA_NUM 1
192#define _QIB_GPIO_SCL_NUM 0
193#define QIB_EEPROM_WEN_NUM 14
194#define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
195
196/* HW counter clock is at 4nsec */
197#define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
198
199/* full speed IB port 1 only */
200#define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
201#define PORT_SPD_CAP_SHIFT 3
202
203/* full speed featuremask, both ports */
204#define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
205
206/*
207 * This file contains almost all the chip-specific register information and
208 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
209 */
210
211/* Use defines to tie machine-generated names to lower-case names */
212#define kr_contextcnt KREG_IDX(ContextCnt)
213#define kr_control KREG_IDX(Control)
214#define kr_counterregbase KREG_IDX(CntrRegBase)
215#define kr_errclear KREG_IDX(ErrClear)
216#define kr_errmask KREG_IDX(ErrMask)
217#define kr_errstatus KREG_IDX(ErrStatus)
218#define kr_extctrl KREG_IDX(EXTCtrl)
219#define kr_extstatus KREG_IDX(EXTStatus)
220#define kr_gpio_clear KREG_IDX(GPIOClear)
221#define kr_gpio_mask KREG_IDX(GPIOMask)
222#define kr_gpio_out KREG_IDX(GPIOOut)
223#define kr_gpio_status KREG_IDX(GPIOStatus)
224#define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
225#define kr_debugportval KREG_IDX(DebugPortValueReg)
226#define kr_fmask KREG_IDX(feature_mask)
227#define kr_act_fmask KREG_IDX(active_feature_mask)
228#define kr_hwerrclear KREG_IDX(HwErrClear)
229#define kr_hwerrmask KREG_IDX(HwErrMask)
230#define kr_hwerrstatus KREG_IDX(HwErrStatus)
231#define kr_intclear KREG_IDX(IntClear)
232#define kr_intmask KREG_IDX(IntMask)
233#define kr_intredirect KREG_IDX(IntRedirect0)
234#define kr_intstatus KREG_IDX(IntStatus)
235#define kr_pagealign KREG_IDX(PageAlign)
236#define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
237#define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
238#define kr_rcvegrbase KREG_IDX(RcvEgrBase)
239#define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
240#define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
241#define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
242#define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
243#define kr_rcvtidbase KREG_IDX(RcvTIDBase)
244#define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
245#define kr_revision KREG_IDX(Revision)
246#define kr_scratch KREG_IDX(Scratch)
247#define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
248#define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
249#define kr_sendctrl KREG_IDX(SendCtrl)
250#define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
251#define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
252#define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
253#define kr_sendpiobufbase KREG_IDX(SendBufBase)
254#define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
255#define kr_sendpiosize KREG_IDX(SendBufSize)
256#define kr_sendregbase KREG_IDX(SendRegBase)
257#define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
258#define kr_userregbase KREG_IDX(UserRegBase)
259#define kr_intgranted KREG_IDX(Int_Granted)
260#define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
261#define kr_intblocked KREG_IDX(IntBlocked)
262#define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
263
264/*
265 * per-port kernel registers. Access only with qib_read_kreg_port()
266 * or qib_write_kreg_port()
267 */
268#define krp_errclear KREG_IBPORT_IDX(ErrClear)
269#define krp_errmask KREG_IBPORT_IDX(ErrMask)
270#define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
271#define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
272#define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
273#define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
274#define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
275#define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
276#define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
277#define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
278#define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
279#define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
280#define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
281#define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
282#define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
283#define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
284#define krp_psinterval KREG_IBPORT_IDX(PSInterval)
285#define krp_psstart KREG_IBPORT_IDX(PSStart)
286#define krp_psstat KREG_IBPORT_IDX(PSStat)
287#define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
288#define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
289#define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
290#define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
291#define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
292#define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
293#define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
294#define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
295#define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
296#define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
297#define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
298#define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
299#define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
300#define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
301#define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
302#define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
303#define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
304#define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
305#define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
306#define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
307#define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
308#define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
309#define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
310#define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
311#define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
312#define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
313#define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
314#define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
315#define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
316#define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
317#define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
318
319/*
320 * Per-context kernel registers. Acess only with qib_read_kreg_ctxt()
321 * or qib_write_kreg_ctxt()
322 */
323#define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
324#define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
325
326/*
327 * TID Flow table, per context. Reduces
328 * number of hdrq updates to one per flow (or on errors).
329 * context 0 and 1 share same memory, but have distinct
330 * addresses. Since for now, we never use expected sends
331 * on kernel contexts, we don't worry about that (we initialize
332 * those entries for ctxt 0/1 on driver load twice, for example).
333 */
334#define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
335#define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
336
337/* these are the error bits in the tid flows, and are W1C */
338#define TIDFLOW_ERRBITS ( \
339 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
340 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
341 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
342 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
343
344/* Most (not all) Counters are per-IBport.
345 * Requires LBIntCnt is at offset 0 in the group
346 */
347#define CREG_IDX(regname) \
348((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
349
350#define crp_badformat CREG_IDX(RxVersionErrCnt)
351#define crp_err_rlen CREG_IDX(RxLenErrCnt)
352#define crp_erricrc CREG_IDX(RxICRCErrCnt)
353#define crp_errlink CREG_IDX(RxLinkMalformCnt)
354#define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
355#define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
356#define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
357#define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
358#define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
359#define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
360#define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
361#define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
362#define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
363#define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
364#define crp_pktrcv CREG_IDX(RxDataPktCnt)
365#define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
366#define crp_pktsend CREG_IDX(TxDataPktCnt)
367#define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
368#define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
369#define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
370#define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
371#define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
372#define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
373#define crp_rcvebp CREG_IDX(RxEBPCnt)
374#define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
375#define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
376#define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
377#define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
378#define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
379#define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
380#define crp_rxvlerr CREG_IDX(RxVlErrCnt)
381#define crp_sendstall CREG_IDX(TxFlowStallCnt)
382#define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
383#define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
384#define crp_txlenerr CREG_IDX(TxLenErrCnt)
385#define crp_txlenerr CREG_IDX(TxLenErrCnt)
386#define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
387#define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
388#define crp_txunderrun CREG_IDX(TxUnderrunCnt)
389#define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
390#define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
391#define crp_wordrcv CREG_IDX(RxDwordCnt)
392#define crp_wordsend CREG_IDX(TxDwordCnt)
393#define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
394
395/* these are the (few) counters that are not port-specific */
396#define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
397 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
398#define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
399#define cr_lbint CREG_DEVIDX(LBIntCnt)
400#define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
401#define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
402#define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
403#define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
404#define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
405
406/* no chip register for # of IB ports supported, so define */
407#define NUM_IB_PORTS 2
408
409/* 1 VL15 buffer per hardware IB port, no register for this, so define */
410#define NUM_VL15_BUFS NUM_IB_PORTS
411
412/*
413 * context 0 and 1 are special, and there is no chip register that
414 * defines this value, so we have to define it here.
415 * These are all allocated to either 0 or 1 for single port
416 * hardware configuration, otherwise each gets half
417 */
418#define KCTXT0_EGRCNT 2048
419
420/* values for vl and port fields in PBC, 7322-specific */
421#define PBC_PORT_SEL_LSB 26
422#define PBC_PORT_SEL_RMASK 1
423#define PBC_VL_NUM_LSB 27
424#define PBC_VL_NUM_RMASK 7
425#define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
426#define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
427
428static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
429 [IB_RATE_2_5_GBPS] = 16,
430 [IB_RATE_5_GBPS] = 8,
431 [IB_RATE_10_GBPS] = 4,
432 [IB_RATE_20_GBPS] = 2,
433 [IB_RATE_30_GBPS] = 2,
434 [IB_RATE_40_GBPS] = 1
435};
436
437#define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
438#define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
439
440/* link training states, from IBC */
441#define IB_7322_LT_STATE_DISABLED 0x00
442#define IB_7322_LT_STATE_LINKUP 0x01
443#define IB_7322_LT_STATE_POLLACTIVE 0x02
444#define IB_7322_LT_STATE_POLLQUIET 0x03
445#define IB_7322_LT_STATE_SLEEPDELAY 0x04
446#define IB_7322_LT_STATE_SLEEPQUIET 0x05
447#define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
448#define IB_7322_LT_STATE_CFGRCVFCFG 0x09
449#define IB_7322_LT_STATE_CFGWAITRMT 0x0a
450#define IB_7322_LT_STATE_CFGIDLE 0x0b
451#define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
452#define IB_7322_LT_STATE_TXREVLANES 0x0d
453#define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
454#define IB_7322_LT_STATE_RECOVERIDLE 0x0f
455#define IB_7322_LT_STATE_CFGENH 0x10
456#define IB_7322_LT_STATE_CFGTEST 0x11
457
458/* link state machine states from IBC */
459#define IB_7322_L_STATE_DOWN 0x0
460#define IB_7322_L_STATE_INIT 0x1
461#define IB_7322_L_STATE_ARM 0x2
462#define IB_7322_L_STATE_ACTIVE 0x3
463#define IB_7322_L_STATE_ACT_DEFER 0x4
464
465static const u8 qib_7322_physportstate[0x20] = {
466 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
467 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
468 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
469 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
470 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
471 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
472 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
473 [IB_7322_LT_STATE_CFGRCVFCFG] =
474 IB_PHYSPORTSTATE_CFG_TRAIN,
475 [IB_7322_LT_STATE_CFGWAITRMT] =
476 IB_PHYSPORTSTATE_CFG_TRAIN,
477 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
478 [IB_7322_LT_STATE_RECOVERRETRAIN] =
479 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
480 [IB_7322_LT_STATE_RECOVERWAITRMT] =
481 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
482 [IB_7322_LT_STATE_RECOVERIDLE] =
483 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
484 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
485 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
486 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
487 [0x13] = IB_PHYSPORTSTATE_CFG_WAIT_ENH,
488 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
489 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
490 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
491 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
492};
493
494struct qib_chip_specific {
495 u64 __iomem *cregbase;
496 u64 *cntrs;
497 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
498 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
499 u64 main_int_mask; /* clear bits which have dedicated handlers */
500 u64 int_enable_mask; /* for per port interrupts in single port mode */
501 u64 errormask;
502 u64 hwerrmask;
503 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
504 u64 gpio_mask; /* shadow the gpio mask register */
505 u64 extctrl; /* shadow the gpio output enable, etc... */
506 u32 ncntrs;
507 u32 nportcntrs;
508 u32 cntrnamelen;
509 u32 portcntrnamelen;
510 u32 numctxts;
511 u32 rcvegrcnt;
512 u32 updthresh; /* current AvailUpdThld */
513 u32 updthresh_dflt; /* default AvailUpdThld */
514 u32 r1;
515 int irq;
516 u32 num_msix_entries;
517 u32 sdmabufcnt;
518 u32 lastbuf_for_pio;
519 u32 stay_in_freeze;
520 u32 recovery_ports_initted;
521#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
522 u32 dca_ctrl;
523 int rhdr_cpu[18];
524 int sdma_cpu[2];
525 u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */
526#endif
527 struct msix_entry *msix_entries;
528 void **msix_arg;
529 unsigned long *sendchkenable;
530 unsigned long *sendgrhchk;
531 unsigned long *sendibchk;
532 u32 rcvavail_timeout[18];
533 char emsgbuf[128]; /* for device error interrupt msg buffer */
534};
535
536/* Table of entries in "human readable" form Tx Emphasis. */
537struct txdds_ent {
538 u8 amp;
539 u8 pre;
540 u8 main;
541 u8 post;
542};
543
544struct vendor_txdds_ent {
545 u8 oui[QSFP_VOUI_LEN];
546 u8 *partnum;
547 struct txdds_ent sdr;
548 struct txdds_ent ddr;
549 struct txdds_ent qdr;
550};
551
552static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
553
554#define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
a77fcf89 555#define TXDDS_EXTRA_SZ 11 /* number of extra tx settings entries */
f931551b
RC		 556#define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
557
558#define H1_FORCE_VAL 8
a77fcf89
RC		 559#define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
560#define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
f931551b
RC		 561
562/* The static and dynamic registers are paired, and the pairs indexed by spd */
563#define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
564 + ((spd) * 2))
565
566#define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
567#define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
568#define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
569#define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
570#define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
571
f931551b
RC		 572struct qib_chippport_specific {
573 u64 __iomem *kpregbase;
574 u64 __iomem *cpregbase;
575 u64 *portcntrs;
576 struct qib_pportdata *ppd;
577 wait_queue_head_t autoneg_wait;
578 struct delayed_work autoneg_work;
579 struct delayed_work ipg_work;
580 struct timer_list chase_timer;
581 /*
582 * these 5 fields are used to establish deltas for IB symbol
583 * errors and linkrecovery errors. They can be reported on
584 * some chips during link negotiation prior to INIT, and with
585 * DDR when faking DDR negotiations with non-IBTA switches.
586 * The chip counters are adjusted at driver unload if there is
587 * a non-zero delta.
588 */
589 u64 ibdeltainprog;
590 u64 ibsymdelta;
591 u64 ibsymsnap;
592 u64 iblnkerrdelta;
593 u64 iblnkerrsnap;
594 u64 iblnkdownsnap;
595 u64 iblnkdowndelta;
596 u64 ibmalfdelta;
597 u64 ibmalfsnap;
598 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
599 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
600 u64 qdr_dfe_time;
601 u64 chase_end;
602 u32 autoneg_tries;
603 u32 recovery_init;
604 u32 qdr_dfe_on;
605 u32 qdr_reforce;
606 /*
607 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
608 * entry zero is unused, to simplify indexing
609 */
a77fcf89
RC		 610 u8 h1_val;
611 u8 no_eep; /* txselect table index to use if no qsfp info */
f931551b
RC		 612 u8 ipg_tries;
613 u8 ibmalfusesnap;
614 struct qib_qsfp_data qsfp_data;
615 char epmsgbuf[192]; /* for port error interrupt msg buffer */
616};
617
618static struct {
619 const char *name;
620 irq_handler_t handler;
621 int lsb;
622 int port; /* 0 if not port-specific, else port # */
623} irq_table[] = {
624 { QIB_DRV_NAME, qib_7322intr, -1, 0 },
625 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail,
626 SYM_LSB(IntStatus, SendBufAvail), 0 },
627 { QIB_DRV_NAME " (sdma 0)", sdma_intr,
628 SYM_LSB(IntStatus, SDmaInt_0), 1 },
629 { QIB_DRV_NAME " (sdma 1)", sdma_intr,
630 SYM_LSB(IntStatus, SDmaInt_1), 2 },
631 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr,
632 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
633 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr,
634 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
635 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr,
636 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
637 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr,
638 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
639 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr,
640 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
641 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr,
642 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
643};
644
645#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
646static const struct dca_reg_map {
647 int shadow_inx;
648 int lsb;
649 u64 mask;
650 u16 regno;
651} dca_rcvhdr_reg_map[] = {
652 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
653 ~SYM_MASK(DCACtrlB, RcvHdrq0DCAOPH) , KREG_IDX(DCACtrlB) },
654 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
655 ~SYM_MASK(DCACtrlB, RcvHdrq1DCAOPH) , KREG_IDX(DCACtrlB) },
656 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
657 ~SYM_MASK(DCACtrlB, RcvHdrq2DCAOPH) , KREG_IDX(DCACtrlB) },
658 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
659 ~SYM_MASK(DCACtrlB, RcvHdrq3DCAOPH) , KREG_IDX(DCACtrlB) },
660 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
661 ~SYM_MASK(DCACtrlC, RcvHdrq4DCAOPH) , KREG_IDX(DCACtrlC) },
662 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
663 ~SYM_MASK(DCACtrlC, RcvHdrq5DCAOPH) , KREG_IDX(DCACtrlC) },
664 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
665 ~SYM_MASK(DCACtrlC, RcvHdrq6DCAOPH) , KREG_IDX(DCACtrlC) },
666 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
667 ~SYM_MASK(DCACtrlC, RcvHdrq7DCAOPH) , KREG_IDX(DCACtrlC) },
668 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
669 ~SYM_MASK(DCACtrlD, RcvHdrq8DCAOPH) , KREG_IDX(DCACtrlD) },
670 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
671 ~SYM_MASK(DCACtrlD, RcvHdrq9DCAOPH) , KREG_IDX(DCACtrlD) },
672 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
673 ~SYM_MASK(DCACtrlD, RcvHdrq10DCAOPH) , KREG_IDX(DCACtrlD) },
674 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
675 ~SYM_MASK(DCACtrlD, RcvHdrq11DCAOPH) , KREG_IDX(DCACtrlD) },
676 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
677 ~SYM_MASK(DCACtrlE, RcvHdrq12DCAOPH) , KREG_IDX(DCACtrlE) },
678 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
679 ~SYM_MASK(DCACtrlE, RcvHdrq13DCAOPH) , KREG_IDX(DCACtrlE) },
680 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
681 ~SYM_MASK(DCACtrlE, RcvHdrq14DCAOPH) , KREG_IDX(DCACtrlE) },
682 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
683 ~SYM_MASK(DCACtrlE, RcvHdrq15DCAOPH) , KREG_IDX(DCACtrlE) },
684 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
685 ~SYM_MASK(DCACtrlF, RcvHdrq16DCAOPH) , KREG_IDX(DCACtrlF) },
686 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
687 ~SYM_MASK(DCACtrlF, RcvHdrq17DCAOPH) , KREG_IDX(DCACtrlF) },
688};
689#endif
690
691/* ibcctrl bits */
692#define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
693/* cycle through TS1/TS2 till OK */
694#define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
695/* wait for TS1, then go on */
696#define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
697#define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
698
699#define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
700#define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
701#define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
702
703#define BLOB_7322_IBCHG 0x101
704
705static inline void qib_write_kreg(const struct qib_devdata *dd,
706 const u32 regno, u64 value);
707static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
708static void write_7322_initregs(struct qib_devdata *);
709static void write_7322_init_portregs(struct qib_pportdata *);
710static void setup_7322_link_recovery(struct qib_pportdata *, u32);
711static void check_7322_rxe_status(struct qib_pportdata *);
712static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
713
714/**
715 * qib_read_ureg32 - read 32-bit virtualized per-context register
716 * @dd: device
717 * @regno: register number
718 * @ctxt: context number
719 *
720 * Return the contents of a register that is virtualized to be per context.
721 * Returns -1 on errors (not distinguishable from valid contents at
722 * runtime; we may add a separate error variable at some point).
723 */
724static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
725 enum qib_ureg regno, int ctxt)
726{
727 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
728 return 0;
729 return readl(regno + (u64 __iomem *)(
730 (dd->ureg_align * ctxt) + (dd->userbase ?
731 (char __iomem *)dd->userbase :
732 (char __iomem *)dd->kregbase + dd->uregbase)));
733}
734
735/**
736 * qib_read_ureg - read virtualized per-context register
737 * @dd: device
738 * @regno: register number
739 * @ctxt: context number
740 *
741 * Return the contents of a register that is virtualized to be per context.
742 * Returns -1 on errors (not distinguishable from valid contents at
743 * runtime; we may add a separate error variable at some point).
744 */
745static inline u64 qib_read_ureg(const struct qib_devdata *dd,
746 enum qib_ureg regno, int ctxt)
747{
748
749 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
750 return 0;
751 return readq(regno + (u64 __iomem *)(
752 (dd->ureg_align * ctxt) + (dd->userbase ?
753 (char __iomem *)dd->userbase :
754 (char __iomem *)dd->kregbase + dd->uregbase)));
755}
756
757/**
758 * qib_write_ureg - write virtualized per-context register
759 * @dd: device
760 * @regno: register number
761 * @value: value
762 * @ctxt: context
763 *
764 * Write the contents of a register that is virtualized to be per context.
765 */
766static inline void qib_write_ureg(const struct qib_devdata *dd,
767 enum qib_ureg regno, u64 value, int ctxt)
768{
769 u64 __iomem *ubase;
770 if (dd->userbase)
771 ubase = (u64 __iomem *)
772 ((char __iomem *) dd->userbase +
773 dd->ureg_align * ctxt);
774 else
775 ubase = (u64 __iomem *)
776 (dd->uregbase +
777 (char __iomem *) dd->kregbase +
778 dd->ureg_align * ctxt);
779
780 if (dd->kregbase && (dd->flags & QIB_PRESENT))
781 writeq(value, &ubase[regno]);
782}
783
784static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
785 const u32 regno)
786{
787 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
788 return -1;
789 return readl((u32 __iomem *) &dd->kregbase[regno]);
790}
791
792static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
793 const u32 regno)
794{
795 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
796 return -1;
797 return readq(&dd->kregbase[regno]);
798}
799
800static inline void qib_write_kreg(const struct qib_devdata *dd,
801 const u32 regno, u64 value)
802{
803 if (dd->kregbase && (dd->flags & QIB_PRESENT))
804 writeq(value, &dd->kregbase[regno]);
805}
806
807/*
808 * not many sanity checks for the port-specific kernel register routines,
809 * since they are only used when it's known to be safe.
810*/
811static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
812 const u16 regno)
813{
814 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
815 return 0ULL;
816 return readq(&ppd->cpspec->kpregbase[regno]);
817}
818
819static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
820 const u16 regno, u64 value)
821{
822 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
823 (ppd->dd->flags & QIB_PRESENT))
824 writeq(value, &ppd->cpspec->kpregbase[regno]);
825}
826
827/**
828 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
829 * @dd: the qlogic_ib device
830 * @regno: the register number to write
831 * @ctxt: the context containing the register
832 * @value: the value to write
833 */
834static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
835 const u16 regno, unsigned ctxt,
836 u64 value)
837{
838 qib_write_kreg(dd, regno + ctxt, value);
839}
840
841static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
842{
843 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
844 return 0;
845 return readq(&dd->cspec->cregbase[regno]);
846
847
848}
849
850static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
851{
852 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
853 return 0;
854 return readl(&dd->cspec->cregbase[regno]);
855
856
857}
858
859static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
860 u16 regno, u64 value)
861{
862 if (ppd->cpspec && ppd->cpspec->cpregbase &&
863 (ppd->dd->flags & QIB_PRESENT))
864 writeq(value, &ppd->cpspec->cpregbase[regno]);
865}
866
867static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
868 u16 regno)
869{
870 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
871 !(ppd->dd->flags & QIB_PRESENT))
872 return 0;
873 return readq(&ppd->cpspec->cpregbase[regno]);
874}
875
876static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
877 u16 regno)
878{
879 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
880 !(ppd->dd->flags & QIB_PRESENT))
881 return 0;
882 return readl(&ppd->cpspec->cpregbase[regno]);
883}
884
885/* bits in Control register */
886#define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
887#define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
888
889/* bits in general interrupt regs */
890#define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
891#define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
892#define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
893#define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
894#define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
895#define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
896#define QIB_I_C_ERROR INT_MASK(Err)
897
898#define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
899#define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
900#define QIB_I_GPIO INT_MASK(AssertGPIO)
901#define QIB_I_P_SDMAINT(pidx) \
902 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
903 INT_MASK_P(SDmaProgress, pidx) | \
904 INT_MASK_PM(SDmaCleanupDone, pidx))
905
906/* Interrupt bits that are "per port" */
907#define QIB_I_P_BITSEXTANT(pidx) \
908 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
909 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
910 INT_MASK_P(SDmaProgress, pidx) | \
911 INT_MASK_PM(SDmaCleanupDone, pidx))
912
913/* Interrupt bits that are common to a device */
914/* currently unused: QIB_I_SPIOSENT */
915#define QIB_I_C_BITSEXTANT \
916 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
917 QIB_I_SPIOSENT | \
918 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
919
920#define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
921 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
922
923/*
924 * Error bits that are "per port".
925 */
926#define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
927#define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
928#define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
929#define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
930#define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
931#define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
932#define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
933#define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
934#define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
935#define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
936#define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
937#define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
938#define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
939#define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
940#define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
941#define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
942#define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
943#define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
944#define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
945#define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
946#define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
947#define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
948#define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
949#define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
950#define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
951#define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
952#define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
953#define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
954
955#define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
956#define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
957#define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
958#define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
959#define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
960#define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
961#define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
962#define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
963#define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
964#define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
965#define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
966
967/* Error bits that are common to a device */
968#define QIB_E_RESET ERR_MASK(ResetNegated)
969#define QIB_E_HARDWARE ERR_MASK(HardwareErr)
970#define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
971
972
973/*
974 * Per chip (rather than per-port) errors. Most either do
975 * nothing but trigger a print (because they self-recover, or
976 * always occur in tandem with other errors that handle the
977 * issue), or because they indicate errors with no recovery,
978 * but we want to know that they happened.
979 */
980#define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
981#define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
982#define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
983#define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
984#define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
985#define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
986#define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
987#define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
988
989/* SDMA chip errors (not per port)
990 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
991 * the SDMAHALT error immediately, so we just print the dup error via the
992 * E_AUTO mechanism. This is true of most of the per-port fatal errors
993 * as well, but since this is port-independent, by definition, it's
994 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
995 * packet send errors, and so are handled in the same manner as other
996 * per-packet errors.
997 */
998#define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
999#define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
1000#define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
1001
1002/*
1003 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
1004 * it is used to print "common" packet errors.
1005 */
1006#define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
1007 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
1008 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
1009 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1010 QIB_E_P_REBP)
1011
1012/* Error Bits that Packet-related (Receive, per-port) */
1013#define QIB_E_P_RPKTERRS (\
1014 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
1015 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
1016 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
1017 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
1018 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
1019 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
1020
1021/*
1022 * Error bits that are Send-related (per port)
1023 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
1024 * All of these potentially need to have a buffer disarmed
1025 */
1026#define QIB_E_P_SPKTERRS (\
1027 QIB_E_P_SUNEXP_PKTNUM |\
1028 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1029 QIB_E_P_SMAXPKTLEN |\
1030 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1031 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1032 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1033
1034#define QIB_E_SPKTERRS ( \
1035 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1036 ERR_MASK_N(SendUnsupportedVLErr) | \
1037 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1038
1039#define QIB_E_P_SDMAERRS ( \
1040 QIB_E_P_SDMAHALT | \
1041 QIB_E_P_SDMADESCADDRMISALIGN | \
1042 QIB_E_P_SDMAUNEXPDATA | \
1043 QIB_E_P_SDMAMISSINGDW | \
1044 QIB_E_P_SDMADWEN | \
1045 QIB_E_P_SDMARPYTAG | \
1046 QIB_E_P_SDMA1STDESC | \
1047 QIB_E_P_SDMABASE | \
1048 QIB_E_P_SDMATAILOUTOFBOUND | \
1049 QIB_E_P_SDMAOUTOFBOUND | \
1050 QIB_E_P_SDMAGENMISMATCH)
1051
1052/*
1053 * This sets some bits more than once, but makes it more obvious which
1054 * bits are not handled under other categories, and the repeat definition
1055 * is not a problem.
1056 */
1057#define QIB_E_P_BITSEXTANT ( \
1058 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1059 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1060 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1061 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1062 )
1063
1064/*
1065 * These are errors that can occur when the link
1066 * changes state while a packet is being sent or received. This doesn't
1067 * cover things like EBP or VCRC that can be the result of a sending
1068 * having the link change state, so we receive a "known bad" packet.
1069 * All of these are "per port", so renamed:
1070 */
1071#define QIB_E_P_LINK_PKTERRS (\
1072 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1073 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1074 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1075 QIB_E_P_RUNEXPCHAR)
1076
1077/*
1078 * This sets some bits more than once, but makes it more obvious which
1079 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1080 * and the repeat definition is not a problem.
1081 */
1082#define QIB_E_C_BITSEXTANT (\
1083 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1084 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1085 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1086
1087/* Likewise Neuter E_SPKT_ERRS_IGNORE */
1088#define E_SPKT_ERRS_IGNORE 0
1089
1090#define QIB_EXTS_MEMBIST_DISABLED \
1091 SYM_MASK(EXTStatus, MemBISTDisabled)
1092#define QIB_EXTS_MEMBIST_ENDTEST \
1093 SYM_MASK(EXTStatus, MemBISTEndTest)
1094
1095#define QIB_E_SPIOARMLAUNCH \
1096 ERR_MASK(SendArmLaunchErr)
1097
1098#define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1099#define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1100
1101/*
1102 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1103 * and also if forced QDR (only QDR enabled). It's enabled for the
1104 * forced QDR case so that scrambling will be enabled by the TS3
1105 * exchange, when supported by both sides of the link.
1106 */
1107#define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1108#define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1109#define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1110#define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1111#define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1112#define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1113 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1114#define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1115
1116#define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1117#define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1118
1119#define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1120#define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1121#define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1122
1123#define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1124#define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1125#define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1126 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1127#define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1128 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1129#define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1130
1131#define IBA7322_REDIRECT_VEC_PER_REG 12
1132
1133#define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1134#define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1135#define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1136#define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1137#define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1138
1139#define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1140
1141#define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1142 .msg = #fldname }
1143#define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1144 fldname##Mask##_##port), .msg = #fldname }
1145static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1146 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1147 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1148 HWE_AUTO(PCIESerdesPClkNotDetect),
1149 HWE_AUTO(PowerOnBISTFailed),
1150 HWE_AUTO(TempsenseTholdReached),
1151 HWE_AUTO(MemoryErr),
1152 HWE_AUTO(PCIeBusParityErr),
1153 HWE_AUTO(PcieCplTimeout),
1154 HWE_AUTO(PciePoisonedTLP),
1155 HWE_AUTO_P(SDmaMemReadErr, 1),
1156 HWE_AUTO_P(SDmaMemReadErr, 0),
1157 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1158 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1159 HWE_AUTO_P(statusValidNoEop, 1),
1160 HWE_AUTO_P(statusValidNoEop, 0),
1161 HWE_AUTO(LATriggered),
1162 { .mask = 0 }
1163};
1164
1165#define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1166 .msg = #fldname }
1167#define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1168 .msg = #fldname }
1169static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1170 E_AUTO(ResetNegated),
1171 E_AUTO(HardwareErr),
1172 E_AUTO(InvalidAddrErr),
1173 E_AUTO(SDmaVL15Err),
1174 E_AUTO(SBufVL15MisUseErr),
1175 E_AUTO(InvalidEEPCmd),
1176 E_AUTO(RcvContextShareErr),
1177 E_AUTO(SendVLMismatchErr),
1178 E_AUTO(SendArmLaunchErr),
1179 E_AUTO(SendSpecialTriggerErr),
1180 E_AUTO(SDmaWrongPortErr),
1181 E_AUTO(SDmaBufMaskDuplicateErr),
1182 E_AUTO(RcvHdrFullErr),
1183 E_AUTO(RcvEgrFullErr),
1184 { .mask = 0 }
1185};
1186
1187static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1188 E_P_AUTO(IBStatusChanged),
1189 E_P_AUTO(SHeadersErr),
1190 E_P_AUTO(VL15BufMisuseErr),
1191 /*
1192 * SDmaHaltErr is not really an error, make it clearer;
1193 */
1194 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted"},
1195 E_P_AUTO(SDmaDescAddrMisalignErr),
1196 E_P_AUTO(SDmaUnexpDataErr),
1197 E_P_AUTO(SDmaMissingDwErr),
1198 E_P_AUTO(SDmaDwEnErr),
1199 E_P_AUTO(SDmaRpyTagErr),
1200 E_P_AUTO(SDma1stDescErr),
1201 E_P_AUTO(SDmaBaseErr),
1202 E_P_AUTO(SDmaTailOutOfBoundErr),
1203 E_P_AUTO(SDmaOutOfBoundErr),
1204 E_P_AUTO(SDmaGenMismatchErr),
1205 E_P_AUTO(SendBufMisuseErr),
1206 E_P_AUTO(SendUnsupportedVLErr),
1207 E_P_AUTO(SendUnexpectedPktNumErr),
1208 E_P_AUTO(SendDroppedDataPktErr),
1209 E_P_AUTO(SendDroppedSmpPktErr),
1210 E_P_AUTO(SendPktLenErr),
1211 E_P_AUTO(SendUnderRunErr),
1212 E_P_AUTO(SendMaxPktLenErr),
1213 E_P_AUTO(SendMinPktLenErr),
1214 E_P_AUTO(RcvIBLostLinkErr),
1215 E_P_AUTO(RcvHdrErr),
1216 E_P_AUTO(RcvHdrLenErr),
1217 E_P_AUTO(RcvBadTidErr),
1218 E_P_AUTO(RcvBadVersionErr),
1219 E_P_AUTO(RcvIBFlowErr),
1220 E_P_AUTO(RcvEBPErr),
1221 E_P_AUTO(RcvUnsupportedVLErr),
1222 E_P_AUTO(RcvUnexpectedCharErr),
1223 E_P_AUTO(RcvShortPktLenErr),
1224 E_P_AUTO(RcvLongPktLenErr),
1225 E_P_AUTO(RcvMaxPktLenErr),
1226 E_P_AUTO(RcvMinPktLenErr),
1227 E_P_AUTO(RcvICRCErr),
1228 E_P_AUTO(RcvVCRCErr),
1229 E_P_AUTO(RcvFormatErr),
1230 { .mask = 0 }
1231};
1232
1233/*
1234 * Below generates "auto-message" for interrupts not specific to any port or
1235 * context
1236 */
1237#define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1238 .msg = #fldname }
1239/* Below generates "auto-message" for interrupts specific to a port */
1240#define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1241 SYM_LSB(IntMask, fldname##Mask##_0), \
1242 SYM_LSB(IntMask, fldname##Mask##_1)), \
1243 .msg = #fldname "_P" }
1244/* For some reason, the SerDesTrimDone bits are reversed */
1245#define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1246 SYM_LSB(IntMask, fldname##Mask##_1), \
1247 SYM_LSB(IntMask, fldname##Mask##_0)), \
1248 .msg = #fldname "_P" }
1249/*
1250 * Below generates "auto-message" for interrupts specific to a context,
1251 * with ctxt-number appended
1252 */
1253#define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1254 SYM_LSB(IntMask, fldname##0IntMask), \
1255 SYM_LSB(IntMask, fldname##17IntMask)), \
1256 .msg = #fldname "_C"}
1257
1258static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1259 INTR_AUTO_P(SDmaInt),
1260 INTR_AUTO_P(SDmaProgressInt),
1261 INTR_AUTO_P(SDmaIdleInt),
1262 INTR_AUTO_P(SDmaCleanupDone),
1263 INTR_AUTO_C(RcvUrg),
1264 INTR_AUTO_P(ErrInt),
1265 INTR_AUTO(ErrInt), /* non-port-specific errs */
1266 INTR_AUTO(AssertGPIOInt),
1267 INTR_AUTO_P(SendDoneInt),
1268 INTR_AUTO(SendBufAvailInt),
1269 INTR_AUTO_C(RcvAvail),
1270 { .mask = 0 }
1271};
1272
1273#define TXSYMPTOM_AUTO_P(fldname) \
1274 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), .msg = #fldname }
1275static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1276 TXSYMPTOM_AUTO_P(NonKeyPacket),
1277 TXSYMPTOM_AUTO_P(GRHFail),
1278 TXSYMPTOM_AUTO_P(PkeyFail),
1279 TXSYMPTOM_AUTO_P(QPFail),
1280 TXSYMPTOM_AUTO_P(SLIDFail),
1281 TXSYMPTOM_AUTO_P(RawIPV6),
1282 TXSYMPTOM_AUTO_P(PacketTooSmall),
1283 { .mask = 0 }
1284};
1285
1286#define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1287
1288/*
1289 * Called when we might have an error that is specific to a particular
1290 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1291 * because we don't need to force the update of pioavail
1292 */
1293static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1294{
1295 struct qib_devdata *dd = ppd->dd;
1296 u32 i;
1297 int any;
1298 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1299 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1300 unsigned long sbuf[4];
1301
1302 /*
1303 * It's possible that sendbuffererror could have bits set; might
1304 * have already done this as a result of hardware error handling.
1305 */
1306 any = 0;
1307 for (i = 0; i < regcnt; ++i) {
1308 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1309 if (sbuf[i]) {
1310 any = 1;
1311 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1312 }
1313 }
1314
1315 if (any)
1316 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1317}
1318
1319/* No txe_recover yet, if ever */
1320
1321/* No decode__errors yet */
1322static void err_decode(char *msg, size_t len, u64 errs,
1323 const struct qib_hwerror_msgs *msp)
1324{
1325 u64 these, lmask;
1326 int took, multi, n = 0;
1327
1328 while (msp && msp->mask) {
1329 multi = (msp->mask & (msp->mask - 1));
1330 while (errs & msp->mask) {
1331 these = (errs & msp->mask);
1332 lmask = (these & (these - 1)) ^ these;
1333 if (len) {
1334 if (n++) {
1335 /* separate the strings */
1336 *msg++ = ',';
1337 len--;
1338 }
1339 took = scnprintf(msg, len, "%s", msp->msg);
1340 len -= took;
1341 msg += took;
1342 }
1343 errs &= ~lmask;
1344 if (len && multi) {
1345 /* More than one bit this mask */
1346 int idx = -1;
1347
1348 while (lmask & msp->mask) {
1349 ++idx;
1350 lmask >>= 1;
1351 }
1352 took = scnprintf(msg, len, "_%d", idx);
1353 len -= took;
1354 msg += took;
1355 }
1356 }
1357 ++msp;
1358 }
1359 /* If some bits are left, show in hex. */
1360 if (len && errs)
1361 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1362 (unsigned long long) errs);
1363}
1364
1365/* only called if r1 set */
1366static void flush_fifo(struct qib_pportdata *ppd)
1367{
1368 struct qib_devdata *dd = ppd->dd;
1369 u32 __iomem *piobuf;
1370 u32 bufn;
1371 u32 *hdr;
1372 u64 pbc;
1373 const unsigned hdrwords = 7;
1374 static struct qib_ib_header ibhdr = {
1375 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1376 .lrh[1] = IB_LID_PERMISSIVE,
1377 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1378 .lrh[3] = IB_LID_PERMISSIVE,
1379 .u.oth.bth[0] = cpu_to_be32(
1380 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1381 .u.oth.bth[1] = cpu_to_be32(0),
1382 .u.oth.bth[2] = cpu_to_be32(0),
1383 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1384 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1385 };
1386
1387 /*
1388 * Send a dummy VL15 packet to flush the launch FIFO.
1389 * This will not actually be sent since the TxeBypassIbc bit is set.
1390 */
1391 pbc = PBC_7322_VL15_SEND |
1392 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1393 (hdrwords + SIZE_OF_CRC);
1394 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1395 if (!piobuf)
1396 return;
1397 writeq(pbc, piobuf);
1398 hdr = (u32 *) &ibhdr;
1399 if (dd->flags & QIB_PIO_FLUSH_WC) {
1400 qib_flush_wc();
1401 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1402 qib_flush_wc();
1403 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1404 qib_flush_wc();
1405 } else
1406 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1407 qib_sendbuf_done(dd, bufn);
1408}
1409
1410/*
1411 * This is called with interrupts disabled and sdma_lock held.
1412 */
1413static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1414{
1415 struct qib_devdata *dd = ppd->dd;
1416 u64 set_sendctrl = 0;
1417 u64 clr_sendctrl = 0;
1418
1419 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1420 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1421 else
1422 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1423
1424 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1425 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1426 else
1427 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1428
1429 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1430 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1431 else
1432 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1433
1434 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1435 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1436 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1437 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1438 else
1439 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1440 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1441 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1442
1443 spin_lock(&dd->sendctrl_lock);
1444
1445 /* If we are draining everything, block sends first */
1446 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1447 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1448 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1449 qib_write_kreg(dd, kr_scratch, 0);
1450 }
1451
1452 ppd->p_sendctrl |= set_sendctrl;
1453 ppd->p_sendctrl &= ~clr_sendctrl;
1454
1455 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1456 qib_write_kreg_port(ppd, krp_sendctrl,
1457 ppd->p_sendctrl |
1458 SYM_MASK(SendCtrl_0, SDmaCleanup));
1459 else
1460 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1461 qib_write_kreg(dd, kr_scratch, 0);
1462
1463 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1464 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1465 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1466 qib_write_kreg(dd, kr_scratch, 0);
1467 }
1468
1469 spin_unlock(&dd->sendctrl_lock);
1470
1471 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1472 flush_fifo(ppd);
1473}
1474
1475static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1476{
1477 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1478}
1479
1480static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1481{
1482 /*
1483 * Set SendDmaLenGen and clear and set
1484 * the MSB of the generation count to enable generation checking
1485 * and load the internal generation counter.
1486 */
1487 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1488 qib_write_kreg_port(ppd, krp_senddmalengen,
1489 ppd->sdma_descq_cnt |
1490 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1491}
1492
1493/*
1494 * Must be called with sdma_lock held, or before init finished.
1495 */
1496static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1497{
1498 /* Commit writes to memory and advance the tail on the chip */
1499 wmb();
1500 ppd->sdma_descq_tail = tail;
1501 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1502}
1503
1504/*
1505 * This is called with interrupts disabled and sdma_lock held.
1506 */
1507static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1508{
1509 /*
1510 * Drain all FIFOs.
1511 * The hardware doesn't require this but we do it so that verbs
1512 * and user applications don't wait for link active to send stale
1513 * data.
1514 */
1515 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1516
1517 qib_sdma_7322_setlengen(ppd);
1518 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1519 ppd->sdma_head_dma[0] = 0;
1520 qib_7322_sdma_sendctrl(ppd,
1521 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1522}
1523
1524#define DISABLES_SDMA ( \
1525 QIB_E_P_SDMAHALT | \
1526 QIB_E_P_SDMADESCADDRMISALIGN | \
1527 QIB_E_P_SDMAMISSINGDW | \
1528 QIB_E_P_SDMADWEN | \
1529 QIB_E_P_SDMARPYTAG | \
1530 QIB_E_P_SDMA1STDESC | \
1531 QIB_E_P_SDMABASE | \
1532 QIB_E_P_SDMATAILOUTOFBOUND | \
1533 QIB_E_P_SDMAOUTOFBOUND | \
1534 QIB_E_P_SDMAGENMISMATCH)
1535
1536static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1537{
1538 unsigned long flags;
1539 struct qib_devdata *dd = ppd->dd;
1540
1541 errs &= QIB_E_P_SDMAERRS;
1542
1543 if (errs & QIB_E_P_SDMAUNEXPDATA)
1544 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1545 ppd->port);
1546
1547 spin_lock_irqsave(&ppd->sdma_lock, flags);
1548
1549 switch (ppd->sdma_state.current_state) {
1550 case qib_sdma_state_s00_hw_down:
1551 break;
1552
1553 case qib_sdma_state_s10_hw_start_up_wait:
1554 if (errs & QIB_E_P_SDMAHALT)
1555 __qib_sdma_process_event(ppd,
1556 qib_sdma_event_e20_hw_started);
1557 break;
1558
1559 case qib_sdma_state_s20_idle:
1560 break;
1561
1562 case qib_sdma_state_s30_sw_clean_up_wait:
1563 break;
1564
1565 case qib_sdma_state_s40_hw_clean_up_wait:
1566 if (errs & QIB_E_P_SDMAHALT)
1567 __qib_sdma_process_event(ppd,
1568 qib_sdma_event_e50_hw_cleaned);
1569 break;
1570
1571 case qib_sdma_state_s50_hw_halt_wait:
1572 if (errs & QIB_E_P_SDMAHALT)
1573 __qib_sdma_process_event(ppd,
1574 qib_sdma_event_e60_hw_halted);
1575 break;
1576
1577 case qib_sdma_state_s99_running:
1578 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1579 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1580 break;
1581 }
1582
1583 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1584}
1585
1586/*
1587 * handle per-device errors (not per-port errors)
1588 */
1589static noinline void handle_7322_errors(struct qib_devdata *dd)
1590{
1591 char *msg;
1592 u64 iserr = 0;
1593 u64 errs;
1594 u64 mask;
1595 int log_idx;
1596
1597 qib_stats.sps_errints++;
1598 errs = qib_read_kreg64(dd, kr_errstatus);
1599 if (!errs) {
1600 qib_devinfo(dd->pcidev, "device error interrupt, "
1601 "but no error bits set!\n");
1602 goto done;
1603 }
1604
1605 /* don't report errors that are masked */
1606 errs &= dd->cspec->errormask;
1607 msg = dd->cspec->emsgbuf;
1608
1609 /* do these first, they are most important */
1610 if (errs & QIB_E_HARDWARE) {
1611 *msg = '\0';
1612 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1613 } else
1614 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1615 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1616 qib_inc_eeprom_err(dd, log_idx, 1);
1617
1618 if (errs & QIB_E_SPKTERRS) {
1619 qib_disarm_7322_senderrbufs(dd->pport);
1620 qib_stats.sps_txerrs++;
1621 } else if (errs & QIB_E_INVALIDADDR)
1622 qib_stats.sps_txerrs++;
1623 else if (errs & QIB_E_ARMLAUNCH) {
1624 qib_stats.sps_txerrs++;
1625 qib_disarm_7322_senderrbufs(dd->pport);
1626 }
1627 qib_write_kreg(dd, kr_errclear, errs);
1628
1629 /*
1630 * The ones we mask off are handled specially below
1631 * or above. Also mask SDMADISABLED by default as it
1632 * is too chatty.
1633 */
1634 mask = QIB_E_HARDWARE;
1635 *msg = '\0';
1636
1637 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1638 qib_7322error_msgs);
1639
1640 /*
1641 * Getting reset is a tragedy for all ports. Mark the device
1642 * _and_ the ports as "offline" in way meaningful to each.
1643 */
1644 if (errs & QIB_E_RESET) {
1645 int pidx;
1646
1647 qib_dev_err(dd, "Got reset, requires re-init "
1648 "(unload and reload driver)\n");
1649 dd->flags &= ~QIB_INITTED; /* needs re-init */
1650 /* mark as having had error */
1651 *dd->devstatusp |= QIB_STATUS_HWERROR;
1652 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1653 if (dd->pport[pidx].link_speed_supported)
1654 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1655 }
1656
1657 if (*msg && iserr)
1658 qib_dev_err(dd, "%s error\n", msg);
1659
1660 /*
1661 * If there were hdrq or egrfull errors, wake up any processes
1662 * waiting in poll. We used to try to check which contexts had
1663 * the overflow, but given the cost of that and the chip reads
1664 * to support it, it's better to just wake everybody up if we
1665 * get an overflow; waiters can poll again if it's not them.
1666 */
1667 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1668 qib_handle_urcv(dd, ~0U);
1669 if (errs & ERR_MASK(RcvEgrFullErr))
1670 qib_stats.sps_buffull++;
1671 else
1672 qib_stats.sps_hdrfull++;
1673 }
1674
1675done:
1676 return;
1677}
1678
1679static void reenable_chase(unsigned long opaque)
1680{
1681 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1682
1683 ppd->cpspec->chase_timer.expires = 0;
1684 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1685 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1686}
1687
1688static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt)
1689{
1690 ppd->cpspec->chase_end = 0;
1691
1692 if (!qib_chase)
1693 return;
1694
1695 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1696 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1697 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1698 add_timer(&ppd->cpspec->chase_timer);
1699}
1700
1701static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1702{
1703 u8 ibclt;
1704 u64 tnow;
1705
1706 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1707
1708 /*
1709 * Detect and handle the state chase issue, where we can
1710 * get stuck if we are unlucky on timing on both sides of
1711 * the link. If we are, we disable, set a timer, and
1712 * then re-enable.
1713 */
1714 switch (ibclt) {
1715 case IB_7322_LT_STATE_CFGRCVFCFG:
1716 case IB_7322_LT_STATE_CFGWAITRMT:
1717 case IB_7322_LT_STATE_TXREVLANES:
1718 case IB_7322_LT_STATE_CFGENH:
1719 tnow = get_jiffies_64();
1720 if (ppd->cpspec->chase_end &&
1721 time_after64(tnow, ppd->cpspec->chase_end))
1722 disable_chase(ppd, tnow, ibclt);
1723 else if (!ppd->cpspec->chase_end)
1724 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1725 break;
1726 default:
1727 ppd->cpspec->chase_end = 0;
1728 break;
1729 }
1730
1731 if (ibclt == IB_7322_LT_STATE_CFGTEST &&
1732 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1733 force_h1(ppd);
1734 ppd->cpspec->qdr_reforce = 1;
1735 } else if (ppd->cpspec->qdr_reforce &&
1736 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1737 (ibclt == IB_7322_LT_STATE_CFGENH ||
1738 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1739 ibclt == IB_7322_LT_STATE_LINKUP))
1740 force_h1(ppd);
1741
1742 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1743 ppd->link_speed_enabled == QIB_IB_QDR &&
1744 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1745 ibclt == IB_7322_LT_STATE_CFGENH ||
1746 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1747 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1748 adj_tx_serdes(ppd);
1749
1750 if (!ppd->cpspec->qdr_dfe_on && ibclt != IB_7322_LT_STATE_LINKUP &&
1751 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1752 ppd->cpspec->qdr_dfe_on = 1;
1753 ppd->cpspec->qdr_dfe_time = 0;
1754 /* On link down, reenable QDR adaptation */
1755 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1756 ppd->dd->cspec->r1 ?
1757 QDR_STATIC_ADAPT_DOWN_R1 :
1758 QDR_STATIC_ADAPT_DOWN);
1759 }
1760}
1761
1762/*
1763 * This is per-pport error handling.
1764 * will likely get it's own MSIx interrupt (one for each port,
1765 * although just a single handler).
1766 */
1767static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1768{
1769 char *msg;
1770 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1771 struct qib_devdata *dd = ppd->dd;
1772
1773 /* do this as soon as possible */
1774 fmask = qib_read_kreg64(dd, kr_act_fmask);
1775 if (!fmask)
1776 check_7322_rxe_status(ppd);
1777
1778 errs = qib_read_kreg_port(ppd, krp_errstatus);
1779 if (!errs)
1780 qib_devinfo(dd->pcidev,
1781 "Port%d error interrupt, but no error bits set!\n",
1782 ppd->port);
1783 if (!fmask)
1784 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1785 if (!errs)
1786 goto done;
1787
1788 msg = ppd->cpspec->epmsgbuf;
1789 *msg = '\0';
1790
1791 if (errs & ~QIB_E_P_BITSEXTANT) {
1792 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1793 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1794 if (!*msg)
1795 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1796 "no others");
1797 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1798 " errors 0x%016Lx set (and %s)\n",
1799 (errs & ~QIB_E_P_BITSEXTANT), msg);
1800 *msg = '\0';
1801 }
1802
1803 if (errs & QIB_E_P_SHDR) {
1804 u64 symptom;
1805
1806 /* determine cause, then write to clear */
1807 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1808 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1809 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1810 hdrchk_msgs);
1811 *msg = '\0';
1812 /* senderrbuf cleared in SPKTERRS below */
1813 }
1814
1815 if (errs & QIB_E_P_SPKTERRS) {
1816 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1817 !(ppd->lflags & QIBL_LINKACTIVE)) {
1818 /*
1819 * This can happen when trying to bring the link
1820 * up, but the IB link changes state at the "wrong"
1821 * time. The IB logic then complains that the packet
1822 * isn't valid. We don't want to confuse people, so
1823 * we just don't print them, except at debug
1824 */
1825 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1826 (errs & QIB_E_P_LINK_PKTERRS),
1827 qib_7322p_error_msgs);
1828 *msg = '\0';
1829 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1830 }
1831 qib_disarm_7322_senderrbufs(ppd);
1832 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1833 !(ppd->lflags & QIBL_LINKACTIVE)) {
1834 /*
1835 * This can happen when SMA is trying to bring the link
1836 * up, but the IB link changes state at the "wrong" time.
1837 * The IB logic then complains that the packet isn't
1838 * valid. We don't want to confuse people, so we just
1839 * don't print them, except at debug
1840 */
1841 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1842 qib_7322p_error_msgs);
1843 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1844 *msg = '\0';
1845 }
1846
1847 qib_write_kreg_port(ppd, krp_errclear, errs);
1848
1849 errs &= ~ignore_this_time;
1850 if (!errs)
1851 goto done;
1852
1853 if (errs & QIB_E_P_RPKTERRS)
1854 qib_stats.sps_rcverrs++;
1855 if (errs & QIB_E_P_SPKTERRS)
1856 qib_stats.sps_txerrs++;
1857
1858 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1859
1860 if (errs & QIB_E_P_SDMAERRS)
1861 sdma_7322_p_errors(ppd, errs);
1862
1863 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1864 u64 ibcs;
1865 u8 ltstate;
1866
1867 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1868 ltstate = qib_7322_phys_portstate(ibcs);
1869
1870 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1871 handle_serdes_issues(ppd, ibcs);
1872 if (!(ppd->cpspec->ibcctrl_a &
1873 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1874 /*
1875 * We got our interrupt, so init code should be
1876 * happy and not try alternatives. Now squelch
1877 * other "chatter" from link-negotiation (pre Init)
1878 */
1879 ppd->cpspec->ibcctrl_a |=
1880 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1881 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1882 ppd->cpspec->ibcctrl_a);
1883 }
1884
1885 /* Update our picture of width and speed from chip */
1886 ppd->link_width_active =
1887 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1888 IB_WIDTH_4X : IB_WIDTH_1X;
1889 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1890 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1891 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1892 QIB_IB_DDR : QIB_IB_SDR;
1893
1894 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1895 IB_PHYSPORTSTATE_DISABLED)
1896 qib_set_ib_7322_lstate(ppd, 0,
1897 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1898 else
1899 /*
1900 * Since going into a recovery state causes the link
1901 * state to go down and since recovery is transitory,
1902 * it is better if we "miss" ever seeing the link
1903 * training state go into recovery (i.e., ignore this
1904 * transition for link state special handling purposes)
1905 * without updating lastibcstat.
1906 */
1907 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1908 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1909 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1910 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1911 qib_handle_e_ibstatuschanged(ppd, ibcs);
1912 }
1913 if (*msg && iserr)
1914 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1915
1916 if (ppd->state_wanted & ppd->lflags)
1917 wake_up_interruptible(&ppd->state_wait);
1918done:
1919 return;
1920}
1921
1922/* enable/disable chip from delivering interrupts */
1923static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1924{
1925 if (enable) {
1926 if (dd->flags & QIB_BADINTR)
1927 return;
1928 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1929 /* cause any pending enabled interrupts to be re-delivered */
1930 qib_write_kreg(dd, kr_intclear, 0ULL);
1931 if (dd->cspec->num_msix_entries) {
1932 /* and same for MSIx */
1933 u64 val = qib_read_kreg64(dd, kr_intgranted);
1934 if (val)
1935 qib_write_kreg(dd, kr_intgranted, val);
1936 }
1937 } else
1938 qib_write_kreg(dd, kr_intmask, 0ULL);
1939}
1940
1941/*
1942 * Try to cleanup as much as possible for anything that might have gone
1943 * wrong while in freeze mode, such as pio buffers being written by user
1944 * processes (causing armlaunch), send errors due to going into freeze mode,
1945 * etc., and try to avoid causing extra interrupts while doing so.
1946 * Forcibly update the in-memory pioavail register copies after cleanup
1947 * because the chip won't do it while in freeze mode (the register values
1948 * themselves are kept correct).
1949 * Make sure that we don't lose any important interrupts by using the chip
1950 * feature that says that writing 0 to a bit in *clear that is set in
1951 * *status will cause an interrupt to be generated again (if allowed by
1952 * the *mask value).
1953 * This is in chip-specific code because of all of the register accesses,
1954 * even though the details are similar on most chips.
1955 */
1956static void qib_7322_clear_freeze(struct qib_devdata *dd)
1957{
1958 int pidx;
1959
1960 /* disable error interrupts, to avoid confusion */
1961 qib_write_kreg(dd, kr_errmask, 0ULL);
1962
1963 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1964 if (dd->pport[pidx].link_speed_supported)
1965 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1966 0ULL);
1967
1968 /* also disable interrupts; errormask is sometimes overwriten */
1969 qib_7322_set_intr_state(dd, 0);
1970
1971 /* clear the freeze, and be sure chip saw it */
1972 qib_write_kreg(dd, kr_control, dd->control);
1973 qib_read_kreg32(dd, kr_scratch);
1974
1975 /*
1976 * Force new interrupt if any hwerr, error or interrupt bits are
1977 * still set, and clear "safe" send packet errors related to freeze
1978 * and cancelling sends. Re-enable error interrupts before possible
1979 * force of re-interrupt on pending interrupts.
1980 */
1981 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1982 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1983 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1984 /* We need to purge per-port errs and reset mask, too */
1985 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1986 if (!dd->pport[pidx].link_speed_supported)
1987 continue;
1988 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1989 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
1990 }
1991 qib_7322_set_intr_state(dd, 1);
1992}
1993
1994/* no error handling to speak of */
1995/**
1996 * qib_7322_handle_hwerrors - display hardware errors.
1997 * @dd: the qlogic_ib device
1998 * @msg: the output buffer
1999 * @msgl: the size of the output buffer
2000 *
2001 * Use same msg buffer as regular errors to avoid excessive stack
2002 * use. Most hardware errors are catastrophic, but for right now,
2003 * we'll print them and continue. We reuse the same message buffer as
2004 * qib_handle_errors() to avoid excessive stack usage.
2005 */
2006static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2007 size_t msgl)
2008{
2009 u64 hwerrs;
2010 u32 ctrl;
2011 int isfatal = 0;
2012
2013 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2014 if (!hwerrs)
2015 goto bail;
2016 if (hwerrs == ~0ULL) {
2017 qib_dev_err(dd, "Read of hardware error status failed "
2018 "(all bits set); ignoring\n");
2019 goto bail;
2020 }
2021 qib_stats.sps_hwerrs++;
2022
2023 /* Always clear the error status register, except BIST fail */
2024 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2025 ~HWE_MASK(PowerOnBISTFailed));
2026
2027 hwerrs &= dd->cspec->hwerrmask;
2028
2029 /* no EEPROM logging, yet */
2030
2031 if (hwerrs)
2032 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
2033 "(cleared)\n", (unsigned long long) hwerrs);
2034
2035 ctrl = qib_read_kreg32(dd, kr_control);
2036 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2037 /*
2038 * No recovery yet...
2039 */
2040 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2041 dd->cspec->stay_in_freeze) {
2042 /*
2043 * If any set that we aren't ignoring only make the
2044 * complaint once, in case it's stuck or recurring,
2045 * and we get here multiple times
2046 * Force link down, so switch knows, and
2047 * LEDs are turned off.
2048 */
2049 if (dd->flags & QIB_INITTED)
2050 isfatal = 1;
2051 } else
2052 qib_7322_clear_freeze(dd);
2053 }
2054
2055 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2056 isfatal = 1;
2057 strlcpy(msg, "[Memory BIST test failed, "
2058 "InfiniPath hardware unusable]", msgl);
2059 /* ignore from now on, so disable until driver reloaded */
2060 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2061 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2062 }
2063
2064 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2065
2066 /* Ignore esoteric PLL failures et al. */
2067
2068 qib_dev_err(dd, "%s hardware error\n", msg);
2069
2070 if (isfatal && !dd->diag_client) {
2071 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2072 " usable, SN %.16s\n", dd->serial);
2073 /*
2074 * for /sys status file and user programs to print; if no
2075 * trailing brace is copied, we'll know it was truncated.
2076 */
2077 if (dd->freezemsg)
2078 snprintf(dd->freezemsg, dd->freezelen,
2079 "{%s}", msg);
2080 qib_disable_after_error(dd);
2081 }
2082bail:;
2083}
2084
2085/**
2086 * qib_7322_init_hwerrors - enable hardware errors
2087 * @dd: the qlogic_ib device
2088 *
2089 * now that we have finished initializing everything that might reasonably
2090 * cause a hardware error, and cleared those errors bits as they occur,
2091 * we can enable hardware errors in the mask (potentially enabling
2092 * freeze mode), and enable hardware errors as errors (along with
2093 * everything else) in errormask
2094 */
2095static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2096{
2097 int pidx;
2098 u64 extsval;
2099
2100 extsval = qib_read_kreg64(dd, kr_extstatus);
2101 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2102 QIB_EXTS_MEMBIST_ENDTEST)))
2103 qib_dev_err(dd, "MemBIST did not complete!\n");
2104
2105 /* never clear BIST failure, so reported on each driver load */
2106 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2107 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2108
2109 /* clear all */
2110 qib_write_kreg(dd, kr_errclear, ~0ULL);
2111 /* enable errors that are masked, at least this first time. */
2112 qib_write_kreg(dd, kr_errmask, ~0ULL);
2113 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2114 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2115 if (dd->pport[pidx].link_speed_supported)
2116 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2117 ~0ULL);
2118}
2119
2120/*
2121 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2122 * on chips that are count-based, rather than trigger-based. There is no
2123 * reference counting, but that's also fine, given the intended use.
2124 * Only chip-specific because it's all register accesses
2125 */
2126static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2127{
2128 if (enable) {
2129 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2130 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2131 } else
2132 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2133 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2134}
2135
2136/*
2137 * Formerly took parameter <which> in pre-shifted,
2138 * pre-merged form with LinkCmd and LinkInitCmd
2139 * together, and assuming the zero was NOP.
2140 */
2141static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2142 u16 linitcmd)
2143{
2144 u64 mod_wd;
2145 struct qib_devdata *dd = ppd->dd;
2146 unsigned long flags;
2147
2148 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2149 /*
2150 * If we are told to disable, note that so link-recovery
2151 * code does not attempt to bring us back up.
2152 * Also reset everything that we can, so we start
2153 * completely clean when re-enabled (before we
2154 * actually issue the disable to the IBC)
2155 */
2156 qib_7322_mini_pcs_reset(ppd);
2157 spin_lock_irqsave(&ppd->lflags_lock, flags);
2158 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2159 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2160 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2161 /*
2162 * Any other linkinitcmd will lead to LINKDOWN and then
2163 * to INIT (if all is well), so clear flag to let
2164 * link-recovery code attempt to bring us back up.
2165 */
2166 spin_lock_irqsave(&ppd->lflags_lock, flags);
2167 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2168 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2169 /*
2170 * Clear status change interrupt reduction so the
2171 * new state is seen.
2172 */
2173 ppd->cpspec->ibcctrl_a &=
2174 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2175 }
2176
2177 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2178 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2179
2180 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2181 mod_wd);
2182 /* write to chip to prevent back-to-back writes of ibc reg */
2183 qib_write_kreg(dd, kr_scratch, 0);
2184
2185}
2186
2187/*
2188 * The total RCV buffer memory is 64KB, used for both ports, and is
2189 * in units of 64 bytes (same as IB flow control credit unit).
2190 * The consumedVL unit in the same registers are in 32 byte units!
2191 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2192 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2193 * in krp_rxcreditvl15, rather than 10.
2194 */
2195#define RCV_BUF_UNITSZ 64
2196#define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2197
2198static void set_vls(struct qib_pportdata *ppd)
2199{
2200 int i, numvls, totcred, cred_vl, vl0extra;
2201 struct qib_devdata *dd = ppd->dd;
2202 u64 val;
2203
2204 numvls = qib_num_vls(ppd->vls_operational);
2205
2206 /*
2207 * Set up per-VL credits. Below is kluge based on these assumptions:
2208 * 1) port is disabled at the time early_init is called.
2209 * 2) give VL15 17 credits, for two max-plausible packets.
2210 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2211 */
2212 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2213 totcred = NUM_RCV_BUF_UNITS(dd);
2214 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2215 totcred -= cred_vl;
2216 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2217 cred_vl = totcred / numvls;
2218 vl0extra = totcred - cred_vl * numvls;
2219 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2220 for (i = 1; i < numvls; i++)
2221 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2222 for (; i < 8; i++) /* no buffer space for other VLs */
2223 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2224
2225 /* Notify IBC that credits need to be recalculated */
2226 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2227 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2228 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2229 qib_write_kreg(dd, kr_scratch, 0ULL);
2230 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2231 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2232
2233 for (i = 0; i < numvls; i++)
2234 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2235 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2236
2237 /* Change the number of operational VLs */
2238 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2239 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2240 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2241 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2242 qib_write_kreg(dd, kr_scratch, 0ULL);
2243}
2244
2245/*
2246 * The code that deals with actual SerDes is in serdes_7322_init().
2247 * Compared to the code for iba7220, it is minimal.
2248 */
2249static int serdes_7322_init(struct qib_pportdata *ppd);
2250
2251/**
2252 * qib_7322_bringup_serdes - bring up the serdes
2253 * @ppd: physical port on the qlogic_ib device
2254 */
2255static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2256{
2257 struct qib_devdata *dd = ppd->dd;
2258 u64 val, guid, ibc;
2259 unsigned long flags;
2260 int ret = 0;
2261
2262 /*
2263 * SerDes model not in Pd, but still need to
2264 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2265 * eventually.
2266 */
2267 /* Put IBC in reset, sends disabled (should be in reset already) */
2268 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2269 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2270 qib_write_kreg(dd, kr_scratch, 0ULL);
2271
2272 if (qib_compat_ddr_negotiate) {
2273 ppd->cpspec->ibdeltainprog = 1;
2274 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2275 crp_ibsymbolerr);
2276 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2277 crp_iblinkerrrecov);
2278 }
2279
2280 /* flowcontrolwatermark is in units of KBytes */
2281 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2282 /*
2283 * Flow control is sent this often, even if no changes in
2284 * buffer space occur. Units are 128ns for this chip.
2285 * Set to 3usec.
2286 */
2287 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2288 /* max error tolerance */
2289 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2290 /* IB credit flow control. */
2291 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2292 /*
2293 * set initial max size pkt IBC will send, including ICRC; it's the
2294 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2295 */
2296 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2297 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2298 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2299
2300 /* initially come up waiting for TS1, without sending anything. */
2301 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2302 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2303
2304 /*
2305 * Reset the PCS interface to the serdes (and also ibc, which is still
2306 * in reset from above). Writes new value of ibcctrl_a as last step.
2307 */
2308 qib_7322_mini_pcs_reset(ppd);
2309 qib_write_kreg(dd, kr_scratch, 0ULL);
2310
2311 if (!ppd->cpspec->ibcctrl_b) {
2312 unsigned lse = ppd->link_speed_enabled;
2313
2314 /*
2315 * Not on re-init after reset, establish shadow
2316 * and force initial config.
2317 */
2318 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2319 krp_ibcctrl_b);
2320 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2321 IBA7322_IBC_SPEED_DDR |
2322 IBA7322_IBC_SPEED_SDR |
2323 IBA7322_IBC_WIDTH_AUTONEG |
2324 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2325 if (lse & (lse - 1)) /* Muliple speeds enabled */
2326 ppd->cpspec->ibcctrl_b |=
2327 (lse << IBA7322_IBC_SPEED_LSB) |
2328 IBA7322_IBC_IBTA_1_2_MASK |
2329 IBA7322_IBC_MAX_SPEED_MASK;
2330 else
2331 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2332 IBA7322_IBC_SPEED_QDR |
2333 IBA7322_IBC_IBTA_1_2_MASK :
2334 (lse == QIB_IB_DDR) ?
2335 IBA7322_IBC_SPEED_DDR :
2336 IBA7322_IBC_SPEED_SDR;
2337 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2338 (IB_WIDTH_1X | IB_WIDTH_4X))
2339 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2340 else
2341 ppd->cpspec->ibcctrl_b |=
2342 ppd->link_width_enabled == IB_WIDTH_4X ?
2343 IBA7322_IBC_WIDTH_4X_ONLY :
2344 IBA7322_IBC_WIDTH_1X_ONLY;
2345
2346 /* always enable these on driver reload, not sticky */
2347 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2348 IBA7322_IBC_HRTBT_MASK);
2349 }
2350 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2351
2352 /* setup so we have more time at CFGTEST to change H1 */
2353 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2354 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2355 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2356 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2357
2358 serdes_7322_init(ppd);
2359
2360 guid = be64_to_cpu(ppd->guid);
2361 if (!guid) {
2362 if (dd->base_guid)
2363 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2364 ppd->guid = cpu_to_be64(guid);
2365 }
2366
2367 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2368 /* write to chip to prevent back-to-back writes of ibc reg */
2369 qib_write_kreg(dd, kr_scratch, 0);
2370
2371 /* Enable port */
2372 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2373 set_vls(ppd);
2374
2375 /* be paranoid against later code motion, etc. */
2376 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2377 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2378 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2379 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2380
2381 /* Also enable IBSTATUSCHG interrupt. */
2382 val = qib_read_kreg_port(ppd, krp_errmask);
2383 qib_write_kreg_port(ppd, krp_errmask,
2384 val | ERR_MASK_N(IBStatusChanged));
2385
2386 /* Always zero until we start messing with SerDes for real */
2387 return ret;
2388}
2389
2390/**
2391 * qib_7322_quiet_serdes - set serdes to txidle
2392 * @dd: the qlogic_ib device
2393 * Called when driver is being unloaded
2394 */
2395static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2396{
2397 u64 val;
2398 unsigned long flags;
2399
2400 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2401
2402 spin_lock_irqsave(&ppd->lflags_lock, flags);
2403 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2404 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2405 wake_up(&ppd->cpspec->autoneg_wait);
2406 cancel_delayed_work(&ppd->cpspec->autoneg_work);
2407 if (ppd->dd->cspec->r1)
2408 cancel_delayed_work(&ppd->cpspec->ipg_work);
2409 flush_scheduled_work();
2410
2411 ppd->cpspec->chase_end = 0;
2412 if (ppd->cpspec->chase_timer.data) /* if initted */
2413 del_timer_sync(&ppd->cpspec->chase_timer);
2414
2415 /*
2416 * Despite the name, actually disables IBC as well. Do it when
2417 * we are as sure as possible that no more packets can be
2418 * received, following the down and the PCS reset.
2419 * The actual disabling happens in qib_7322_mini_pci_reset(),
2420 * along with the PCS being reset.
2421 */
2422 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2423 qib_7322_mini_pcs_reset(ppd);
2424
2425 /*
2426 * Update the adjusted counters so the adjustment persists
2427 * across driver reload.
2428 */
2429 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2430 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2431 struct qib_devdata *dd = ppd->dd;
2432 u64 diagc;
2433
2434 /* enable counter writes */
2435 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2436 qib_write_kreg(dd, kr_hwdiagctrl,
2437 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2438
2439 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2440 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2441 if (ppd->cpspec->ibdeltainprog)
2442 val -= val - ppd->cpspec->ibsymsnap;
2443 val -= ppd->cpspec->ibsymdelta;
2444 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2445 }
2446 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2447 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2448 if (ppd->cpspec->ibdeltainprog)
2449 val -= val - ppd->cpspec->iblnkerrsnap;
2450 val -= ppd->cpspec->iblnkerrdelta;
2451 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2452 }
2453 if (ppd->cpspec->iblnkdowndelta) {
2454 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2455 val += ppd->cpspec->iblnkdowndelta;
2456 write_7322_creg_port(ppd, crp_iblinkdown, val);
2457 }
2458 /*
2459 * No need to save ibmalfdelta since IB perfcounters
2460 * are cleared on driver reload.
2461 */
2462
2463 /* and disable counter writes */
2464 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2465 }
2466}
2467
2468/**
2469 * qib_setup_7322_setextled - set the state of the two external LEDs
2470 * @ppd: physical port on the qlogic_ib device
2471 * @on: whether the link is up or not
2472 *
2473 * The exact combo of LEDs if on is true is determined by looking
2474 * at the ibcstatus.
2475 *
2476 * These LEDs indicate the physical and logical state of IB link.
2477 * For this chip (at least with recommended board pinouts), LED1
2478 * is Yellow (logical state) and LED2 is Green (physical state),
2479 *
2480 * Note: We try to match the Mellanox HCA LED behavior as best
2481 * we can. Green indicates physical link state is OK (something is
2482 * plugged in, and we can train).
2483 * Amber indicates the link is logically up (ACTIVE).
2484 * Mellanox further blinks the amber LED to indicate data packet
2485 * activity, but we have no hardware support for that, so it would
2486 * require waking up every 10-20 msecs and checking the counters
2487 * on the chip, and then turning the LED off if appropriate. That's
2488 * visible overhead, so not something we will do.
2489 */
2490static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2491{
2492 struct qib_devdata *dd = ppd->dd;
2493 u64 extctl, ledblink = 0, val;
2494 unsigned long flags;
2495 int yel, grn;
2496
2497 /*
2498 * The diags use the LED to indicate diag info, so we leave
2499 * the external LED alone when the diags are running.
2500 */
2501 if (dd->diag_client)
2502 return;
2503
2504 /* Allow override of LED display for, e.g. Locating system in rack */
2505 if (ppd->led_override) {
2506 grn = (ppd->led_override & QIB_LED_PHYS);
2507 yel = (ppd->led_override & QIB_LED_LOG);
2508 } else if (on) {
2509 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2510 grn = qib_7322_phys_portstate(val) ==
2511 IB_PHYSPORTSTATE_LINKUP;
2512 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2513 } else {
2514 grn = 0;
2515 yel = 0;
2516 }
2517
2518 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2519 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2520 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2521 if (grn) {
2522 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2523 /*
2524 * Counts are in chip clock (4ns) periods.
2525 * This is 1/16 sec (66.6ms) on,
2526 * 3/16 sec (187.5 ms) off, with packets rcvd.
2527 */
2528 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2529 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2530 }
2531 if (yel)
2532 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2533 dd->cspec->extctrl = extctl;
2534 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2535 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2536
2537 if (ledblink) /* blink the LED on packet receive */
2538 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2539}
2540
2541#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2542static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd)
2543{
2544 struct qib_devdata *dd = rcd->dd;
2545 struct qib_chip_specific *cspec = dd->cspec;
2546 int cpu = get_cpu();
2547
2548 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) {
2549 const struct dca_reg_map *rmp;
2550
2551 cspec->rhdr_cpu[rcd->ctxt] = cpu;
2552 rmp = &dca_rcvhdr_reg_map[rcd->ctxt];
2553 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask;
2554 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |=
2555 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb;
2556 qib_write_kreg(dd, rmp->regno,
2557 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]);
2558 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable);
2559 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2560 }
2561 put_cpu();
2562}
2563
2564static void qib_update_sdma_dca(struct qib_pportdata *ppd)
2565{
2566 struct qib_devdata *dd = ppd->dd;
2567 struct qib_chip_specific *cspec = dd->cspec;
2568 int cpu = get_cpu();
2569 unsigned pidx = ppd->port - 1;
2570
2571 if (cspec->sdma_cpu[pidx] != cpu) {
2572 cspec->sdma_cpu[pidx] = cpu;
2573 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ?
2574 SYM_MASK(DCACtrlF, SendDma1DCAOPH) :
2575 SYM_MASK(DCACtrlF, SendDma0DCAOPH));
2576 cspec->dca_rcvhdr_ctrl[4] |=
2577 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) <<
2578 (ppd->hw_pidx ?
2579 SYM_LSB(DCACtrlF, SendDma1DCAOPH) :
2580 SYM_LSB(DCACtrlF, SendDma0DCAOPH));
2581 qib_write_kreg(dd, KREG_IDX(DCACtrlF),
2582 cspec->dca_rcvhdr_ctrl[4]);
2583 cspec->dca_ctrl |= ppd->hw_pidx ?
2584 SYM_MASK(DCACtrlA, SendDMAHead1DCAEnable) :
2585 SYM_MASK(DCACtrlA, SendDMAHead0DCAEnable);
2586 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl);
2587 }
2588 put_cpu();
2589}
2590
2591static void qib_setup_dca(struct qib_devdata *dd)
2592{
2593 struct qib_chip_specific *cspec = dd->cspec;
2594 int i;
2595
2596 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++)
2597 cspec->rhdr_cpu[i] = -1;
2598 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2599 cspec->sdma_cpu[i] = -1;
2600 cspec->dca_rcvhdr_ctrl[0] =
2601 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) |
2602 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) |
2603 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) |
2604 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt));
2605 cspec->dca_rcvhdr_ctrl[1] =
2606 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) |
2607 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) |
2608 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) |
2609 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt));
2610 cspec->dca_rcvhdr_ctrl[2] =
2611 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) |
2612 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) |
2613 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) |
2614 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt));
2615 cspec->dca_rcvhdr_ctrl[3] =
2616 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) |
2617 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) |
2618 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) |
2619 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt));
2620 cspec->dca_rcvhdr_ctrl[4] =
2621 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) |
2622 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt));
2623 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++)
2624 qib_write_kreg(dd, KREG_IDX(DCACtrlB) + i,
2625 cspec->dca_rcvhdr_ctrl[i]);
2626}
2627
2628#endif
2629
2630/*
2631 * Disable MSIx interrupt if enabled, call generic MSIx code
2632 * to cleanup, and clear pending MSIx interrupts.
2633 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2634 */
2635static void qib_7322_nomsix(struct qib_devdata *dd)
2636{
2637 u64 intgranted;
2638 int n;
2639
2640 dd->cspec->main_int_mask = ~0ULL;
2641 n = dd->cspec->num_msix_entries;
2642 if (n) {
2643 int i;
2644
2645 dd->cspec->num_msix_entries = 0;
2646 for (i = 0; i < n; i++)
2647 free_irq(dd->cspec->msix_entries[i].vector,
2648 dd->cspec->msix_arg[i]);
2649 qib_nomsix(dd);
2650 }
2651 /* make sure no MSIx interrupts are left pending */
2652 intgranted = qib_read_kreg64(dd, kr_intgranted);
2653 if (intgranted)
2654 qib_write_kreg(dd, kr_intgranted, intgranted);
2655}
2656
2657static void qib_7322_free_irq(struct qib_devdata *dd)
2658{
2659 if (dd->cspec->irq) {
2660 free_irq(dd->cspec->irq, dd);
2661 dd->cspec->irq = 0;
2662 }
2663 qib_7322_nomsix(dd);
2664}
2665
2666static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2667{
2668 int i;
2669
2670#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2671 if (dd->flags & QIB_DCA_ENABLED) {
2672 dca_remove_requester(&dd->pcidev->dev);
2673 dd->flags &= ~QIB_DCA_ENABLED;
2674 dd->cspec->dca_ctrl = 0;
2675 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl);
2676 }
2677#endif
2678
2679 qib_7322_free_irq(dd);
2680 kfree(dd->cspec->cntrs);
2681 kfree(dd->cspec->sendchkenable);
2682 kfree(dd->cspec->sendgrhchk);
2683 kfree(dd->cspec->sendibchk);
2684 kfree(dd->cspec->msix_entries);
2685 kfree(dd->cspec->msix_arg);
2686 for (i = 0; i < dd->num_pports; i++) {
2687 unsigned long flags;
2688 u32 mask = QSFP_GPIO_MOD_PRS_N |
2689 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2690
2691 kfree(dd->pport[i].cpspec->portcntrs);
2692 if (dd->flags & QIB_HAS_QSFP) {
2693 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2694 dd->cspec->gpio_mask &= ~mask;
2695 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2696 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2697 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2698 }
2699 if (dd->pport[i].ibport_data.smi_ah)
2700 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2701 }
2702}
2703
2704/* handle SDMA interrupts */
2705static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2706{
2707 struct qib_pportdata *ppd0 = &dd->pport[0];
2708 struct qib_pportdata *ppd1 = &dd->pport[1];
2709 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2710 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2711 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2712 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2713
2714 if (intr0)
2715 qib_sdma_intr(ppd0);
2716 if (intr1)
2717 qib_sdma_intr(ppd1);
2718
2719 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2720 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2721 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2722 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2723}
2724
2725/*
2726 * Set or clear the Send buffer available interrupt enable bit.
2727 */
2728static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2729{
2730 unsigned long flags;
2731
2732 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2733 if (needint)
2734 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2735 else
2736 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2737 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2738 qib_write_kreg(dd, kr_scratch, 0ULL);
2739 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2740}
2741
2742/*
2743 * Somehow got an interrupt with reserved bits set in interrupt status.
2744 * Print a message so we know it happened, then clear them.
2745 * keep mainline interrupt handler cache-friendly
2746 */
2747static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2748{
2749 u64 kills;
2750 char msg[128];
2751
2752 kills = istat & ~QIB_I_BITSEXTANT;
2753 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2754 " %s\n", (unsigned long long) kills, msg);
2755 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2756}
2757
2758/* keep mainline interrupt handler cache-friendly */
2759static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2760{
2761 u32 gpiostatus;
2762 int handled = 0;
2763 int pidx;
2764
2765 /*
2766 * Boards for this chip currently don't use GPIO interrupts,
2767 * so clear by writing GPIOstatus to GPIOclear, and complain
2768 * to developer. To avoid endless repeats, clear
2769 * the bits in the mask, since there is some kind of
2770 * programming error or chip problem.
2771 */
2772 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2773 /*
2774 * In theory, writing GPIOstatus to GPIOclear could
2775 * have a bad side-effect on some diagnostic that wanted
2776 * to poll for a status-change, but the various shadows
2777 * make that problematic at best. Diags will just suppress
2778 * all GPIO interrupts during such tests.
2779 */
2780 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2781 /*
2782 * Check for QSFP MOD_PRS changes
2783 * only works for single port if IB1 != pidx1
2784 */
2785 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2786 ++pidx) {
2787 struct qib_pportdata *ppd;
2788 struct qib_qsfp_data *qd;
2789 u32 mask;
2790 if (!dd->pport[pidx].link_speed_supported)
2791 continue;
2792 mask = QSFP_GPIO_MOD_PRS_N;
2793 ppd = dd->pport + pidx;
2794 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2795 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2796 u64 pins;
2797 qd = &ppd->cpspec->qsfp_data;
2798 gpiostatus &= ~mask;
2799 pins = qib_read_kreg64(dd, kr_extstatus);
2800 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2801 if (!(pins & mask)) {
2802 ++handled;
2803 qd->t_insert = get_jiffies_64();
2804 schedule_work(&qd->work);
2805 }
2806 }
2807 }
2808
2809 if (gpiostatus && !handled) {
2810 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2811 u32 gpio_irq = mask & gpiostatus;
2812
2813 /*
2814 * Clear any troublemakers, and update chip from shadow
2815 */
2816 dd->cspec->gpio_mask &= ~gpio_irq;
2817 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2818 }
2819}
2820
2821/*
2822 * Handle errors and unusual events first, separate function
2823 * to improve cache hits for fast path interrupt handling.
2824 */
2825static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2826{
2827 if (istat & ~QIB_I_BITSEXTANT)
2828 unknown_7322_ibits(dd, istat);
2829 if (istat & QIB_I_GPIO)
2830 unknown_7322_gpio_intr(dd);
2831 if (istat & QIB_I_C_ERROR)
2832 handle_7322_errors(dd);
2833 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2834 handle_7322_p_errors(dd->rcd[0]->ppd);
2835 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2836 handle_7322_p_errors(dd->rcd[1]->ppd);
2837}
2838
2839/*
2840 * Dynamically adjust the rcv int timeout for a context based on incoming
2841 * packet rate.
2842 */
2843static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2844{
2845 struct qib_devdata *dd = rcd->dd;
2846 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2847
2848 /*
2849 * Dynamically adjust idle timeout on chip
2850 * based on number of packets processed.
2851 */
2852 if (npkts < rcv_int_count && timeout > 2)
2853 timeout >>= 1;
2854 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2855 timeout = min(timeout << 1, rcv_int_timeout);
2856 else
2857 return;
2858
2859 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2860 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2861}
2862
2863/*
2864 * This is the main interrupt handler.
2865 * It will normally only be used for low frequency interrupts but may
2866 * have to handle all interrupts if INTx is enabled or fewer than normal
2867 * MSIx interrupts were allocated.
2868 * This routine should ignore the interrupt bits for any of the
2869 * dedicated MSIx handlers.
2870 */
2871static irqreturn_t qib_7322intr(int irq, void *data)
2872{
2873 struct qib_devdata *dd = data;
2874 irqreturn_t ret;
2875 u64 istat;
2876 u64 ctxtrbits;
2877 u64 rmask;
2878 unsigned i;
2879 u32 npkts;
2880
2881 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2882 /*
2883 * This return value is not great, but we do not want the
2884 * interrupt core code to remove our interrupt handler
2885 * because we don't appear to be handling an interrupt
2886 * during a chip reset.
2887 */
2888 ret = IRQ_HANDLED;
2889 goto bail;
2890 }
2891
2892 istat = qib_read_kreg64(dd, kr_intstatus);
2893
2894 if (unlikely(istat == ~0ULL)) {
2895 qib_bad_intrstatus(dd);
2896 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2897 /* don't know if it was our interrupt or not */
2898 ret = IRQ_NONE;
2899 goto bail;
2900 }
2901
2902 istat &= dd->cspec->main_int_mask;
2903 if (unlikely(!istat)) {
2904 /* already handled, or shared and not us */
2905 ret = IRQ_NONE;
2906 goto bail;
2907 }
2908
2909 qib_stats.sps_ints++;
2910 if (dd->int_counter != (u32) -1)
2911 dd->int_counter++;
2912
2913 /* handle "errors" of various kinds first, device ahead of port */
2914 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2915 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2916 INT_MASK_P(Err, 1))))
2917 unlikely_7322_intr(dd, istat);
2918
2919 /*
2920 * Clear the interrupt bits we found set, relatively early, so we
2921 * "know" know the chip will have seen this by the time we process
2922 * the queue, and will re-interrupt if necessary. The processor
2923 * itself won't take the interrupt again until we return.
2924 */
2925 qib_write_kreg(dd, kr_intclear, istat);
2926
2927 /*
2928 * Handle kernel receive queues before checking for pio buffers
2929 * available since receives can overflow; piobuf waiters can afford
2930 * a few extra cycles, since they were waiting anyway.
2931 */
2932 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2933 if (ctxtrbits) {
2934 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2935 (1ULL << QIB_I_RCVURG_LSB);
2936 for (i = 0; i < dd->first_user_ctxt; i++) {
2937 if (ctxtrbits & rmask) {
2938 ctxtrbits &= ~rmask;
2939 if (dd->rcd[i]) {
2940 qib_kreceive(dd->rcd[i], NULL, &npkts);
2941 adjust_rcv_timeout(dd->rcd[i], npkts);
2942 }
2943 }
2944 rmask <<= 1;
2945 }
2946 if (ctxtrbits) {
2947 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2948 (ctxtrbits >> QIB_I_RCVURG_LSB);
2949 qib_handle_urcv(dd, ctxtrbits);
2950 }
2951 }
2952
2953 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2954 sdma_7322_intr(dd, istat);
2955
2956 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2957 qib_ib_piobufavail(dd);
2958
2959 ret = IRQ_HANDLED;
2960bail:
2961 return ret;
2962}
2963
2964/*
2965 * Dedicated receive packet available interrupt handler.
2966 */
2967static irqreturn_t qib_7322pintr(int irq, void *data)
2968{
2969 struct qib_ctxtdata *rcd = data;
2970 struct qib_devdata *dd = rcd->dd;
2971 u32 npkts;
2972
2973 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2974 /*
2975 * This return value is not great, but we do not want the
2976 * interrupt core code to remove our interrupt handler
2977 * because we don't appear to be handling an interrupt
2978 * during a chip reset.
2979 */
2980 return IRQ_HANDLED;
2981
2982 qib_stats.sps_ints++;
2983 if (dd->int_counter != (u32) -1)
2984 dd->int_counter++;
2985
2986#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2987 if (dd->flags & QIB_DCA_ENABLED)
2988 qib_update_rhdrq_dca(rcd);
2989#endif
2990
2991 /* Clear the interrupt bit we expect to be set. */
2992 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2993 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2994
2995 qib_kreceive(rcd, NULL, &npkts);
2996 adjust_rcv_timeout(rcd, npkts);
2997
2998 return IRQ_HANDLED;
2999}
3000
3001/*
3002 * Dedicated Send buffer available interrupt handler.
3003 */
3004static irqreturn_t qib_7322bufavail(int irq, void *data)
3005{
3006 struct qib_devdata *dd = data;
3007
3008 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3009 /*
3010 * This return value is not great, but we do not want the
3011 * interrupt core code to remove our interrupt handler
3012 * because we don't appear to be handling an interrupt
3013 * during a chip reset.
3014 */
3015 return IRQ_HANDLED;
3016
3017 qib_stats.sps_ints++;
3018 if (dd->int_counter != (u32) -1)
3019 dd->int_counter++;
3020
3021 /* Clear the interrupt bit we expect to be set. */
3022 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
3023
3024 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
3025 if (dd->flags & QIB_INITTED)
3026 qib_ib_piobufavail(dd);
3027 else
3028 qib_wantpiobuf_7322_intr(dd, 0);
3029
3030 return IRQ_HANDLED;
3031}
3032
3033/*
3034 * Dedicated Send DMA interrupt handler.
3035 */
3036static irqreturn_t sdma_intr(int irq, void *data)
3037{
3038 struct qib_pportdata *ppd = data;
3039 struct qib_devdata *dd = ppd->dd;
3040
3041 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3042 /*
3043 * This return value is not great, but we do not want the
3044 * interrupt core code to remove our interrupt handler
3045 * because we don't appear to be handling an interrupt
3046 * during a chip reset.
3047 */
3048 return IRQ_HANDLED;
3049
3050 qib_stats.sps_ints++;
3051 if (dd->int_counter != (u32) -1)
3052 dd->int_counter++;
3053
3054#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
3055 if (dd->flags & QIB_DCA_ENABLED)
3056 qib_update_sdma_dca(ppd);
3057#endif
3058
3059 /* Clear the interrupt bit we expect to be set. */
3060 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3061 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
3062 qib_sdma_intr(ppd);
3063
3064 return IRQ_HANDLED;
3065}
3066
3067/*
3068 * Dedicated Send DMA idle interrupt handler.
3069 */
3070static irqreturn_t sdma_idle_intr(int irq, void *data)
3071{
3072 struct qib_pportdata *ppd = data;
3073 struct qib_devdata *dd = ppd->dd;
3074
3075 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3076 /*
3077 * This return value is not great, but we do not want the
3078 * interrupt core code to remove our interrupt handler
3079 * because we don't appear to be handling an interrupt
3080 * during a chip reset.
3081 */
3082 return IRQ_HANDLED;
3083
3084 qib_stats.sps_ints++;
3085 if (dd->int_counter != (u32) -1)
3086 dd->int_counter++;
3087
3088#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
3089 if (dd->flags & QIB_DCA_ENABLED)
3090 qib_update_sdma_dca(ppd);
3091#endif
3092
3093 /* Clear the interrupt bit we expect to be set. */
3094 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3095 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
3096 qib_sdma_intr(ppd);
3097
3098 return IRQ_HANDLED;
3099}
3100
3101/*
3102 * Dedicated Send DMA progress interrupt handler.
3103 */
3104static irqreturn_t sdma_progress_intr(int irq, void *data)
3105{
3106 struct qib_pportdata *ppd = data;
3107 struct qib_devdata *dd = ppd->dd;
3108
3109 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3110 /*
3111 * This return value is not great, but we do not want the
3112 * interrupt core code to remove our interrupt handler
3113 * because we don't appear to be handling an interrupt
3114 * during a chip reset.
3115 */
3116 return IRQ_HANDLED;
3117
3118 qib_stats.sps_ints++;
3119 if (dd->int_counter != (u32) -1)
3120 dd->int_counter++;
3121
3122#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
3123 if (dd->flags & QIB_DCA_ENABLED)
3124 qib_update_sdma_dca(ppd);
3125#endif
3126
3127 /* Clear the interrupt bit we expect to be set. */
3128 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3129 INT_MASK_P(SDmaProgress, 1) :
3130 INT_MASK_P(SDmaProgress, 0));
3131 qib_sdma_intr(ppd);
3132
3133 return IRQ_HANDLED;
3134}
3135
3136/*
3137 * Dedicated Send DMA cleanup interrupt handler.
3138 */
3139static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3140{
3141 struct qib_pportdata *ppd = data;
3142 struct qib_devdata *dd = ppd->dd;
3143
3144 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3145 /*
3146 * This return value is not great, but we do not want the
3147 * interrupt core code to remove our interrupt handler
3148 * because we don't appear to be handling an interrupt
3149 * during a chip reset.
3150 */
3151 return IRQ_HANDLED;
3152
3153 qib_stats.sps_ints++;
3154 if (dd->int_counter != (u32) -1)
3155 dd->int_counter++;
3156
3157#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
3158 if (dd->flags & QIB_DCA_ENABLED)
3159 qib_update_sdma_dca(ppd);
3160#endif
3161
3162 /* Clear the interrupt bit we expect to be set. */
3163 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3164 INT_MASK_PM(SDmaCleanupDone, 1) :
3165 INT_MASK_PM(SDmaCleanupDone, 0));
3166 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3167
3168 return IRQ_HANDLED;
3169}
3170
3171/*
3172 * Set up our chip-specific interrupt handler.
3173 * The interrupt type has already been setup, so
3174 * we just need to do the registration and error checking.
3175 * If we are using MSIx interrupts, we may fall back to
3176 * INTx later, if the interrupt handler doesn't get called
3177 * within 1/2 second (see verify_interrupt()).
3178 */
3179static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3180{
3181 int ret, i, msixnum;
3182 u64 redirect[6];
3183 u64 mask;
3184
3185 if (!dd->num_pports)
3186 return;
3187
3188 if (clearpend) {
3189 /*
3190 * if not switching interrupt types, be sure interrupts are
3191 * disabled, and then clear anything pending at this point,
3192 * because we are starting clean.
3193 */
3194 qib_7322_set_intr_state(dd, 0);
3195
3196 /* clear the reset error, init error/hwerror mask */
3197 qib_7322_init_hwerrors(dd);
3198
3199 /* clear any interrupt bits that might be set */
3200 qib_write_kreg(dd, kr_intclear, ~0ULL);
3201
3202 /* make sure no pending MSIx intr, and clear diag reg */
3203 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3204 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3205 }
3206
3207 if (!dd->cspec->num_msix_entries) {
3208 /* Try to get INTx interrupt */
3209try_intx:
3210 if (!dd->pcidev->irq) {
3211 qib_dev_err(dd, "irq is 0, BIOS error? "
3212 "Interrupts won't work\n");
3213 goto bail;
3214 }
3215 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3216 IRQF_SHARED, QIB_DRV_NAME, dd);
3217 if (ret) {
3218 qib_dev_err(dd, "Couldn't setup INTx "
3219 "interrupt (irq=%d): %d\n",
3220 dd->pcidev->irq, ret);
3221 goto bail;
3222 }
3223 dd->cspec->irq = dd->pcidev->irq;
3224 dd->cspec->main_int_mask = ~0ULL;
3225 goto bail;
3226 }
3227
3228 /* Try to get MSIx interrupts */
3229 memset(redirect, 0, sizeof redirect);
3230 mask = ~0ULL;
3231 msixnum = 0;
3232 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3233 irq_handler_t handler;
3234 const char *name;
3235 void *arg;
3236 u64 val;
3237 int lsb, reg, sh;
3238
3239 if (i < ARRAY_SIZE(irq_table)) {
3240 if (irq_table[i].port) {
3241 /* skip if for a non-configured port */
3242 if (irq_table[i].port > dd->num_pports)
3243 continue;
3244 arg = dd->pport + irq_table[i].port - 1;
3245 } else
3246 arg = dd;
3247 lsb = irq_table[i].lsb;
3248 handler = irq_table[i].handler;
3249 name = irq_table[i].name;
3250 } else {
3251 unsigned ctxt;
3252
3253 ctxt = i - ARRAY_SIZE(irq_table);
3254 /* per krcvq context receive interrupt */
3255 arg = dd->rcd[ctxt];
3256 if (!arg)
3257 continue;
3258 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3259 handler = qib_7322pintr;
3260 name = QIB_DRV_NAME " (kctx)";
3261 }
3262 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3263 handler, 0, name, arg);
3264 if (ret) {
3265 /*
3266 * Shouldn't happen since the enable said we could
3267 * have as many as we are trying to setup here.
3268 */
3269 qib_dev_err(dd, "Couldn't setup MSIx "
3270 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3271 dd->cspec->msix_entries[msixnum].vector,
3272 ret);
3273 qib_7322_nomsix(dd);
3274 goto try_intx;
3275 }
3276 dd->cspec->msix_arg[msixnum] = arg;
3277 if (lsb >= 0) {
3278 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3279 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3280 SYM_LSB(IntRedirect0, vec1);
3281 mask &= ~(1ULL << lsb);
3282 redirect[reg] |= ((u64) msixnum) << sh;
3283 }
3284 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3285 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3286 msixnum++;
3287 }
3288 /* Initialize the vector mapping */
3289 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3290 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3291 dd->cspec->main_int_mask = mask;
3292bail:;
3293}
3294
3295/**
3296 * qib_7322_boardname - fill in the board name and note features
3297 * @dd: the qlogic_ib device
3298 *
3299 * info will be based on the board revision register
3300 */
3301static unsigned qib_7322_boardname(struct qib_devdata *dd)
3302{
3303 /* Will need enumeration of board-types here */
3304 char *n;
3305 u32 boardid, namelen;
3306 unsigned features = DUAL_PORT_CAP;
3307
3308 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3309
3310 switch (boardid) {
3311 case 0:
3312 n = "InfiniPath_QLE7342_Emulation";
3313 break;
3314 case 1:
3315 n = "InfiniPath_QLE7340";
3316 dd->flags |= QIB_HAS_QSFP;
3317 features = PORT_SPD_CAP;
3318 break;
3319 case 2:
3320 n = "InfiniPath_QLE7342";
3321 dd->flags |= QIB_HAS_QSFP;
3322 break;
3323 case 3:
3324 n = "InfiniPath_QMI7342";
3325 break;
3326 case 4:
3327 n = "InfiniPath_Unsupported7342";
3328 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3329 features = 0;
3330 break;
3331 case BOARD_QMH7342:
3332 n = "InfiniPath_QMH7342";
3333 features = 0x24;
3334 break;
3335 case BOARD_QME7342:
3336 n = "InfiniPath_QME7342";
3337 break;
3338 case 15:
3339 n = "InfiniPath_QLE7342_TEST";
3340 dd->flags |= QIB_HAS_QSFP;
3341 break;
3342 default:
3343 n = "InfiniPath_QLE73xy_UNKNOWN";
3344 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3345 break;
3346 }
3347 dd->board_atten = 1; /* index into txdds_Xdr */
3348
3349 namelen = strlen(n) + 1;
3350 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3351 if (!dd->boardname)
3352 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3353 else
3354 snprintf(dd->boardname, namelen, "%s", n);
3355
3356 snprintf(dd->boardversion, sizeof(dd->boardversion),
3357 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3358 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3359 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3360 dd->majrev, dd->minrev,
3361 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3362
3363 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3364 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3365 " by module parameter\n", dd->unit);
3366 features &= PORT_SPD_CAP;
3367 }
3368
3369 return features;
3370}
3371
3372/*
3373 * This routine sleeps, so it can only be called from user context, not
3374 * from interrupt context.
3375 */
3376static int qib_do_7322_reset(struct qib_devdata *dd)
3377{
3378 u64 val;
3379 u64 *msix_vecsave;
3380 int i, msix_entries, ret = 1;
3381 u16 cmdval;
3382 u8 int_line, clinesz;
3383 unsigned long flags;
3384
3385 /* Use dev_err so it shows up in logs, etc. */
3386 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3387
3388 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3389
3390 msix_entries = dd->cspec->num_msix_entries;
3391
3392 /* no interrupts till re-initted */
3393 qib_7322_set_intr_state(dd, 0);
3394
3395 if (msix_entries) {
3396 qib_7322_nomsix(dd);
3397 /* can be up to 512 bytes, too big for stack */
3398 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3399 sizeof(u64), GFP_KERNEL);
3400 if (!msix_vecsave)
3401 qib_dev_err(dd, "No mem to save MSIx data\n");
3402 } else
3403 msix_vecsave = NULL;
3404
3405 /*
3406 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3407 * info that is set up by the BIOS, so we have to save and restore
3408 * it ourselves. There is some risk something could change it,
3409 * after we save it, but since we have disabled the MSIx, it
3410 * shouldn't be touched...
3411 */
3412 for (i = 0; i < msix_entries; i++) {
3413 u64 vecaddr, vecdata;
3414 vecaddr = qib_read_kreg64(dd, 2 * i +
3415 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3416 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3417 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3418 if (msix_vecsave) {
3419 msix_vecsave[2 * i] = vecaddr;
3420 /* save it without the masked bit set */
3421 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3422 }
3423 }
3424
3425 dd->pport->cpspec->ibdeltainprog = 0;
3426 dd->pport->cpspec->ibsymdelta = 0;
3427 dd->pport->cpspec->iblnkerrdelta = 0;
3428 dd->pport->cpspec->ibmalfdelta = 0;
3429 dd->int_counter = 0; /* so we check interrupts work again */
3430
3431 /*
3432 * Keep chip from being accessed until we are ready. Use
3433 * writeq() directly, to allow the write even though QIB_PRESENT
3434 * isnt' set.
3435 */
3436 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3437 dd->flags |= QIB_DOING_RESET;
3438 val = dd->control | QLOGIC_IB_C_RESET;
3439 writeq(val, &dd->kregbase[kr_control]);
3440
3441 for (i = 1; i <= 5; i++) {
3442 /*
3443 * Allow MBIST, etc. to complete; longer on each retry.
3444 * We sometimes get machine checks from bus timeout if no
3445 * response, so for now, make it *really* long.
3446 */
3447 msleep(1000 + (1 + i) * 3000);
3448
3449 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3450
3451 /*
3452 * Use readq directly, so we don't need to mark it as PRESENT
3453 * until we get a successful indication that all is well.
3454 */
3455 val = readq(&dd->kregbase[kr_revision]);
3456 if (val == dd->revision)
3457 break;
3458 if (i == 5) {
3459 qib_dev_err(dd, "Failed to initialize after reset, "
3460 "unusable\n");
3461 ret = 0;
3462 goto bail;
3463 }
3464 }
3465
3466 dd->flags |= QIB_PRESENT; /* it's back */
3467
3468 if (msix_entries) {
3469 /* restore the MSIx vector address and data if saved above */
3470 for (i = 0; i < msix_entries; i++) {
3471 dd->cspec->msix_entries[i].entry = i;
3472 if (!msix_vecsave || !msix_vecsave[2 * i])
3473 continue;
3474 qib_write_kreg(dd, 2 * i +
3475 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3476 msix_vecsave[2 * i]);
3477 qib_write_kreg(dd, 1 + 2 * i +
3478 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3479 msix_vecsave[1 + 2 * i]);
3480 }
3481 }
3482
3483 /* initialize the remaining registers. */
3484 for (i = 0; i < dd->num_pports; ++i)
3485 write_7322_init_portregs(&dd->pport[i]);
3486 write_7322_initregs(dd);
3487
3488 if (qib_pcie_params(dd, dd->lbus_width,
3489 &dd->cspec->num_msix_entries,
3490 dd->cspec->msix_entries))
3491 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3492 "continuing anyway\n");
3493
3494 qib_setup_7322_interrupt(dd, 1);
3495
3496 for (i = 0; i < dd->num_pports; ++i) {
3497 struct qib_pportdata *ppd = &dd->pport[i];
3498
3499 spin_lock_irqsave(&ppd->lflags_lock, flags);
3500 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3501 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3502 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3503 }
3504
3505bail:
3506 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3507 kfree(msix_vecsave);
3508 return ret;
3509}
3510
3511/**
3512 * qib_7322_put_tid - write a TID to the chip
3513 * @dd: the qlogic_ib device
3514 * @tidptr: pointer to the expected TID (in chip) to update
3515 * @tidtype: 0 for eager, 1 for expected
3516 * @pa: physical address of in memory buffer; tidinvalid if freeing
3517 */
3518static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3519 u32 type, unsigned long pa)
3520{
3521 if (!(dd->flags & QIB_PRESENT))
3522 return;
3523 if (pa != dd->tidinvalid) {
3524 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3525
3526 /* paranoia checks */
3527 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3528 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3529 pa);
3530 return;
3531 }
3532 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3533 qib_dev_err(dd, "Physical page address 0x%lx "
3534 "larger than supported\n", pa);
3535 return;
3536 }
3537
3538 if (type == RCVHQ_RCV_TYPE_EAGER)
3539 chippa |= dd->tidtemplate;
3540 else /* for now, always full 4KB page */
3541 chippa |= IBA7322_TID_SZ_4K;
3542 pa = chippa;
3543 }
3544 writeq(pa, tidptr);
3545 mmiowb();
3546}
3547
3548/**
3549 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3550 * @dd: the qlogic_ib device
3551 * @ctxt: the ctxt
3552 *
3553 * clear all TID entries for a ctxt, expected and eager.
3554 * Used from qib_close().
3555 */
3556static void qib_7322_clear_tids(struct qib_devdata *dd,
3557 struct qib_ctxtdata *rcd)
3558{
3559 u64 __iomem *tidbase;
3560 unsigned long tidinv;
3561 u32 ctxt;
3562 int i;
3563
3564 if (!dd->kregbase || !rcd)
3565 return;
3566
3567 ctxt = rcd->ctxt;
3568
3569 tidinv = dd->tidinvalid;
3570 tidbase = (u64 __iomem *)
3571 ((char __iomem *) dd->kregbase +
3572 dd->rcvtidbase +
3573 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3574
3575 for (i = 0; i < dd->rcvtidcnt; i++)
3576 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3577 tidinv);
3578
3579 tidbase = (u64 __iomem *)
3580 ((char __iomem *) dd->kregbase +
3581 dd->rcvegrbase +
3582 rcd->rcvegr_tid_base * sizeof(*tidbase));
3583
3584 for (i = 0; i < rcd->rcvegrcnt; i++)
3585 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3586 tidinv);
3587}
3588
3589/**
3590 * qib_7322_tidtemplate - setup constants for TID updates
3591 * @dd: the qlogic_ib device
3592 *
3593 * We setup stuff that we use a lot, to avoid calculating each time
3594 */
3595static void qib_7322_tidtemplate(struct qib_devdata *dd)
3596{
3597 /*
3598 * For now, we always allocate 4KB buffers (at init) so we can
3599 * receive max size packets. We may want a module parameter to
3600 * specify 2KB or 4KB and/or make it per port instead of per device
3601 * for those who want to reduce memory footprint. Note that the
3602 * rcvhdrentsize size must be large enough to hold the largest
3603 * IB header (currently 96 bytes) that we expect to handle (plus of
3604 * course the 2 dwords of RHF).
3605 */
3606 if (dd->rcvegrbufsize == 2048)
3607 dd->tidtemplate = IBA7322_TID_SZ_2K;
3608 else if (dd->rcvegrbufsize == 4096)
3609 dd->tidtemplate = IBA7322_TID_SZ_4K;
3610 dd->tidinvalid = 0;
3611}
3612
3613/**
3614 * qib_init_7322_get_base_info - set chip-specific flags for user code
3615 * @rcd: the qlogic_ib ctxt
3616 * @kbase: qib_base_info pointer
3617 *
3618 * We set the PCIE flag because the lower bandwidth on PCIe vs
3619 * HyperTransport can affect some user packet algorithims.
3620 */
3621
3622static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3623 struct qib_base_info *kinfo)
3624{
3625 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3626 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3627 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3628 if (rcd->dd->cspec->r1)
3629 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3630 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3631 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3632
3633 return 0;
3634}
3635
3636static struct qib_message_header *
3637qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3638{
3639 u32 offset = qib_hdrget_offset(rhf_addr);
3640
3641 return (struct qib_message_header *)
3642 (rhf_addr - dd->rhf_offset + offset);
3643}
3644
3645/*
3646 * Configure number of contexts.
3647 */
3648static void qib_7322_config_ctxts(struct qib_devdata *dd)
3649{
3650 unsigned long flags;
3651 u32 nchipctxts;
3652
3653 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3654 dd->cspec->numctxts = nchipctxts;
3655 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3656 /*
3657 * Set the mask for which bits from the QPN are used
3658 * to select a context number.
3659 */
3660 dd->qpn_mask = 0x3f;
3661 dd->first_user_ctxt = NUM_IB_PORTS +
3662 (qib_n_krcv_queues - 1) * dd->num_pports;
3663 if (dd->first_user_ctxt > nchipctxts)
3664 dd->first_user_ctxt = nchipctxts;
3665 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3666 } else {
3667 dd->first_user_ctxt = NUM_IB_PORTS;
3668 dd->n_krcv_queues = 1;
3669 }
3670
3671 if (!qib_cfgctxts) {
3672 int nctxts = dd->first_user_ctxt + num_online_cpus();
3673
3674 if (nctxts <= 6)
3675 dd->ctxtcnt = 6;
3676 else if (nctxts <= 10)
3677 dd->ctxtcnt = 10;
3678 else if (nctxts <= nchipctxts)
3679 dd->ctxtcnt = nchipctxts;
3680 } else if (qib_cfgctxts < dd->num_pports)
3681 dd->ctxtcnt = dd->num_pports;
3682 else if (qib_cfgctxts <= nchipctxts)
3683 dd->ctxtcnt = qib_cfgctxts;
3684 if (!dd->ctxtcnt) /* none of the above, set to max */
3685 dd->ctxtcnt = nchipctxts;
3686
3687 /*
3688 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3689 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3690 * Lock to be paranoid about later motion, etc.
3691 */
3692 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3693 if (dd->ctxtcnt > 10)
3694 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3695 else if (dd->ctxtcnt > 6)
3696 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3697 /* else configure for default 6 receive ctxts */
3698
3699 /* The XRC opcode is 5. */
3700 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3701
3702 /*
3703 * RcvCtrl *must* be written here so that the
3704 * chip understands how to change rcvegrcnt below.
3705 */
3706 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3707 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3708
3709 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3710 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3711 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3712 dd->num_pports > 1 ? 1024U : 2048U);
3713}
3714
3715static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3716{
3717
3718 int lsb, ret = 0;
3719 u64 maskr; /* right-justified mask */
3720
3721 switch (which) {
3722
3723 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3724 ret = ppd->link_width_enabled;
3725 goto done;
3726
3727 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3728 ret = ppd->link_width_active;
3729 goto done;
3730
3731 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3732 ret = ppd->link_speed_enabled;
3733 goto done;
3734
3735 case QIB_IB_CFG_SPD: /* Get current Link spd */
3736 ret = ppd->link_speed_active;
3737 goto done;
3738
3739 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3740 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3741 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3742 break;
3743
3744 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3745 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3746 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3747 break;
3748
3749 case QIB_IB_CFG_LINKLATENCY:
3750 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3751 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3752 goto done;
3753
3754 case QIB_IB_CFG_OP_VLS:
3755 ret = ppd->vls_operational;
3756 goto done;
3757
3758 case QIB_IB_CFG_VL_HIGH_CAP:
3759 ret = 16;
3760 goto done;
3761
3762 case QIB_IB_CFG_VL_LOW_CAP:
3763 ret = 16;
3764 goto done;
3765
3766 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3767 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3768 OverrunThreshold);
3769 goto done;
3770
3771 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3772 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3773 PhyerrThreshold);
3774 goto done;
3775
3776 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3777 /* will only take effect when the link state changes */
3778 ret = (ppd->cpspec->ibcctrl_a &
3779 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3780 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3781 goto done;
3782
3783 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3784 lsb = IBA7322_IBC_HRTBT_LSB;
3785 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3786 break;
3787
3788 case QIB_IB_CFG_PMA_TICKS:
3789 /*
3790 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3791 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3792 */
3793 if (ppd->link_speed_active == QIB_IB_QDR)
3794 ret = 3;
3795 else if (ppd->link_speed_active == QIB_IB_DDR)
3796 ret = 1;
3797 else
3798 ret = 0;
3799 goto done;
3800
3801 default:
3802 ret = -EINVAL;
3803 goto done;
3804 }
3805 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3806done:
3807 return ret;
3808}
3809
3810/*
3811 * Below again cribbed liberally from older version. Do not lean
3812 * heavily on it.
3813 */
3814#define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3815#define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3816 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3817
3818static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3819{
3820 struct qib_devdata *dd = ppd->dd;
3821 u64 maskr; /* right-justified mask */
3822 int lsb, ret = 0;
3823 u16 lcmd, licmd;
3824 unsigned long flags;
3825
3826 switch (which) {
3827 case QIB_IB_CFG_LIDLMC:
3828 /*
3829 * Set LID and LMC. Combined to avoid possible hazard
3830 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3831 */
3832 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3833 maskr = IBA7322_IBC_DLIDLMC_MASK;
3834 /*
3835 * For header-checking, the SLID in the packet will
3836 * be masked with SendIBSLMCMask, and compared
3837 * with SendIBSLIDAssignMask. Make sure we do not
3838 * set any bits not covered by the mask, or we get
3839 * false-positives.
3840 */
3841 qib_write_kreg_port(ppd, krp_sendslid,
3842 val & (val >> 16) & SendIBSLIDAssignMask);
3843 qib_write_kreg_port(ppd, krp_sendslidmask,
3844 (val >> 16) & SendIBSLMCMask);
3845 break;
3846
3847 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3848 ppd->link_width_enabled = val;
3849 /* convert IB value to chip register value */
3850 if (val == IB_WIDTH_1X)
3851 val = 0;
3852 else if (val == IB_WIDTH_4X)
3853 val = 1;
3854 else
3855 val = 3;
3856 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3857 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3858 break;
3859
3860 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3861 /*
3862 * As with width, only write the actual register if the
3863 * link is currently down, otherwise takes effect on next
3864 * link change. Since setting is being explictly requested
3865 * (via MAD or sysfs), clear autoneg failure status if speed
3866 * autoneg is enabled.
3867 */
3868 ppd->link_speed_enabled = val;
3869 val <<= IBA7322_IBC_SPEED_LSB;
3870 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3871 IBA7322_IBC_MAX_SPEED_MASK;
3872 if (val & (val - 1)) {
3873 /* Muliple speeds enabled */
3874 val |= IBA7322_IBC_IBTA_1_2_MASK |
3875 IBA7322_IBC_MAX_SPEED_MASK;
3876 spin_lock_irqsave(&ppd->lflags_lock, flags);
3877 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3878 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3879 } else if (val & IBA7322_IBC_SPEED_QDR)
3880 val |= IBA7322_IBC_IBTA_1_2_MASK;
3881 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3882 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3883 break;
3884
3885 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3886 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3887 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3888 break;
3889
3890 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3891 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3892 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3893 break;
3894
3895 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3896 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3897 OverrunThreshold);
3898 if (maskr != val) {
3899 ppd->cpspec->ibcctrl_a &=
3900 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3901 ppd->cpspec->ibcctrl_a |= (u64) val <<
3902 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3903 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3904 ppd->cpspec->ibcctrl_a);
3905 qib_write_kreg(dd, kr_scratch, 0ULL);
3906 }
3907 goto bail;
3908
3909 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3910 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3911 PhyerrThreshold);
3912 if (maskr != val) {
3913 ppd->cpspec->ibcctrl_a &=
3914 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3915 ppd->cpspec->ibcctrl_a |= (u64) val <<
3916 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3917 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3918 ppd->cpspec->ibcctrl_a);
3919 qib_write_kreg(dd, kr_scratch, 0ULL);
3920 }
3921 goto bail;
3922
3923 case QIB_IB_CFG_PKEYS: /* update pkeys */
3924 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3925 ((u64) ppd->pkeys[2] << 32) |
3926 ((u64) ppd->pkeys[3] << 48);
3927 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3928 goto bail;
3929
3930 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3931 /* will only take effect when the link state changes */
3932 if (val == IB_LINKINITCMD_POLL)
3933 ppd->cpspec->ibcctrl_a &=
3934 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3935 else /* SLEEP */
3936 ppd->cpspec->ibcctrl_a |=
3937 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3938 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3939 qib_write_kreg(dd, kr_scratch, 0ULL);
3940 goto bail;
3941
3942 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3943 /*
3944 * Update our housekeeping variables, and set IBC max
3945 * size, same as init code; max IBC is max we allow in
3946 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3947 * Set even if it's unchanged, print debug message only
3948 * on changes.
3949 */
3950 val = (ppd->ibmaxlen >> 2) + 1;
3951 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3952 ppd->cpspec->ibcctrl_a |= (u64)val <<
3953 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3954 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3955 ppd->cpspec->ibcctrl_a);
3956 qib_write_kreg(dd, kr_scratch, 0ULL);
3957 goto bail;
3958
3959 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3960 switch (val & 0xffff0000) {
3961 case IB_LINKCMD_DOWN:
3962 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3963 ppd->cpspec->ibmalfusesnap = 1;
3964 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3965 crp_errlink);
3966 if (!ppd->cpspec->ibdeltainprog &&
3967 qib_compat_ddr_negotiate) {
3968 ppd->cpspec->ibdeltainprog = 1;
3969 ppd->cpspec->ibsymsnap =
3970 read_7322_creg32_port(ppd,
3971 crp_ibsymbolerr);
3972 ppd->cpspec->iblnkerrsnap =
3973 read_7322_creg32_port(ppd,
3974 crp_iblinkerrrecov);
3975 }
3976 break;
3977
3978 case IB_LINKCMD_ARMED:
3979 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3980 if (ppd->cpspec->ibmalfusesnap) {
3981 ppd->cpspec->ibmalfusesnap = 0;
3982 ppd->cpspec->ibmalfdelta +=
3983 read_7322_creg32_port(ppd,
3984 crp_errlink) -
3985 ppd->cpspec->ibmalfsnap;
3986 }
3987 break;
3988
3989 case IB_LINKCMD_ACTIVE:
3990 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3991 break;
3992
3993 default:
3994 ret = -EINVAL;
3995 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3996 goto bail;
3997 }
3998 switch (val & 0xffff) {
3999 case IB_LINKINITCMD_NOP:
4000 licmd = 0;
4001 break;
4002
4003 case IB_LINKINITCMD_POLL:
4004 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
4005 break;
4006
4007 case IB_LINKINITCMD_SLEEP:
4008 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
4009 break;
4010
4011 case IB_LINKINITCMD_DISABLE:
4012 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
4013 ppd->cpspec->chase_end = 0;
4014 /*
4015 * stop state chase counter and timer, if running.
4016 * wait forpending timer, but don't clear .data (ppd)!
4017 */
4018 if (ppd->cpspec->chase_timer.expires) {
4019 del_timer_sync(&ppd->cpspec->chase_timer);
4020 ppd->cpspec->chase_timer.expires = 0;
4021 }
4022 break;
4023
4024 default:
4025 ret = -EINVAL;
4026 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
4027 val & 0xffff);
4028 goto bail;
4029 }
4030 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
4031 goto bail;
4032
4033 case QIB_IB_CFG_OP_VLS:
4034 if (ppd->vls_operational != val) {
4035 ppd->vls_operational = val;
4036 set_vls(ppd);
4037 }
4038 goto bail;
4039
4040 case QIB_IB_CFG_VL_HIGH_LIMIT:
4041 qib_write_kreg_port(ppd, krp_highprio_limit, val);
4042 goto bail;
4043
4044 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
4045 if (val > 3) {
4046 ret = -EINVAL;
4047 goto bail;
4048 }
4049 lsb = IBA7322_IBC_HRTBT_LSB;
4050 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
4051 break;
4052
4053 case QIB_IB_CFG_PORT:
4054 /* val is the port number of the switch we are connected to. */
4055 if (ppd->dd->cspec->r1) {
4056 cancel_delayed_work(&ppd->cpspec->ipg_work);
4057 ppd->cpspec->ipg_tries = 0;
4058 }
4059 goto bail;
4060
4061 default:
4062 ret = -EINVAL;
4063 goto bail;
4064 }
4065 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
4066 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
4067 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4068 qib_write_kreg(dd, kr_scratch, 0);
4069bail:
4070 return ret;
4071}
4072
4073static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
4074{
4075 int ret = 0;
4076 u64 val, ctrlb;
4077
4078 /* only IBC loopback, may add serdes and xgxs loopbacks later */
4079 if (!strncmp(what, "ibc", 3)) {
4080 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
4081 Loopback);
4082 val = 0; /* disable heart beat, so link will come up */
4083 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
4084 ppd->dd->unit, ppd->port);
4085 } else if (!strncmp(what, "off", 3)) {
4086 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
4087 Loopback);
4088 /* enable heart beat again */
4089 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
4090 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
4091 "(normal)\n", ppd->dd->unit, ppd->port);
4092 } else
4093 ret = -EINVAL;
4094 if (!ret) {
4095 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4096 ppd->cpspec->ibcctrl_a);
4097 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
4098 << IBA7322_IBC_HRTBT_LSB);
4099 ppd->cpspec->ibcctrl_b = ctrlb | val;
4100 qib_write_kreg_port(ppd, krp_ibcctrl_b,
4101 ppd->cpspec->ibcctrl_b);
4102 qib_write_kreg(ppd->dd, kr_scratch, 0);
4103 }
4104 return ret;
4105}
4106
4107static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4108 struct ib_vl_weight_elem *vl)
4109{
4110 unsigned i;
4111
4112 for (i = 0; i < 16; i++, regno++, vl++) {
4113 u32 val = qib_read_kreg_port(ppd, regno);
4114
4115 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4116 SYM_RMASK(LowPriority0_0, VirtualLane);
4117 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4118 SYM_RMASK(LowPriority0_0, Weight);
4119 }
4120}
4121
4122static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4123 struct ib_vl_weight_elem *vl)
4124{
4125 unsigned i;
4126
4127 for (i = 0; i < 16; i++, regno++, vl++) {
4128 u64 val;
4129
4130 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4131 SYM_LSB(LowPriority0_0, VirtualLane)) |
4132 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4133 SYM_LSB(LowPriority0_0, Weight));
4134 qib_write_kreg_port(ppd, regno, val);
4135 }
4136 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4137 struct qib_devdata *dd = ppd->dd;
4138 unsigned long flags;
4139
4140 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4141 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4142 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4143 qib_write_kreg(dd, kr_scratch, 0);
4144 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4145 }
4146}
4147
4148static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4149{
4150 switch (which) {
4151 case QIB_IB_TBL_VL_HIGH_ARB:
4152 get_vl_weights(ppd, krp_highprio_0, t);
4153 break;
4154
4155 case QIB_IB_TBL_VL_LOW_ARB:
4156 get_vl_weights(ppd, krp_lowprio_0, t);
4157 break;
4158
4159 default:
4160 return -EINVAL;
4161 }
4162 return 0;
4163}
4164
4165static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4166{
4167 switch (which) {
4168 case QIB_IB_TBL_VL_HIGH_ARB:
4169 set_vl_weights(ppd, krp_highprio_0, t);
4170 break;
4171
4172 case QIB_IB_TBL_VL_LOW_ARB:
4173 set_vl_weights(ppd, krp_lowprio_0, t);
4174 break;
4175
4176 default:
4177 return -EINVAL;
4178 }
4179 return 0;
4180}
4181
4182static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4183 u32 updegr, u32 egrhd)
4184{
4185 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4186 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4187 if (updegr)
4188 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4189}
4190
4191static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4192{
4193 u32 head, tail;
4194
4195 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4196 if (rcd->rcvhdrtail_kvaddr)
4197 tail = qib_get_rcvhdrtail(rcd);
4198 else
4199 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4200 return head == tail;
4201}
4202
4203#define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4204 QIB_RCVCTRL_CTXT_DIS | \
4205 QIB_RCVCTRL_TIDFLOW_ENB | \
4206 QIB_RCVCTRL_TIDFLOW_DIS | \
4207 QIB_RCVCTRL_TAILUPD_ENB | \
4208 QIB_RCVCTRL_TAILUPD_DIS | \
4209 QIB_RCVCTRL_INTRAVAIL_ENB | \
4210 QIB_RCVCTRL_INTRAVAIL_DIS | \
4211 QIB_RCVCTRL_BP_ENB | \
4212 QIB_RCVCTRL_BP_DIS)
4213
4214#define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4215 QIB_RCVCTRL_CTXT_DIS | \
4216 QIB_RCVCTRL_PKEY_DIS | \
4217 QIB_RCVCTRL_PKEY_ENB)
4218
4219/*
4220 * Modify the RCVCTRL register in chip-specific way. This
4221 * is a function because bit positions and (future) register
4222 * location is chip-specifc, but the needed operations are
4223 * generic. <op> is a bit-mask because we often want to
4224 * do multiple modifications.
4225 */
4226static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4227 int ctxt)
4228{
4229 struct qib_devdata *dd = ppd->dd;
4230 struct qib_ctxtdata *rcd;
4231 u64 mask, val;
4232 unsigned long flags;
4233
4234 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4235
4236 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4237 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4238 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4239 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4240 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4241 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4242 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4243 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4244 if (op & QIB_RCVCTRL_PKEY_ENB)
4245 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4246 if (op & QIB_RCVCTRL_PKEY_DIS)
4247 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4248 if (ctxt < 0) {
4249 mask = (1ULL << dd->ctxtcnt) - 1;
4250 rcd = NULL;
4251 } else {
4252 mask = (1ULL << ctxt);
4253 rcd = dd->rcd[ctxt];
4254 }
4255 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4256 ppd->p_rcvctrl |=
4257 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4258 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4259 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4260 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4261 }
4262 /* Write these registers before the context is enabled. */
4263 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4264 rcd->rcvhdrqtailaddr_phys);
4265 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4266 rcd->rcvhdrq_phys);
4267 rcd->seq_cnt = 1;
4268#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
4269 if (dd->flags & QIB_DCA_ENABLED)
4270 qib_update_rhdrq_dca(rcd);
4271#endif
4272 }
4273 if (op & QIB_RCVCTRL_CTXT_DIS)
4274 ppd->p_rcvctrl &=
4275 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4276 if (op & QIB_RCVCTRL_BP_ENB)
4277 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4278 if (op & QIB_RCVCTRL_BP_DIS)
4279 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4280 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4281 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4282 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4283 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4284 /*
4285 * Decide which registers to write depending on the ops enabled.
4286 * Special case is "flush" (no bits set at all)
4287 * which needs to write both.
4288 */
4289 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4290 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4291 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4292 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4293 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4294 /*
4295 * Init the context registers also; if we were
4296 * disabled, tail and head should both be zero
4297 * already from the enable, but since we don't
4298 * know, we have to do it explictly.
4299 */
4300 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4301 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4302
4303 /* be sure enabling write seen; hd/tl should be 0 */
4304 (void) qib_read_kreg32(dd, kr_scratch);
4305 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4306 dd->rcd[ctxt]->head = val;
4307 /* If kctxt, interrupt on next receive. */
4308 if (ctxt < dd->first_user_ctxt)
4309 val |= dd->rhdrhead_intr_off;
4310 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4311 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4312 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4313 /* arm rcv interrupt */
4314 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4315 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4316 }
4317 if (op & QIB_RCVCTRL_CTXT_DIS) {
4318 unsigned f;
4319
4320 /* Now that the context is disabled, clear these registers. */
4321 if (ctxt >= 0) {
4322 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4323 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4324 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4325 qib_write_ureg(dd, ur_rcvflowtable + f,
4326 TIDFLOW_ERRBITS, ctxt);
4327 } else {
4328 unsigned i;
4329
4330 for (i = 0; i < dd->cfgctxts; i++) {
4331 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4332 i, 0);
4333 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4334 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4335 qib_write_ureg(dd, ur_rcvflowtable + f,
4336 TIDFLOW_ERRBITS, i);
4337 }
4338 }
4339 }
4340 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4341}
4342
4343/*
4344 * Modify the SENDCTRL register in chip-specific way. This
4345 * is a function where there are multiple such registers with
4346 * slightly different layouts.
4347 * The chip doesn't allow back-to-back sendctrl writes, so write
4348 * the scratch register after writing sendctrl.
4349 *
4350 * Which register is written depends on the operation.
4351 * Most operate on the common register, while
4352 * SEND_ENB and SEND_DIS operate on the per-port ones.
4353 * SEND_ENB is included in common because it can change SPCL_TRIG
4354 */
4355#define SENDCTRL_COMMON_MODS (\
4356 QIB_SENDCTRL_CLEAR | \
4357 QIB_SENDCTRL_AVAIL_DIS | \
4358 QIB_SENDCTRL_AVAIL_ENB | \
4359 QIB_SENDCTRL_AVAIL_BLIP | \
4360 QIB_SENDCTRL_DISARM | \
4361 QIB_SENDCTRL_DISARM_ALL | \
4362 QIB_SENDCTRL_SEND_ENB)
4363
4364#define SENDCTRL_PORT_MODS (\
4365 QIB_SENDCTRL_CLEAR | \
4366 QIB_SENDCTRL_SEND_ENB | \
4367 QIB_SENDCTRL_SEND_DIS | \
4368 QIB_SENDCTRL_FLUSH)
4369
4370static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4371{
4372 struct qib_devdata *dd = ppd->dd;
4373 u64 tmp_dd_sendctrl;
4374 unsigned long flags;
4375
4376 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4377
4378 /* First the dd ones that are "sticky", saved in shadow */
4379 if (op & QIB_SENDCTRL_CLEAR)
4380 dd->sendctrl = 0;
4381 if (op & QIB_SENDCTRL_AVAIL_DIS)
4382 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4383 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4384 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4385 if (dd->flags & QIB_USE_SPCL_TRIG)
4386 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4387 }
4388
4389 /* Then the ppd ones that are "sticky", saved in shadow */
4390 if (op & QIB_SENDCTRL_SEND_DIS)
4391 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4392 else if (op & QIB_SENDCTRL_SEND_ENB)
4393 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4394
4395 if (op & QIB_SENDCTRL_DISARM_ALL) {
4396 u32 i, last;
4397
4398 tmp_dd_sendctrl = dd->sendctrl;
4399 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4400 /*
4401 * Disarm any buffers that are not yet launched,
4402 * disabling updates until done.
4403 */
4404 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4405 for (i = 0; i < last; i++) {
4406 qib_write_kreg(dd, kr_sendctrl,
4407 tmp_dd_sendctrl |
4408 SYM_MASK(SendCtrl, Disarm) | i);
4409 qib_write_kreg(dd, kr_scratch, 0);
4410 }
4411 }
4412
4413 if (op & QIB_SENDCTRL_FLUSH) {
4414 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4415
4416 /*
4417 * Now drain all the fifos. The Abort bit should never be
4418 * needed, so for now, at least, we don't use it.
4419 */
4420 tmp_ppd_sendctrl |=
4421 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4422 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4423 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4424 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4425 qib_write_kreg(dd, kr_scratch, 0);
4426 }
4427
4428 tmp_dd_sendctrl = dd->sendctrl;
4429
4430 if (op & QIB_SENDCTRL_DISARM)
4431 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4432 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4433 SYM_LSB(SendCtrl, DisarmSendBuf));
4434 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4435 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4436 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4437
4438 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4439 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4440 qib_write_kreg(dd, kr_scratch, 0);
4441 }
4442
4443 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4444 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4445 qib_write_kreg(dd, kr_scratch, 0);
4446 }
4447
4448 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4449 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4450 qib_write_kreg(dd, kr_scratch, 0);
4451 }
4452
4453 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4454
4455 if (op & QIB_SENDCTRL_FLUSH) {
4456 u32 v;
4457 /*
4458 * ensure writes have hit chip, then do a few
4459 * more reads, to allow DMA of pioavail registers
4460 * to occur, so in-memory copy is in sync with
4461 * the chip. Not always safe to sleep.
4462 */
4463 v = qib_read_kreg32(dd, kr_scratch);
4464 qib_write_kreg(dd, kr_scratch, v);
4465 v = qib_read_kreg32(dd, kr_scratch);
4466 qib_write_kreg(dd, kr_scratch, v);
4467 qib_read_kreg32(dd, kr_scratch);
4468 }
4469}
4470
4471#define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4472#define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4473#define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4474
4475/**
4476 * qib_portcntr_7322 - read a per-port chip counter
4477 * @ppd: the qlogic_ib pport
4478 * @creg: the counter to read (not a chip offset)
4479 */
4480static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4481{
4482 struct qib_devdata *dd = ppd->dd;
4483 u64 ret = 0ULL;
4484 u16 creg;
4485 /* 0xffff for unimplemented or synthesized counters */
4486 static const u32 xlator[] = {
4487 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4488 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4489 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4490 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4491 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4492 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4493 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4494 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4495 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4496 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4497 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4498 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4499 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4500 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4501 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4502 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4503 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4504 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4505 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4506 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4507 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4508 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4509 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4510 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4511 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4512 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4513 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4514 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4515 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4516 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4517 /*
4518 * the next 3 aren't really counters, but were implemented
4519 * as counters in older chips, so still get accessed as
4520 * though they were counters from this code.
4521 */
4522 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4523 [QIBPORTCNTR_PSSTART] = krp_psstart,
4524 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4525 /* pseudo-counter, summed for all ports */
4526 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4527 };
4528
4529 if (reg >= ARRAY_SIZE(xlator)) {
4530 qib_devinfo(ppd->dd->pcidev,
4531 "Unimplemented portcounter %u\n", reg);
4532 goto done;
4533 }
4534 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4535
4536 /* handle non-counters and special cases first */
4537 if (reg == QIBPORTCNTR_KHDROVFL) {
4538 int i;
4539
4540 /* sum over all kernel contexts (skip if mini_init) */
4541 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4542 struct qib_ctxtdata *rcd = dd->rcd[i];
4543
4544 if (!rcd || rcd->ppd != ppd)
4545 continue;
4546 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4547 }
4548 goto done;
4549 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4550 /*
4551 * Used as part of the synthesis of port_rcv_errors
4552 * in the verbs code for IBTA counters. Not needed for 7322,
4553 * because all the errors are already counted by other cntrs.
4554 */
4555 goto done;
4556 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4557 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4558 /* were counters in older chips, now per-port kernel regs */
4559 ret = qib_read_kreg_port(ppd, creg);
4560 goto done;
4561 }
4562
4563 /*
4564 * Only fast increment counters are 64 bits; use 32 bit reads to
4565 * avoid two independent reads when on Opteron.
4566 */
4567 if (xlator[reg] & _PORT_64BIT_FLAG)
4568 ret = read_7322_creg_port(ppd, creg);
4569 else
4570 ret = read_7322_creg32_port(ppd, creg);
4571 if (creg == crp_ibsymbolerr) {
4572 if (ppd->cpspec->ibdeltainprog)
4573 ret -= ret - ppd->cpspec->ibsymsnap;
4574 ret -= ppd->cpspec->ibsymdelta;
4575 } else if (creg == crp_iblinkerrrecov) {
4576 if (ppd->cpspec->ibdeltainprog)
4577 ret -= ret - ppd->cpspec->iblnkerrsnap;
4578 ret -= ppd->cpspec->iblnkerrdelta;
4579 } else if (creg == crp_errlink)
4580 ret -= ppd->cpspec->ibmalfdelta;
4581 else if (creg == crp_iblinkdown)
4582 ret += ppd->cpspec->iblnkdowndelta;
4583done:
4584 return ret;
4585}
4586
4587/*
4588 * Device counter names (not port-specific), one line per stat,
4589 * single string. Used by utilities like ipathstats to print the stats
4590 * in a way which works for different versions of drivers, without changing
4591 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4592 * display by utility.
4593 * Non-error counters are first.
4594 * Start of "error" conters is indicated by a leading "E " on the first
4595 * "error" counter, and doesn't count in label length.
4596 * The EgrOvfl list needs to be last so we truncate them at the configured
4597 * context count for the device.
4598 * cntr7322indices contains the corresponding register indices.
4599 */
4600static const char cntr7322names[] =
4601 "Interrupts\n"
4602 "HostBusStall\n"
4603 "E RxTIDFull\n"
4604 "RxTIDInvalid\n"
4605 "RxTIDFloDrop\n" /* 7322 only */
4606 "Ctxt0EgrOvfl\n"
4607 "Ctxt1EgrOvfl\n"
4608 "Ctxt2EgrOvfl\n"
4609 "Ctxt3EgrOvfl\n"
4610 "Ctxt4EgrOvfl\n"
4611 "Ctxt5EgrOvfl\n"
4612 "Ctxt6EgrOvfl\n"
4613 "Ctxt7EgrOvfl\n"
4614 "Ctxt8EgrOvfl\n"
4615 "Ctxt9EgrOvfl\n"
4616 "Ctx10EgrOvfl\n"
4617 "Ctx11EgrOvfl\n"
4618 "Ctx12EgrOvfl\n"
4619 "Ctx13EgrOvfl\n"
4620 "Ctx14EgrOvfl\n"
4621 "Ctx15EgrOvfl\n"
4622 "Ctx16EgrOvfl\n"
4623 "Ctx17EgrOvfl\n"
4624 ;
4625
4626static const u32 cntr7322indices[] = {
4627 cr_lbint | _PORT_64BIT_FLAG,
4628 cr_lbstall | _PORT_64BIT_FLAG,
4629 cr_tidfull,
4630 cr_tidinvalid,
4631 cr_rxtidflowdrop,
4632 cr_base_egrovfl + 0,
4633 cr_base_egrovfl + 1,
4634 cr_base_egrovfl + 2,
4635 cr_base_egrovfl + 3,
4636 cr_base_egrovfl + 4,
4637 cr_base_egrovfl + 5,
4638 cr_base_egrovfl + 6,
4639 cr_base_egrovfl + 7,
4640 cr_base_egrovfl + 8,
4641 cr_base_egrovfl + 9,
4642 cr_base_egrovfl + 10,
4643 cr_base_egrovfl + 11,
4644 cr_base_egrovfl + 12,
4645 cr_base_egrovfl + 13,
4646 cr_base_egrovfl + 14,
4647 cr_base_egrovfl + 15,
4648 cr_base_egrovfl + 16,
4649 cr_base_egrovfl + 17,
4650};
4651
4652/*
4653 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4654 * portcntr7322indices is somewhat complicated by some registers needing
4655 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4656 */
4657static const char portcntr7322names[] =
4658 "TxPkt\n"
4659 "TxFlowPkt\n"
4660 "TxWords\n"
4661 "RxPkt\n"
4662 "RxFlowPkt\n"
4663 "RxWords\n"
4664 "TxFlowStall\n"
4665 "TxDmaDesc\n" /* 7220 and 7322-only */
4666 "E RxDlidFltr\n" /* 7220 and 7322-only */
4667 "IBStatusChng\n"
4668 "IBLinkDown\n"
4669 "IBLnkRecov\n"
4670 "IBRxLinkErr\n"
4671 "IBSymbolErr\n"
4672 "RxLLIErr\n"
4673 "RxBadFormat\n"
4674 "RxBadLen\n"
4675 "RxBufOvrfl\n"
4676 "RxEBP\n"
4677 "RxFlowCtlErr\n"
4678 "RxICRCerr\n"
4679 "RxLPCRCerr\n"
4680 "RxVCRCerr\n"
4681 "RxInvalLen\n"
4682 "RxInvalPKey\n"
4683 "RxPktDropped\n"
4684 "TxBadLength\n"
4685 "TxDropped\n"
4686 "TxInvalLen\n"
4687 "TxUnderrun\n"
4688 "TxUnsupVL\n"
4689 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4690 "RxVL15Drop\n"
4691 "RxVlErr\n"
4692 "XcessBufOvfl\n"
4693 "RxQPBadCtxt\n" /* 7322-only from here down */
4694 "TXBadHeader\n"
4695 ;
4696
4697static const u32 portcntr7322indices[] = {
4698 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4699 crp_pktsendflow,
4700 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4701 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4702 crp_pktrcvflowctrl,
4703 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4704 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4705 crp_txsdmadesc | _PORT_64BIT_FLAG,
4706 crp_rxdlidfltr,
4707 crp_ibstatuschange,
4708 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4709 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4710 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4711 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4712 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4713 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4714 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4715 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4716 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4717 crp_rcvflowctrlviol,
4718 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4719 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4720 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4721 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4722 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4723 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4724 crp_txminmaxlenerr,
4725 crp_txdroppedpkt,
4726 crp_txlenerr,
4727 crp_txunderrun,
4728 crp_txunsupvl,
4729 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4730 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4731 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4732 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4733 crp_rxqpinvalidctxt,
4734 crp_txhdrerr,
4735};
4736
4737/* do all the setup to make the counter reads efficient later */
4738static void init_7322_cntrnames(struct qib_devdata *dd)
4739{
4740 int i, j = 0;
4741 char *s;
4742
4743 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4744 i++) {
4745 /* we always have at least one counter before the egrovfl */
4746 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4747 j = 1;
4748 s = strchr(s + 1, '\n');
4749 if (s && j)
4750 j++;
4751 }
4752 dd->cspec->ncntrs = i;
4753 if (!s)
4754 /* full list; size is without terminating null */
4755 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4756 else
4757 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4758 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4759 * sizeof(u64), GFP_KERNEL);
4760 if (!dd->cspec->cntrs)
4761 qib_dev_err(dd, "Failed allocation for counters\n");
4762
4763 for (i = 0, s = (char *)portcntr7322names; s; i++)
4764 s = strchr(s + 1, '\n');
4765 dd->cspec->nportcntrs = i - 1;
4766 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4767 for (i = 0; i < dd->num_pports; ++i) {
4768 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4769 * sizeof(u64), GFP_KERNEL);
4770 if (!dd->pport[i].cpspec->portcntrs)
4771 qib_dev_err(dd, "Failed allocation for"
4772 " portcounters\n");
4773 }
4774}
4775
4776static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4777 u64 **cntrp)
4778{
4779 u32 ret;
4780
4781 if (namep) {
4782 ret = dd->cspec->cntrnamelen;
4783 if (pos >= ret)
4784 ret = 0; /* final read after getting everything */
4785 else
4786 *namep = (char *) cntr7322names;
4787 } else {
4788 u64 *cntr = dd->cspec->cntrs;
4789 int i;
4790
4791 ret = dd->cspec->ncntrs * sizeof(u64);
4792 if (!cntr || pos >= ret) {
4793 /* everything read, or couldn't get memory */
4794 ret = 0;
4795 goto done;
4796 }
4797 *cntrp = cntr;
4798 for (i = 0; i < dd->cspec->ncntrs; i++)
4799 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4800 *cntr++ = read_7322_creg(dd,
4801 cntr7322indices[i] &
4802 _PORT_CNTR_IDXMASK);
4803 else
4804 *cntr++ = read_7322_creg32(dd,
4805 cntr7322indices[i]);
4806 }
4807done:
4808 return ret;
4809}
4810
4811static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4812 char **namep, u64 **cntrp)
4813{
4814 u32 ret;
4815
4816 if (namep) {
4817 ret = dd->cspec->portcntrnamelen;
4818 if (pos >= ret)
4819 ret = 0; /* final read after getting everything */
4820 else
4821 *namep = (char *)portcntr7322names;
4822 } else {
4823 struct qib_pportdata *ppd = &dd->pport[port];
4824 u64 *cntr = ppd->cpspec->portcntrs;
4825 int i;
4826
4827 ret = dd->cspec->nportcntrs * sizeof(u64);
4828 if (!cntr || pos >= ret) {
4829 /* everything read, or couldn't get memory */
4830 ret = 0;
4831 goto done;
4832 }
4833 *cntrp = cntr;
4834 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4835 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4836 *cntr++ = qib_portcntr_7322(ppd,
4837 portcntr7322indices[i] &
4838 _PORT_CNTR_IDXMASK);
4839 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4840 *cntr++ = read_7322_creg_port(ppd,
4841 portcntr7322indices[i] &
4842 _PORT_CNTR_IDXMASK);
4843 else
4844 *cntr++ = read_7322_creg32_port(ppd,
4845 portcntr7322indices[i]);
4846 }
4847 }
4848done:
4849 return ret;
4850}
4851
4852/**
4853 * qib_get_7322_faststats - get word counters from chip before they overflow
4854 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4855 *
4856 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4857 * real purpose of this function is to maintain the notion of
4858 * "active time", which in turn is only logged into the eeprom,
4859 * which we don;t have, yet, for 7322-based boards.
4860 *
4861 * called from add_timer
4862 */
4863static void qib_get_7322_faststats(unsigned long opaque)
4864{
4865 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4866 struct qib_pportdata *ppd;
4867 unsigned long flags;
4868 u64 traffic_wds;
4869 int pidx;
4870
4871 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4872 ppd = dd->pport + pidx;
4873
4874 /*
4875 * If port isn't enabled or not operational ports, or
4876 * diags is running (can cause memory diags to fail)
4877 * skip this port this time.
4878 */
4879 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4880 || dd->diag_client)
4881 continue;
4882
4883 /*
4884 * Maintain an activity timer, based on traffic
4885 * exceeding a threshold, so we need to check the word-counts
4886 * even if they are 64-bit.
4887 */
4888 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4889 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4890 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4891 traffic_wds -= ppd->dd->traffic_wds;
4892 ppd->dd->traffic_wds += traffic_wds;
4893 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4894 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4895 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4896 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4897 QIB_IB_QDR) &&
4898 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4899 QIBL_LINKACTIVE)) &&
4900 ppd->cpspec->qdr_dfe_time &&
4901 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) {
4902 ppd->cpspec->qdr_dfe_on = 0;
4903
4904 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4905 ppd->dd->cspec->r1 ?
4906 QDR_STATIC_ADAPT_INIT_R1 :
4907 QDR_STATIC_ADAPT_INIT);
4908 force_h1(ppd);
4909 }
4910 }
4911 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4912}
4913
4914/*
4915 * If we were using MSIx, try to fallback to INTx.
4916 */
4917static int qib_7322_intr_fallback(struct qib_devdata *dd)
4918{
4919 if (!dd->cspec->num_msix_entries)
4920 return 0; /* already using INTx */
4921
4922 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4923 " trying INTx interrupts\n");
4924 qib_7322_nomsix(dd);
4925 qib_enable_intx(dd->pcidev);
4926 qib_setup_7322_interrupt(dd, 0);
4927 return 1;
4928}
4929
4930/*
4931 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4932 * than resetting the IBC or external link state, and useful in some
4933 * cases to cause some retraining. To do this right, we reset IBC
4934 * as well, then return to previous state (which may be still in reset)
4935 * NOTE: some callers of this "know" this writes the current value
4936 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4937 * check all callers.
4938 */
4939static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4940{
4941 u64 val;
4942 struct qib_devdata *dd = ppd->dd;
4943 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4944 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4945 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4946
4947 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4948 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4949 ppd->cpspec->ibcctrl_a &
4950 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4951
4952 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4953 qib_read_kreg32(dd, kr_scratch);
4954 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4955 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4956 qib_write_kreg(dd, kr_scratch, 0ULL);
4957}
4958
4959/*
4960 * This code for non-IBTA-compliant IB speed negotiation is only known to
4961 * work for the SDR to DDR transition, and only between an HCA and a switch
4962 * with recent firmware. It is based on observed heuristics, rather than
4963 * actual knowledge of the non-compliant speed negotiation.
4964 * It has a number of hard-coded fields, since the hope is to rewrite this
4965 * when a spec is available on how the negoation is intended to work.
4966 */
4967static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4968 u32 dcnt, u32 *data)
4969{
4970 int i;
4971 u64 pbc;
4972 u32 __iomem *piobuf;
4973 u32 pnum, control, len;
4974 struct qib_devdata *dd = ppd->dd;
4975
4976 i = 0;
4977 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4978 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4979 pbc = ((u64) control << 32) | len;
4980 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4981 if (i++ > 15)
4982 return;
4983 udelay(2);
4984 }
4985 /* disable header check on this packet, since it can't be valid */
4986 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4987 writeq(pbc, piobuf);
4988 qib_flush_wc();
4989 qib_pio_copy(piobuf + 2, hdr, 7);
4990 qib_pio_copy(piobuf + 9, data, dcnt);
4991 if (dd->flags & QIB_USE_SPCL_TRIG) {
4992 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4993
4994 qib_flush_wc();
4995 __raw_writel(0xaebecede, piobuf + spcl_off);
4996 }
4997 qib_flush_wc();
4998 qib_sendbuf_done(dd, pnum);
4999 /* and re-enable hdr check */
5000 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
5001}
5002
5003/*
5004 * _start packet gets sent twice at start, _done gets sent twice at end
5005 */
5006static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
5007{
5008 struct qib_devdata *dd = ppd->dd;
5009 static u32 swapped;
5010 u32 dw, i, hcnt, dcnt, *data;
5011 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
5012 static u32 madpayload_start[0x40] = {
5013 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5014 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5015 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
5016 };
5017 static u32 madpayload_done[0x40] = {
5018 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
5019 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
5020 0x40000001, 0x1388, 0x15e, /* rest 0's */
5021 };
5022
5023 dcnt = ARRAY_SIZE(madpayload_start);
5024 hcnt = ARRAY_SIZE(hdr);
5025 if (!swapped) {
5026 /* for maintainability, do it at runtime */
5027 for (i = 0; i < hcnt; i++) {
5028 dw = (__force u32) cpu_to_be32(hdr[i]);
5029 hdr[i] = dw;
5030 }
5031 for (i = 0; i < dcnt; i++) {
5032 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
5033 madpayload_start[i] = dw;
5034 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
5035 madpayload_done[i] = dw;
5036 }
5037 swapped = 1;
5038 }
5039
5040 data = which ? madpayload_done : madpayload_start;
5041
5042 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5043 qib_read_kreg64(dd, kr_scratch);
5044 udelay(2);
5045 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
5046 qib_read_kreg64(dd, kr_scratch);
5047 udelay(2);
5048}
5049
5050/*
5051 * Do the absolute minimum to cause an IB speed change, and make it
5052 * ready, but don't actually trigger the change. The caller will
5053 * do that when ready (if link is in Polling training state, it will
5054 * happen immediately, otherwise when link next goes down)
5055 *
5056 * This routine should only be used as part of the DDR autonegotation
5057 * code for devices that are not compliant with IB 1.2 (or code that
5058 * fixes things up for same).
5059 *
5060 * When link has gone down, and autoneg enabled, or autoneg has
5061 * failed and we give up until next time we set both speeds, and
5062 * then we want IBTA enabled as well as "use max enabled speed.
5063 */
5064static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
5065{
5066 u64 newctrlb;
5067 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
5068 IBA7322_IBC_IBTA_1_2_MASK |
5069 IBA7322_IBC_MAX_SPEED_MASK);
5070
5071 if (speed & (speed - 1)) /* multiple speeds */
5072 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
5073 IBA7322_IBC_IBTA_1_2_MASK |
5074 IBA7322_IBC_MAX_SPEED_MASK;
5075 else
5076 newctrlb |= speed == QIB_IB_QDR ?
5077 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
5078 ((speed == QIB_IB_DDR ?
5079 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
5080
5081 if (newctrlb == ppd->cpspec->ibcctrl_b)
5082 return;
5083
5084 ppd->cpspec->ibcctrl_b = newctrlb;
5085 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
5086 qib_write_kreg(ppd->dd, kr_scratch, 0);
5087}
5088
5089/*
5090 * This routine is only used when we are not talking to another
5091 * IB 1.2-compliant device that we think can do DDR.
5092 * (This includes all existing switch chips as of Oct 2007.)
5093 * 1.2-compliant devices go directly to DDR prior to reaching INIT
5094 */
5095static void try_7322_autoneg(struct qib_pportdata *ppd)
5096{
5097 unsigned long flags;
5098
5099 spin_lock_irqsave(&ppd->lflags_lock, flags);
5100 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5101 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5102 qib_autoneg_7322_send(ppd, 0);
5103 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5104 qib_7322_mini_pcs_reset(ppd);
5105 /* 2 msec is minimum length of a poll cycle */
5106 schedule_delayed_work(&ppd->cpspec->autoneg_work,
5107 msecs_to_jiffies(2));
5108}
5109
5110/*
5111 * Handle the empirically determined mechanism for auto-negotiation
5112 * of DDR speed with switches.
5113 */
5114static void autoneg_7322_work(struct work_struct *work)
5115{
5116 struct qib_pportdata *ppd;
5117 struct qib_devdata *dd;
5118 u64 startms;
5119 u32 i;
5120 unsigned long flags;
5121
5122 ppd = container_of(work, struct qib_chippport_specific,
5123 autoneg_work.work)->ppd;
5124 dd = ppd->dd;
5125
5126 startms = jiffies_to_msecs(jiffies);
5127
5128 /*
5129 * Busy wait for this first part, it should be at most a
5130 * few hundred usec, since we scheduled ourselves for 2msec.
5131 */
5132 for (i = 0; i < 25; i++) {
5133 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5134 == IB_7322_LT_STATE_POLLQUIET) {
5135 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5136 break;
5137 }
5138 udelay(100);
5139 }
5140
5141 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5142 goto done; /* we got there early or told to stop */
5143
5144 /* we expect this to timeout */
5145 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5146 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5147 msecs_to_jiffies(90)))
5148 goto done;
5149 qib_7322_mini_pcs_reset(ppd);
5150
5151 /* we expect this to timeout */
5152 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5153 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5154 msecs_to_jiffies(1700)))
5155 goto done;
5156 qib_7322_mini_pcs_reset(ppd);
5157
5158 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5159
5160 /*
5161 * Wait up to 250 msec for link to train and get to INIT at DDR;
5162 * this should terminate early.
5163 */
5164 wait_event_timeout(ppd->cpspec->autoneg_wait,
5165 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5166 msecs_to_jiffies(250));
5167done:
5168 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5169 spin_lock_irqsave(&ppd->lflags_lock, flags);
5170 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5171 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5172 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5173 ppd->cpspec->autoneg_tries = 0;
5174 }
5175 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5176 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5177 }
5178}
5179
5180/*
5181 * This routine is used to request IPG set in the QLogic switch.
5182 * Only called if r1.
5183 */
5184static void try_7322_ipg(struct qib_pportdata *ppd)
5185{
5186 struct qib_ibport *ibp = &ppd->ibport_data;
5187 struct ib_mad_send_buf *send_buf;
5188 struct ib_mad_agent *agent;
5189 struct ib_smp *smp;
5190 unsigned delay;
5191 int ret;
5192
5193 agent = ibp->send_agent;
5194 if (!agent)
5195 goto retry;
5196
5197 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5198 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5199 if (IS_ERR(send_buf))
5200 goto retry;
5201
5202 if (!ibp->smi_ah) {
5203 struct ib_ah_attr attr;
5204 struct ib_ah *ah;
5205
5206 memset(&attr, 0, sizeof attr);
5207 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5208 attr.port_num = ppd->port;
5209 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5210 if (IS_ERR(ah))
5211 ret = -EINVAL;
5212 else {
5213 send_buf->ah = ah;
5214 ibp->smi_ah = to_iah(ah);
5215 ret = 0;
5216 }
5217 } else {
5218 send_buf->ah = &ibp->smi_ah->ibah;
5219 ret = 0;
5220 }
5221
5222 smp = send_buf->mad;
5223 smp->base_version = IB_MGMT_BASE_VERSION;
5224 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5225 smp->class_version = 1;
5226 smp->method = IB_MGMT_METHOD_SEND;
5227 smp->hop_cnt = 1;
5228 smp->attr_id = QIB_VENDOR_IPG;
5229 smp->attr_mod = 0;
5230
5231 if (!ret)
5232 ret = ib_post_send_mad(send_buf, NULL);
5233 if (ret)
5234 ib_free_send_mad(send_buf);
5235retry:
5236 delay = 2 << ppd->cpspec->ipg_tries;
5237 schedule_delayed_work(&ppd->cpspec->ipg_work, msecs_to_jiffies(delay));
5238}
5239
5240/*
5241 * Timeout handler for setting IPG.
5242 * Only called if r1.
5243 */
5244static void ipg_7322_work(struct work_struct *work)
5245{
5246 struct qib_pportdata *ppd;
5247
5248 ppd = container_of(work, struct qib_chippport_specific,
5249 ipg_work.work)->ppd;
5250 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5251 && ++ppd->cpspec->ipg_tries <= 10)
5252 try_7322_ipg(ppd);
5253}
5254
5255static u32 qib_7322_iblink_state(u64 ibcs)
5256{
5257 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5258
5259 switch (state) {
5260 case IB_7322_L_STATE_INIT:
5261 state = IB_PORT_INIT;
5262 break;
5263 case IB_7322_L_STATE_ARM:
5264 state = IB_PORT_ARMED;
5265 break;
5266 case IB_7322_L_STATE_ACTIVE:
5267 /* fall through */
5268 case IB_7322_L_STATE_ACT_DEFER:
5269 state = IB_PORT_ACTIVE;
5270 break;
5271 default: /* fall through */
5272 case IB_7322_L_STATE_DOWN:
5273 state = IB_PORT_DOWN;
5274 break;
5275 }
5276 return state;
5277}
5278
5279/* returns the IBTA port state, rather than the IBC link training state */
5280static u8 qib_7322_phys_portstate(u64 ibcs)
5281{
5282 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5283 return qib_7322_physportstate[state];
5284}
5285
5286static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5287{
5288 int ret = 0, symadj = 0;
5289 unsigned long flags;
5290 int mult;
5291
5292 spin_lock_irqsave(&ppd->lflags_lock, flags);
5293 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5294 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5295
5296 /* Update our picture of width and speed from chip */
5297 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5298 ppd->link_speed_active = QIB_IB_QDR;
5299 mult = 4;
5300 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5301 ppd->link_speed_active = QIB_IB_DDR;
5302 mult = 2;
5303 } else {
5304 ppd->link_speed_active = QIB_IB_SDR;
5305 mult = 1;
5306 }
5307 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5308 ppd->link_width_active = IB_WIDTH_4X;
5309 mult *= 4;
5310 } else
5311 ppd->link_width_active = IB_WIDTH_1X;
5312 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5313
5314 if (!ibup) {
5315 u64 clr;
5316
5317 /* Link went down. */
5318 /* do IPG MAD again after linkdown, even if last time failed */
5319 ppd->cpspec->ipg_tries = 0;
5320 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5321 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5322 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5323 if (clr)
5324 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5325 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5326 QIBL_IB_AUTONEG_INPROG)))
5327 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5328 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
a77fcf89
RC		 5329 /* unlock the Tx settings, speed may change */
5330 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5331 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5332 reset_tx_deemphasis_override));
f931551b 5333 qib_cancel_sends(ppd);
a77fcf89
RC		 5334 /* on link down, ensure sane pcs state */
5335 qib_7322_mini_pcs_reset(ppd);
f931551b
RC		 5336 spin_lock_irqsave(&ppd->sdma_lock, flags);
5337 if (__qib_sdma_running(ppd))
5338 __qib_sdma_process_event(ppd,
5339 qib_sdma_event_e70_go_idle);
5340 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5341 }
5342 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5343 if (clr == ppd->cpspec->iblnkdownsnap)
5344 ppd->cpspec->iblnkdowndelta++;
5345 } else {
5346 if (qib_compat_ddr_negotiate &&
5347 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5348 QIBL_IB_AUTONEG_INPROG)) &&
5349 ppd->link_speed_active == QIB_IB_SDR &&
5350 (ppd->link_speed_enabled & QIB_IB_DDR)
5351 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5352 /* we are SDR, and auto-negotiation enabled */
5353 ++ppd->cpspec->autoneg_tries;
5354 if (!ppd->cpspec->ibdeltainprog) {
5355 ppd->cpspec->ibdeltainprog = 1;
5356 ppd->cpspec->ibsymdelta +=
5357 read_7322_creg32_port(ppd,
5358 crp_ibsymbolerr) -
5359 ppd->cpspec->ibsymsnap;
5360 ppd->cpspec->iblnkerrdelta +=
5361 read_7322_creg32_port(ppd,
5362 crp_iblinkerrrecov) -
5363 ppd->cpspec->iblnkerrsnap;
5364 }
5365 try_7322_autoneg(ppd);
5366 ret = 1; /* no other IB status change processing */
5367 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5368 ppd->link_speed_active == QIB_IB_SDR) {
5369 qib_autoneg_7322_send(ppd, 1);
5370 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5371 qib_7322_mini_pcs_reset(ppd);
5372 udelay(2);
5373 ret = 1; /* no other IB status change processing */
5374 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5375 (ppd->link_speed_active & QIB_IB_DDR)) {
5376 spin_lock_irqsave(&ppd->lflags_lock, flags);
5377 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5378 QIBL_IB_AUTONEG_FAILED);
5379 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5380 ppd->cpspec->autoneg_tries = 0;
5381 /* re-enable SDR, for next link down */
5382 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5383 wake_up(&ppd->cpspec->autoneg_wait);
5384 symadj = 1;
5385 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5386 /*
5387 * Clear autoneg failure flag, and do setup
5388 * so we'll try next time link goes down and
5389 * back to INIT (possibly connected to a
5390 * different device).
5391 */
5392 spin_lock_irqsave(&ppd->lflags_lock, flags);
5393 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5394 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5395 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5396 symadj = 1;
5397 }
5398 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5399 symadj = 1;
5400 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5401 try_7322_ipg(ppd);
5402 if (!ppd->cpspec->recovery_init)
5403 setup_7322_link_recovery(ppd, 0);
5404 ppd->cpspec->qdr_dfe_time = jiffies +
5405 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5406 }
5407 ppd->cpspec->ibmalfusesnap = 0;
5408 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5409 crp_errlink);
5410 }
5411 if (symadj) {
5412 ppd->cpspec->iblnkdownsnap =
5413 read_7322_creg32_port(ppd, crp_iblinkdown);
5414 if (ppd->cpspec->ibdeltainprog) {
5415 ppd->cpspec->ibdeltainprog = 0;
5416 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5417 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5418 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5419 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5420 }
5421 } else if (!ibup && qib_compat_ddr_negotiate &&
5422 !ppd->cpspec->ibdeltainprog &&
5423 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5424 ppd->cpspec->ibdeltainprog = 1;
5425 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5426 crp_ibsymbolerr);
5427 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5428 crp_iblinkerrrecov);
5429 }
5430
5431 if (!ret)
5432 qib_setup_7322_setextled(ppd, ibup);
5433 return ret;
5434}
5435
5436/*
5437 * Does read/modify/write to appropriate registers to
5438 * set output and direction bits selected by mask.
5439 * these are in their canonical postions (e.g. lsb of
5440 * dir will end up in D48 of extctrl on existing chips).
5441 * returns contents of GP Inputs.
5442 */
5443static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5444{
5445 u64 read_val, new_out;
5446 unsigned long flags;
5447
5448 if (mask) {
5449 /* some bits being written, lock access to GPIO */
5450 dir &= mask;
5451 out &= mask;
5452 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5453 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5454 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5455 new_out = (dd->cspec->gpio_out & ~mask) | out;
5456
5457 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5458 qib_write_kreg(dd, kr_gpio_out, new_out);
5459 dd->cspec->gpio_out = new_out;
5460 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5461 }
5462 /*
5463 * It is unlikely that a read at this time would get valid
5464 * data on a pin whose direction line was set in the same
5465 * call to this function. We include the read here because
5466 * that allows us to potentially combine a change on one pin with
5467 * a read on another, and because the old code did something like
5468 * this.
5469 */
5470 read_val = qib_read_kreg64(dd, kr_extstatus);
5471 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5472}
5473
5474/* Enable writes to config EEPROM, if possible. Returns previous state */
5475static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5476{
5477 int prev_wen;
5478 u32 mask;
5479
5480 mask = 1 << QIB_EEPROM_WEN_NUM;
5481 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5482 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5483
5484 return prev_wen & 1;
5485}
5486
5487/*
5488 * Read fundamental info we need to use the chip. These are
5489 * the registers that describe chip capabilities, and are
5490 * saved in shadow registers.
5491 */
5492static void get_7322_chip_params(struct qib_devdata *dd)
5493{
5494 u64 val;
5495 u32 piobufs;
5496 int mtu;
5497
5498 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5499
5500 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5501
5502 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5503 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5504 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5505 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5506 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5507
5508 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5509 dd->piobcnt2k = val & ~0U;
5510 dd->piobcnt4k = val >> 32;
5511 val = qib_read_kreg64(dd, kr_sendpiosize);
5512 dd->piosize2k = val & ~0U;
5513 dd->piosize4k = val >> 32;
5514
5515 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5516 if (mtu == -1)
5517 mtu = QIB_DEFAULT_MTU;
5518 dd->pport[0].ibmtu = (u32)mtu;
5519 dd->pport[1].ibmtu = (u32)mtu;
5520
5521 /* these may be adjusted in init_chip_wc_pat() */
5522 dd->pio2kbase = (u32 __iomem *)
5523 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5524 dd->pio4kbase = (u32 __iomem *)
5525 ((char __iomem *) dd->kregbase +
5526 (dd->piobufbase >> 32));
5527 /*
5528 * 4K buffers take 2 pages; we use roundup just to be
5529 * paranoid; we calculate it once here, rather than on
5530 * ever buf allocate
5531 */
5532 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5533
5534 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5535
5536 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5537 (sizeof(u64) * BITS_PER_BYTE / 2);
5538}
5539
5540/*
5541 * The chip base addresses in cspec and cpspec have to be set
5542 * after possible init_chip_wc_pat(), rather than in
5543 * get_7322_chip_params(), so split out as separate function
5544 */
5545static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5546{
5547 u32 cregbase;
5548 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5549
5550 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5551 (char __iomem *)dd->kregbase);
5552
5553 dd->egrtidbase = (u64 __iomem *)
5554 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5555
5556 /* port registers are defined as relative to base of chip */
5557 dd->pport[0].cpspec->kpregbase =
5558 (u64 __iomem *)((char __iomem *)dd->kregbase);
5559 dd->pport[1].cpspec->kpregbase =
5560 (u64 __iomem *)(dd->palign +
5561 (char __iomem *)dd->kregbase);
5562 dd->pport[0].cpspec->cpregbase =
5563 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5564 kr_counterregbase) + (char __iomem *)dd->kregbase);
5565 dd->pport[1].cpspec->cpregbase =
5566 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5567 kr_counterregbase) + (char __iomem *)dd->kregbase);
5568}
5569
5570/*
5571 * This is a fairly special-purpose observer, so we only support
5572 * the port-specific parts of SendCtrl
5573 */
5574
5575#define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5576 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5577 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5578 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5579 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5580 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5581 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5582
5583static int sendctrl_hook(struct qib_devdata *dd,
5584 const struct diag_observer *op, u32 offs,
5585 u64 *data, u64 mask, int only_32)
5586{
5587 unsigned long flags;
5588 unsigned idx;
5589 unsigned pidx;
5590 struct qib_pportdata *ppd = NULL;
5591 u64 local_data, all_bits;
5592
5593 /*
5594 * The fixed correspondence between Physical ports and pports is
5595 * severed. We need to hunt for the ppd that corresponds
5596 * to the offset we got. And we have to do that without admitting
5597 * we know the stride, apparently.
5598 */
5599 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5600 u64 __iomem *psptr;
5601 u32 psoffs;
5602
5603 ppd = dd->pport + pidx;
5604 if (!ppd->cpspec->kpregbase)
5605 continue;
5606
5607 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5608 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5609 if (psoffs == offs)
5610 break;
5611 }
5612
5613 /* If pport is not being managed by driver, just avoid shadows. */
5614 if (pidx >= dd->num_pports)
5615 ppd = NULL;
5616
5617 /* In any case, "idx" is flat index in kreg space */
5618 idx = offs / sizeof(u64);
5619
5620 all_bits = ~0ULL;
5621 if (only_32)
5622 all_bits >>= 32;
5623
5624 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5625 if (!ppd || (mask & all_bits) != all_bits) {
5626 /*
5627 * At least some mask bits are zero, so we need
5628 * to read. The judgement call is whether from
5629 * reg or shadow. First-cut: read reg, and complain
5630 * if any bits which should be shadowed are different
5631 * from their shadowed value.
5632 */
5633 if (only_32)
5634 local_data = (u64)qib_read_kreg32(dd, idx);
5635 else
5636 local_data = qib_read_kreg64(dd, idx);
5637 *data = (local_data & ~mask) | (*data & mask);
5638 }
5639 if (mask) {
5640 /*
5641 * At least some mask bits are one, so we need
5642 * to write, but only shadow some bits.
5643 */
5644 u64 sval, tval; /* Shadowed, transient */
5645
5646 /*
5647 * New shadow val is bits we don't want to touch,
5648 * ORed with bits we do, that are intended for shadow.
5649 */
5650 if (ppd) {
5651 sval = ppd->p_sendctrl & ~mask;
5652 sval |= *data & SENDCTRL_SHADOWED & mask;
5653 ppd->p_sendctrl = sval;
5654 } else
5655 sval = *data & SENDCTRL_SHADOWED & mask;
5656 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5657 qib_write_kreg(dd, idx, tval);
5658 qib_write_kreg(dd, kr_scratch, 0Ull);
5659 }
5660 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5661 return only_32 ? 4 : 8;
5662}
5663
5664static const struct diag_observer sendctrl_0_observer = {
5665 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5666 KREG_IDX(SendCtrl_0) * sizeof(u64)
5667};
5668
5669static const struct diag_observer sendctrl_1_observer = {
5670 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5671 KREG_IDX(SendCtrl_1) * sizeof(u64)
5672};
5673
5674static ushort sdma_fetch_prio = 8;
5675module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5676MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5677
5678/* Besides logging QSFP events, we set appropriate TxDDS values */
5679static void init_txdds_table(struct qib_pportdata *ppd, int override);
5680
5681static void qsfp_7322_event(struct work_struct *work)
5682{
5683 struct qib_qsfp_data *qd;
5684 struct qib_pportdata *ppd;
5685 u64 pwrup;
5686 int ret;
5687 u32 le2;
5688
5689 qd = container_of(work, struct qib_qsfp_data, work);
5690 ppd = qd->ppd;
5691 pwrup = qd->t_insert + msecs_to_jiffies(QSFP_PWR_LAG_MSEC);
5692
5693 /*
5694 * Some QSFP's not only do not respond until the full power-up
5695 * time, but may behave badly if we try. So hold off responding
5696 * to insertion.
5697 */
5698 while (1) {
5699 u64 now = get_jiffies_64();
5700 if (time_after64(now, pwrup))
5701 break;
5702 msleep(1);
5703 }
5704 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5705 /*
5706 * Need to change LE2 back to defaults if we couldn't
5707 * read the cable type (to handle cable swaps), so do this
5708 * even on failure to read cable information. We don't
5709 * get here for QME, so IS_QME check not needed here.
5710 */
5711 le2 = (!ret && qd->cache.atten[1] >= qib_long_atten &&
5712 !ppd->dd->cspec->r1 && QSFP_IS_CU(qd->cache.tech)) ?
5713 LE2_5m : LE2_DEFAULT;
5714 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5715 init_txdds_table(ppd, 0);
5716}
5717
5718/*
5719 * There is little we can do but complain to the user if QSFP
5720 * initialization fails.
5721 */
5722static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5723{
5724 unsigned long flags;
5725 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5726 struct qib_devdata *dd = ppd->dd;
5727 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5728
5729 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5730 qd->ppd = ppd;
5731 qib_qsfp_init(qd, qsfp_7322_event);
5732 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5733 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5734 dd->cspec->gpio_mask |= mod_prs_bit;
5735 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5736 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5737 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5738}
5739
5740/*
a77fcf89 5741 * called at device initialization time, and also if the txselect
f931551b
RC		 5742 * module parameter is changed. This is used for cables that don't
5743 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5744 * We initialize to the default, then if there is a specific
a77fcf89
RC		 5745 * unit,port match, we use that (and set it immediately, for the
5746 * current speed, if the link is at INIT or better).
f931551b 5747 * String format is "default# unit#,port#=# ... u,p=#", separators must
a77fcf89
RC		 5748 * be a SPACE character. A newline terminates. The u,p=# tuples may
5749 * optionally have "u,p=#,#", where the final # is the H1 value
f931551b
RC		 5750 * The last specific match is used (actually, all are used, but last
5751 * one is the one that winds up set); if none at all, fall back on default.
5752 */
5753static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5754{
5755 char *nxt, *str;
a77fcf89 5756 u32 pidx, unit, port, deflt, h1;
f931551b 5757 unsigned long val;
a77fcf89 5758 int any = 0, seth1;
f931551b 5759
a77fcf89 5760 str = txselect_list;
f931551b 5761
a77fcf89 5762 /* default number is validated in setup_txselect() */
f931551b
RC		 5763 deflt = simple_strtoul(str, &nxt, 0);
5764 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5765 dd->pport[pidx].cpspec->no_eep = deflt;
5766
5767 while (*nxt && nxt[1]) {
5768 str = ++nxt;
5769 unit = simple_strtoul(str, &nxt, 0);
5770 if (nxt == str || !*nxt || *nxt != ',') {
5771 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5772 ;
5773 continue;
5774 }
5775 str = ++nxt;
5776 port = simple_strtoul(str, &nxt, 0);
5777 if (nxt == str || *nxt != '=') {
5778 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5779 ;
5780 continue;
5781 }
5782 str = ++nxt;
5783 val = simple_strtoul(str, &nxt, 0);
5784 if (nxt == str) {
5785 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5786 ;
5787 continue;
5788 }
a77fcf89 5789 if (val >= TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)
f931551b 5790 continue;
a77fcf89
RC		 5791 seth1 = 0;
5792 h1 = 0; /* gcc thinks it might be used uninitted */
5793 if (*nxt == ',' && nxt[1]) {
5794 str = ++nxt;
5795 h1 = (u32)simple_strtoul(str, &nxt, 0);
5796 if (nxt == str)
5797 while (*nxt && *nxt++ != ' ') /* skip */
5798 ;
5799 else
5800 seth1 = 1;
5801 }
f931551b
RC		 5802 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5803 ++pidx) {
a77fcf89
RC		 5804 struct qib_pportdata *ppd = &dd->pport[pidx];
5805
5806 if (ppd->port != port || !ppd->link_speed_supported)
f931551b 5807 continue;
a77fcf89 5808 ppd->cpspec->no_eep = val;
f931551b 5809 /* now change the IBC and serdes, overriding generic */
a77fcf89 5810 init_txdds_table(ppd, 1);
f931551b
RC		 5811 any++;
5812 }
5813 if (*nxt == '\n')
5814 break; /* done */
5815 }
5816 if (change && !any) {
5817 /* no specific setting, use the default.
5818 * Change the IBC and serdes, but since it's
5819 * general, don't override specific settings.
5820 */
a77fcf89
RC		 5821 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5822 if (dd->pport[pidx].link_speed_supported)
5823 init_txdds_table(&dd->pport[pidx], 0);
f931551b
RC		 5824 }
5825}
5826
a77fcf89
RC		 5827/* handle the txselect parameter changing */
5828static int setup_txselect(const char *str, struct kernel_param *kp)
f931551b
RC		 5829{
5830 struct qib_devdata *dd;
5831 unsigned long val;
5832 char *n;
5833 if (strlen(str) >= MAX_ATTEN_LEN) {
a77fcf89 5834 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
f931551b
RC		 5835 "too long\n");
5836 return -ENOSPC;
5837 }
5838 val = simple_strtoul(str, &n, 0);
a77fcf89 5839 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
f931551b 5840 printk(KERN_INFO QIB_DRV_NAME
a77fcf89
RC		 5841 "txselect_values must start with a number < %d\n",
5842 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
f931551b
RC		 5843 return -EINVAL;
5844 }
a77fcf89 5845 strcpy(txselect_list, str);
f931551b
RC		 5846
5847 list_for_each_entry(dd, &qib_dev_list, list)
a77fcf89
RC		 5848 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5849 set_no_qsfp_atten(dd, 1);
f931551b
RC		 5850 return 0;
5851}
5852
5853/*
5854 * Write the final few registers that depend on some of the
5855 * init setup. Done late in init, just before bringing up
5856 * the serdes.
5857 */
5858static int qib_late_7322_initreg(struct qib_devdata *dd)
5859{
5860 int ret = 0, n;
5861 u64 val;
5862
5863 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5864 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5865 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5866 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5867 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5868 if (val != dd->pioavailregs_phys) {
5869 qib_dev_err(dd, "Catastrophic software error, "
5870 "SendPIOAvailAddr written as %lx, "
5871 "read back as %llx\n",
5872 (unsigned long) dd->pioavailregs_phys,
5873 (unsigned long long) val);
5874 ret = -EINVAL;
5875 }
5876
5877 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5878 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5879 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5880 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5881
5882 qib_register_observer(dd, &sendctrl_0_observer);
5883 qib_register_observer(dd, &sendctrl_1_observer);
5884
5885 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5886 qib_write_kreg(dd, kr_control, dd->control);
5887 /*
5888 * Set SendDmaFetchPriority and init Tx params, including
5889 * QSFP handler on boards that have QSFP.
5890 * First set our default attenuation entry for cables that
5891 * don't have valid attenuation.
5892 */
5893 set_no_qsfp_atten(dd, 0);
5894 for (n = 0; n < dd->num_pports; ++n) {
5895 struct qib_pportdata *ppd = dd->pport + n;
5896
5897 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5898 sdma_fetch_prio & 0xf);
5899 /* Initialize qsfp if present on board. */
5900 if (dd->flags & QIB_HAS_QSFP)
5901 qib_init_7322_qsfp(ppd);
5902 }
5903 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5904 qib_write_kreg(dd, kr_control, dd->control);
5905
5906 return ret;
5907}
5908
5909/* per IB port errors. */
5910#define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5911 MASK_ACROSS(8, 15))
5912#define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5913#define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5914 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5915 MASK_ACROSS(0, 11))
5916
5917/*
5918 * Write the initialization per-port registers that need to be done at
5919 * driver load and after reset completes (i.e., that aren't done as part
5920 * of other init procedures called from qib_init.c).
5921 * Some of these should be redundant on reset, but play safe.
5922 */
5923static void write_7322_init_portregs(struct qib_pportdata *ppd)
5924{
5925 u64 val;
5926 int i;
5927
5928 if (!ppd->link_speed_supported) {
5929 /* no buffer credits for this port */
5930 for (i = 1; i < 8; i++)
5931 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5932 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5933 qib_write_kreg(ppd->dd, kr_scratch, 0);
5934 return;
5935 }
5936
5937 /*
5938 * Set the number of supported virtual lanes in IBC,
5939 * for flow control packet handling on unsupported VLs
5940 */
5941 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5942 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5943 val |= (u64)(ppd->vls_supported - 1) <<
5944 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5945 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5946
5947 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5948
5949 /* enable tx header checking */
5950 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5951 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5952 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5953
5954 qib_write_kreg_port(ppd, krp_ncmodectrl,
5955 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5956
5957 /*
5958 * Unconditionally clear the bufmask bits. If SDMA is
5959 * enabled, we'll set them appropriately later.
5960 */
5961 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5962 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5963 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5964 if (ppd->dd->cspec->r1)
5965 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5966}
5967
5968/*
5969 * Write the initialization per-device registers that need to be done at
5970 * driver load and after reset completes (i.e., that aren't done as part
5971 * of other init procedures called from qib_init.c). Also write per-port
5972 * registers that are affected by overall device config, such as QP mapping
5973 * Some of these should be redundant on reset, but play safe.
5974 */
5975static void write_7322_initregs(struct qib_devdata *dd)
5976{
5977 struct qib_pportdata *ppd;
5978 int i, pidx;
5979 u64 val;
5980
5981 /* Set Multicast QPs received by port 2 to map to context one. */
5982 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
5983
5984 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5985 unsigned n, regno;
5986 unsigned long flags;
5987
5988 if (!dd->qpn_mask || !dd->pport[pidx].link_speed_supported)
5989 continue;
5990
5991 ppd = &dd->pport[pidx];
5992
5993 /* be paranoid against later code motion, etc. */
5994 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5995 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5996 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5997
5998 /* Initialize QP to context mapping */
5999 regno = krp_rcvqpmaptable;
6000 val = 0;
6001 if (dd->num_pports > 1)
6002 n = dd->first_user_ctxt / dd->num_pports;
6003 else
6004 n = dd->first_user_ctxt - 1;
6005 for (i = 0; i < 32; ) {
6006 unsigned ctxt;
6007
6008 if (dd->num_pports > 1)
6009 ctxt = (i % n) * dd->num_pports + pidx;
6010 else if (i % n)
6011 ctxt = (i % n) + 1;
6012 else
6013 ctxt = ppd->hw_pidx;
6014 val |= ctxt << (5 * (i % 6));
6015 i++;
6016 if (i % 6 == 0) {
6017 qib_write_kreg_port(ppd, regno, val);
6018 val = 0;
6019 regno++;
6020 }
6021 }
6022 qib_write_kreg_port(ppd, regno, val);
6023 }
6024
6025 /*
6026 * Setup up interrupt mitigation for kernel contexts, but
6027 * not user contexts (user contexts use interrupts when
6028 * stalled waiting for any packet, so want those interrupts
6029 * right away).
6030 */
6031 for (i = 0; i < dd->first_user_ctxt; i++) {
6032 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6033 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
6034 }
6035
6036 /*
6037 * Initialize as (disabled) rcvflow tables. Application code
6038 * will setup each flow as it uses the flow.
6039 * Doesn't clear any of the error bits that might be set.
6040 */
6041 val = TIDFLOW_ERRBITS; /* these are W1C */
6042 for (i = 0; i < dd->ctxtcnt; i++) {
6043 int flow;
6044 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
6045 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
6046 }
6047
6048 /*
6049 * dual cards init to dual port recovery, single port cards to
6050 * the one port. Dual port cards may later adjust to 1 port,
6051 * and then back to dual port if both ports are connected
6052 * */
6053 if (dd->num_pports)
6054 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
6055}
6056
6057static int qib_init_7322_variables(struct qib_devdata *dd)
6058{
6059 struct qib_pportdata *ppd;
6060 unsigned features, pidx, sbufcnt;
6061 int ret, mtu;
6062 u32 sbufs, updthresh;
6063
6064 /* pport structs are contiguous, allocated after devdata */
6065 ppd = (struct qib_pportdata *)(dd + 1);
6066 dd->pport = ppd;
6067 ppd[0].dd = dd;
6068 ppd[1].dd = dd;
6069
6070 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6071
6072 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6073 ppd[1].cpspec = &ppd[0].cpspec[1];
6074 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
6075 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
6076
6077 spin_lock_init(&dd->cspec->rcvmod_lock);
6078 spin_lock_init(&dd->cspec->gpio_lock);
6079
6080 /* we haven't yet set QIB_PRESENT, so use read directly */
6081 dd->revision = readq(&dd->kregbase[kr_revision]);
6082
6083 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
6084 qib_dev_err(dd, "Revision register read failure, "
6085 "giving up initialization\n");
6086 ret = -ENODEV;
6087 goto bail;
6088 }
6089 dd->flags |= QIB_PRESENT; /* now register routines work */
6090
6091 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6092 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6093 dd->cspec->r1 = dd->minrev == 1;
6094
6095 get_7322_chip_params(dd);
6096 features = qib_7322_boardname(dd);
6097
6098 /* now that piobcnt2k and 4k set, we can allocate these */
6099 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6100 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6101 sbufcnt /= BITS_PER_LONG;
6102 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6103 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6104 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6105 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6106 dd->cspec->sendibchk = kmalloc(sbufcnt *
6107 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6108 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6109 !dd->cspec->sendibchk) {
6110 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6111 ret = -ENOMEM;
6112 goto bail;
6113 }
6114
6115 ppd = dd->pport;
6116
6117 /*
6118 * GPIO bits for TWSI data and clock,
6119 * used for serial EEPROM.
6120 */
6121 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6122 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6123 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6124
6125 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6126 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6127 QIB_HAS_THRESH_UPDATE |
6128 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6129 dd->flags |= qib_special_trigger ?
6130 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6131
6132 /*
6133 * Setup initial values. These may change when PAT is enabled, but
6134 * we need these to do initial chip register accesses.
6135 */
6136 qib_7322_set_baseaddrs(dd);
6137
6138 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6139 if (mtu == -1)
6140 mtu = QIB_DEFAULT_MTU;
6141
6142 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6143 /* all hwerrors become interrupts, unless special purposed */
6144 dd->cspec->hwerrmask = ~0ULL;
6145 /* link_recovery setup causes these errors, so ignore them,
6146 * other than clearing them when they occur */
6147 dd->cspec->hwerrmask &=
6148 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6149 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6150 HWE_MASK(LATriggered));
6151
6152 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6153 struct qib_chippport_specific *cp = ppd->cpspec;
6154 ppd->link_speed_supported = features & PORT_SPD_CAP;
6155 features >>= PORT_SPD_CAP_SHIFT;
6156 if (!ppd->link_speed_supported) {
6157 /* single port mode (7340, or configured) */
6158 dd->skip_kctxt_mask |= 1 << pidx;
6159 if (pidx == 0) {
6160 /* Make sure port is disabled. */
6161 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6162 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6163 ppd[0] = ppd[1];
6164 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6165 IBSerdesPClkNotDetectMask_0)
6166 | SYM_MASK(HwErrMask,
6167 SDmaMemReadErrMask_0));
6168 dd->cspec->int_enable_mask &= ~(
6169 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6170 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6171 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6172 SYM_MASK(IntMask, SDmaIntMask_0) |
6173 SYM_MASK(IntMask, ErrIntMask_0) |
6174 SYM_MASK(IntMask, SendDoneIntMask_0));
6175 } else {
6176 /* Make sure port is disabled. */
6177 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6178 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6179 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6180 IBSerdesPClkNotDetectMask_1)
6181 | SYM_MASK(HwErrMask,
6182 SDmaMemReadErrMask_1));
6183 dd->cspec->int_enable_mask &= ~(
6184 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6185 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6186 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6187 SYM_MASK(IntMask, SDmaIntMask_1) |
6188 SYM_MASK(IntMask, ErrIntMask_1) |
6189 SYM_MASK(IntMask, SendDoneIntMask_1));
6190 }
6191 continue;
6192 }
6193
6194 dd->num_pports++;
6195 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6196
6197 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6198 ppd->link_width_enabled = IB_WIDTH_4X;
6199 ppd->link_speed_enabled = ppd->link_speed_supported;
6200 /*
6201 * Set the initial values to reasonable default, will be set
6202 * for real when link is up.
6203 */
6204 ppd->link_width_active = IB_WIDTH_4X;
6205 ppd->link_speed_active = QIB_IB_SDR;
6206 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6207 switch (qib_num_cfg_vls) {
6208 case 1:
6209 ppd->vls_supported = IB_VL_VL0;
6210 break;
6211 case 2:
6212 ppd->vls_supported = IB_VL_VL0_1;
6213 break;
6214 default:
6215 qib_devinfo(dd->pcidev,
6216 "Invalid num_vls %u, using 4 VLs\n",
6217 qib_num_cfg_vls);
6218 qib_num_cfg_vls = 4;
6219 /* fall through */
6220 case 4:
6221 ppd->vls_supported = IB_VL_VL0_3;
6222 break;
6223 case 8:
6224 if (mtu <= 2048)
6225 ppd->vls_supported = IB_VL_VL0_7;
6226 else {
6227 qib_devinfo(dd->pcidev,
6228 "Invalid num_vls %u for MTU %d "
6229 ", using 4 VLs\n",
6230 qib_num_cfg_vls, mtu);
6231 ppd->vls_supported = IB_VL_VL0_3;
6232 qib_num_cfg_vls = 4;
6233 }
6234 break;
6235 }
6236 ppd->vls_operational = ppd->vls_supported;
6237
6238 init_waitqueue_head(&cp->autoneg_wait);
6239 INIT_DELAYED_WORK(&cp->autoneg_work,
6240 autoneg_7322_work);
6241 if (ppd->dd->cspec->r1)
6242 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6243
6244 /*
6245 * For Mez and similar cards, no qsfp info, so do
6246 * the "cable info" setup here. Can be overridden
6247 * in adapter-specific routines.
6248 */
6249 if (!(ppd->dd->flags & QIB_HAS_QSFP)) {
f931551b
RC		 6250 if (!IS_QMH(ppd->dd) && !IS_QME(ppd->dd))
6251 qib_devinfo(ppd->dd->pcidev, "IB%u:%u: "
6252 "Unknown mezzanine card type\n",
a77fcf89
RC		 6253 dd->unit, ppd->port);
6254 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
f931551b 6255 /*
a77fcf89
RC		 6256 * Choose center value as default tx serdes setting
6257 * until changed through module parameter.
f931551b 6258 */
a77fcf89
RC		 6259 ppd->cpspec->no_eep = IS_QMH(dd) ?
6260 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
f931551b
RC		 6261 } else
6262 cp->h1_val = H1_FORCE_VAL;
6263
6264 /* Avoid writes to chip for mini_init */
6265 if (!qib_mini_init)
6266 write_7322_init_portregs(ppd);
6267
6268 init_timer(&cp->chase_timer);
6269 cp->chase_timer.function = reenable_chase;
6270 cp->chase_timer.data = (unsigned long)ppd;
6271
6272 ppd++;
6273 }
6274
6275 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
6276 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
a77fcf89 6277 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
f931551b
RC		 6278
6279 /* we always allocate at least 2048 bytes for eager buffers */
6280 dd->rcvegrbufsize = max(mtu, 2048);
6281
6282 qib_7322_tidtemplate(dd);
6283
6284 /*
6285 * We can request a receive interrupt for 1 or
6286 * more packets from current offset.
6287 */
6288 dd->rhdrhead_intr_off =
6289 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6290
6291 /* setup the stats timer; the add_timer is done at end of init */
6292 init_timer(&dd->stats_timer);
6293 dd->stats_timer.function = qib_get_7322_faststats;
6294 dd->stats_timer.data = (unsigned long) dd;
6295
6296 dd->ureg_align = 0x10000; /* 64KB alignment */
6297
6298 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6299
6300 qib_7322_config_ctxts(dd);
6301 qib_set_ctxtcnt(dd);
6302
6303 if (qib_wc_pat) {
6304 ret = init_chip_wc_pat(dd, NUM_VL15_BUFS * dd->align4k);
6305 if (ret)
6306 goto bail;
6307 }
6308 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6309
6310 ret = 0;
6311 if (qib_mini_init)
6312 goto bail;
6313 if (!dd->num_pports) {
6314 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6315 goto bail; /* no error, so can still figure out why err */
6316 }
6317
6318 write_7322_initregs(dd);
6319 ret = qib_create_ctxts(dd);
6320 init_7322_cntrnames(dd);
6321
6322 updthresh = 8U; /* update threshold */
6323
6324 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6325 * reserve the update threshold amount for other kernel use, such
6326 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6327 * unless we aren't enabling SDMA, in which case we want to use
6328 * all the 4k bufs for the kernel.
6329 * if this was less than the update threshold, we could wait
6330 * a long time for an update. Coded this way because we
6331 * sometimes change the update threshold for various reasons,
6332 * and we want this to remain robust.
6333 */
6334 if (dd->flags & QIB_HAS_SEND_DMA) {
6335 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6336 sbufs = updthresh > 3 ? updthresh : 3;
6337 } else {
6338 dd->cspec->sdmabufcnt = 0;
6339 sbufs = dd->piobcnt4k;
6340 }
6341 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6342 dd->cspec->sdmabufcnt;
6343 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6344 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6345 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6346 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6347
6348 /*
6349 * If we have 16 user contexts, we will have 7 sbufs
6350 * per context, so reduce the update threshold to match. We
6351 * want to update before we actually run out, at low pbufs/ctxt
6352 * so give ourselves some margin.
6353 */
6354 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6355 updthresh = dd->pbufsctxt - 2;
6356 dd->cspec->updthresh_dflt = updthresh;
6357 dd->cspec->updthresh = updthresh;
6358
6359 /* before full enable, no interrupts, no locking needed */
6360 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6361 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6362 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6363
6364 dd->psxmitwait_supported = 1;
6365 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6366bail:
6367 if (!dd->ctxtcnt)
6368 dd->ctxtcnt = 1; /* for other initialization code */
6369
6370 return ret;
6371}
6372
6373static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6374 u32 *pbufnum)
6375{
6376 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6377 struct qib_devdata *dd = ppd->dd;
6378
6379 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6380 if (pbc & PBC_7322_VL15_SEND) {
6381 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6382 last = first;
6383 } else {
6384 if ((plen + 1) > dd->piosize2kmax_dwords)
6385 first = dd->piobcnt2k;
6386 else
6387 first = 0;
6388 last = dd->cspec->lastbuf_for_pio;
6389 }
6390 return qib_getsendbuf_range(dd, pbufnum, first, last);
6391}
6392
6393static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6394 u32 start)
6395{
6396 qib_write_kreg_port(ppd, krp_psinterval, intv);
6397 qib_write_kreg_port(ppd, krp_psstart, start);
6398}
6399
6400/*
6401 * Must be called with sdma_lock held, or before init finished.
6402 */
6403static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6404{
6405 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6406}
6407
6408static struct sdma_set_state_action sdma_7322_action_table[] = {
6409 [qib_sdma_state_s00_hw_down] = {
6410 .go_s99_running_tofalse = 1,
6411 .op_enable = 0,
6412 .op_intenable = 0,
6413 .op_halt = 0,
6414 .op_drain = 0,
6415 },
6416 [qib_sdma_state_s10_hw_start_up_wait] = {
6417 .op_enable = 0,
6418 .op_intenable = 1,
6419 .op_halt = 1,
6420 .op_drain = 0,
6421 },
6422 [qib_sdma_state_s20_idle] = {
6423 .op_enable = 1,
6424 .op_intenable = 1,
6425 .op_halt = 1,
6426 .op_drain = 0,
6427 },
6428 [qib_sdma_state_s30_sw_clean_up_wait] = {
6429 .op_enable = 0,
6430 .op_intenable = 1,
6431 .op_halt = 1,
6432 .op_drain = 0,
6433 },
6434 [qib_sdma_state_s40_hw_clean_up_wait] = {
6435 .op_enable = 1,
6436 .op_intenable = 1,
6437 .op_halt = 1,
6438 .op_drain = 0,
6439 },
6440 [qib_sdma_state_s50_hw_halt_wait] = {
6441 .op_enable = 1,
6442 .op_intenable = 1,
6443 .op_halt = 1,
6444 .op_drain = 1,
6445 },
6446 [qib_sdma_state_s99_running] = {
6447 .op_enable = 1,
6448 .op_intenable = 1,
6449 .op_halt = 0,
6450 .op_drain = 0,
6451 .go_s99_running_totrue = 1,
6452 },
6453};
6454
6455static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6456{
6457 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6458}
6459
6460static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6461{
6462 struct qib_devdata *dd = ppd->dd;
6463 unsigned lastbuf, erstbuf;
6464 u64 senddmabufmask[3] = { 0 };
6465 int n, ret = 0;
6466
6467 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6468 qib_sdma_7322_setlengen(ppd);
6469 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6470 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6471 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6472 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6473
6474 if (dd->num_pports)
6475 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6476 else
6477 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6478 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6479 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6480 dd->cspec->sdmabufcnt);
6481 lastbuf = erstbuf + n;
6482
6483 ppd->sdma_state.first_sendbuf = erstbuf;
6484 ppd->sdma_state.last_sendbuf = lastbuf;
6485 for (; erstbuf < lastbuf; ++erstbuf) {
6486 unsigned word = erstbuf / BITS_PER_LONG;
6487 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6488
6489 BUG_ON(word >= 3);
6490 senddmabufmask[word] |= 1ULL << bit;
6491 }
6492 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6493 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6494 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6495 return ret;
6496}
6497
6498/* sdma_lock must be held */
6499static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6500{
6501 struct qib_devdata *dd = ppd->dd;
6502 int sane;
6503 int use_dmahead;
6504 u16 swhead;
6505 u16 swtail;
6506 u16 cnt;
6507 u16 hwhead;
6508
6509 use_dmahead = __qib_sdma_running(ppd) &&
6510 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6511retry:
6512 hwhead = use_dmahead ?
6513 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6514 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6515
6516 swhead = ppd->sdma_descq_head;
6517 swtail = ppd->sdma_descq_tail;
6518 cnt = ppd->sdma_descq_cnt;
6519
6520 if (swhead < swtail)
6521 /* not wrapped */
6522 sane = (hwhead >= swhead) & (hwhead <= swtail);
6523 else if (swhead > swtail)
6524 /* wrapped around */
6525 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6526 (hwhead <= swtail);
6527 else
6528 /* empty */
6529 sane = (hwhead == swhead);
6530
6531 if (unlikely(!sane)) {
6532 if (use_dmahead) {
6533 /* try one more time, directly from the register */
6534 use_dmahead = 0;
6535 goto retry;
6536 }
6537 /* proceed as if no progress */
6538 hwhead = swhead;
6539 }
6540
6541 return hwhead;
6542}
6543
6544static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6545{
6546 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6547
6548 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6549 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6550 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6551 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6552}
6553
6554/*
6555 * Compute the amount of delay before sending the next packet if the
6556 * port's send rate differs from the static rate set for the QP.
6557 * The delay affects the next packet and the amount of the delay is
6558 * based on the length of the this packet.
6559 */
6560static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6561 u8 srate, u8 vl)
6562{
6563 u8 snd_mult = ppd->delay_mult;
6564 u8 rcv_mult = ib_rate_to_delay[srate];
6565 u32 ret;
6566
6567 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6568
6569 /* Indicate VL15, else set the VL in the control word */
6570 if (vl == 15)
6571 ret |= PBC_7322_VL15_SEND_CTRL;
6572 else
6573 ret |= vl << PBC_VL_NUM_LSB;
6574 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6575
6576 return ret;
6577}
6578
6579/*
6580 * Enable the per-port VL15 send buffers for use.
6581 * They follow the rest of the buffers, without a config parameter.
6582 * This was in initregs, but that is done before the shadow
6583 * is set up, and this has to be done after the shadow is
6584 * set up.
6585 */
6586static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6587{
6588 unsigned vl15bufs;
6589
6590 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6591 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6592 TXCHK_CHG_TYPE_KERN, NULL);
6593}
6594
6595static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6596{
6597 if (rcd->ctxt < NUM_IB_PORTS) {
6598 if (rcd->dd->num_pports > 1) {
6599 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6600 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6601 } else {
6602 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6603 rcd->rcvegr_tid_base = 0;
6604 }
6605 } else {
6606 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6607 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6608 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6609 }
6610}
6611
6612#define QTXSLEEPS 5000
6613static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6614 u32 len, u32 which, struct qib_ctxtdata *rcd)
6615{
6616 int i;
6617 const int last = start + len - 1;
6618 const int lastr = last / BITS_PER_LONG;
6619 u32 sleeps = 0;
6620 int wait = rcd != NULL;
6621 unsigned long flags;
6622
6623 while (wait) {
6624 unsigned long shadow;
6625 int cstart, previ = -1;
6626
6627 /*
6628 * when flipping from kernel to user, we can't change
6629 * the checking type if the buffer is allocated to the
6630 * driver. It's OK the other direction, because it's
6631 * from close, and we have just disarm'ed all the
6632 * buffers. All the kernel to kernel changes are also
6633 * OK.
6634 */
6635 for (cstart = start; cstart <= last; cstart++) {
6636 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6637 / BITS_PER_LONG;
6638 if (i != previ) {
6639 shadow = (unsigned long)
6640 le64_to_cpu(dd->pioavailregs_dma[i]);
6641 previ = i;
6642 }
6643 if (test_bit(((2 * cstart) +
6644 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6645 % BITS_PER_LONG, &shadow))
6646 break;
6647 }
6648
6649 if (cstart > last)
6650 break;
6651
6652 if (sleeps == QTXSLEEPS)
6653 break;
6654 /* make sure we see an updated copy next time around */
6655 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6656 sleeps++;
6657 msleep(1);
6658 }
6659
6660 switch (which) {
6661 case TXCHK_CHG_TYPE_DIS1:
6662 /*
6663 * disable checking on a range; used by diags; just
6664 * one buffer, but still written generically
6665 */
6666 for (i = start; i <= last; i++)
6667 clear_bit(i, dd->cspec->sendchkenable);
6668 break;
6669
6670 case TXCHK_CHG_TYPE_ENAB1:
6671 /*
6672 * (re)enable checking on a range; used by diags; just
6673 * one buffer, but still written generically; read
6674 * scratch to be sure buffer actually triggered, not
6675 * just flushed from processor.
6676 */
6677 qib_read_kreg32(dd, kr_scratch);
6678 for (i = start; i <= last; i++)
6679 set_bit(i, dd->cspec->sendchkenable);
6680 break;
6681
6682 case TXCHK_CHG_TYPE_KERN:
6683 /* usable by kernel */
6684 for (i = start; i <= last; i++) {
6685 set_bit(i, dd->cspec->sendibchk);
6686 clear_bit(i, dd->cspec->sendgrhchk);
6687 }
6688 spin_lock_irqsave(&dd->uctxt_lock, flags);
6689 /* see if we need to raise avail update threshold */
6690 for (i = dd->first_user_ctxt;
6691 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6692 && i < dd->cfgctxts; i++)
6693 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6694 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6695 < dd->cspec->updthresh_dflt)
6696 break;
6697 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6698 if (i == dd->cfgctxts) {
6699 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6700 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6701 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6702 dd->sendctrl |= (dd->cspec->updthresh &
6703 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6704 SYM_LSB(SendCtrl, AvailUpdThld);
6705 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6706 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6707 }
6708 break;
6709
6710 case TXCHK_CHG_TYPE_USER:
6711 /* for user process */
6712 for (i = start; i <= last; i++) {
6713 clear_bit(i, dd->cspec->sendibchk);
6714 set_bit(i, dd->cspec->sendgrhchk);
6715 }
6716 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6717 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6718 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6719 dd->cspec->updthresh = (rcd->piocnt /
6720 rcd->subctxt_cnt) - 1;
6721 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6722 dd->sendctrl |= (dd->cspec->updthresh &
6723 SYM_RMASK(SendCtrl, AvailUpdThld))
6724 << SYM_LSB(SendCtrl, AvailUpdThld);
6725 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6726 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6727 } else
6728 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6729 break;
6730
6731 default:
6732 break;
6733 }
6734
6735 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6736 qib_write_kreg(dd, kr_sendcheckmask + i,
6737 dd->cspec->sendchkenable[i]);
6738
6739 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6740 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6741 dd->cspec->sendgrhchk[i]);
6742 qib_write_kreg(dd, kr_sendibpktmask + i,
6743 dd->cspec->sendibchk[i]);
6744 }
6745
6746 /*
6747 * Be sure whatever we did was seen by the chip and acted upon,
6748 * before we return. Mostly important for which >= 2.
6749 */
6750 qib_read_kreg32(dd, kr_scratch);
6751}
6752
6753
6754/* useful for trigger analyzers, etc. */
6755static void writescratch(struct qib_devdata *dd, u32 val)
6756{
6757 qib_write_kreg(dd, kr_scratch, val);
6758}
6759
6760/* Dummy for now, use chip regs soon */
6761static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6762{
6763 return -ENXIO;
6764}
6765
6766/**
6767 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6768 * @dev: the pci_dev for qlogic_ib device
6769 * @ent: pci_device_id struct for this dev
6770 *
6771 * Also allocates, inits, and returns the devdata struct for this
6772 * device instance
6773 *
6774 * This is global, and is called directly at init to set up the
6775 * chip-specific function pointers for later use.
6776 */
6777struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6778 const struct pci_device_id *ent)
6779{
6780 struct qib_devdata *dd;
6781 int ret, i;
6782 u32 tabsize, actual_cnt = 0;
6783
6784 dd = qib_alloc_devdata(pdev,
6785 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6786 sizeof(struct qib_chip_specific) +
6787 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6788 if (IS_ERR(dd))
6789 goto bail;
6790
6791 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6792 dd->f_cleanup = qib_setup_7322_cleanup;
6793 dd->f_clear_tids = qib_7322_clear_tids;
6794 dd->f_free_irq = qib_7322_free_irq;
6795 dd->f_get_base_info = qib_7322_get_base_info;
6796 dd->f_get_msgheader = qib_7322_get_msgheader;
6797 dd->f_getsendbuf = qib_7322_getsendbuf;
6798 dd->f_gpio_mod = gpio_7322_mod;
6799 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6800 dd->f_hdrqempty = qib_7322_hdrqempty;
6801 dd->f_ib_updown = qib_7322_ib_updown;
6802 dd->f_init_ctxt = qib_7322_init_ctxt;
6803 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6804 dd->f_intr_fallback = qib_7322_intr_fallback;
6805 dd->f_late_initreg = qib_late_7322_initreg;
6806 dd->f_setpbc_control = qib_7322_setpbc_control;
6807 dd->f_portcntr = qib_portcntr_7322;
6808 dd->f_put_tid = qib_7322_put_tid;
6809 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6810 dd->f_rcvctrl = rcvctrl_7322_mod;
6811 dd->f_read_cntrs = qib_read_7322cntrs;
6812 dd->f_read_portcntrs = qib_read_7322portcntrs;
6813 dd->f_reset = qib_do_7322_reset;
6814 dd->f_init_sdma_regs = init_sdma_7322_regs;
6815 dd->f_sdma_busy = qib_sdma_7322_busy;
6816 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6817 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6818 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6819 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6820 dd->f_sendctrl = sendctrl_7322_mod;
6821 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6822 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6823 dd->f_iblink_state = qib_7322_iblink_state;
6824 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6825 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6826 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6827 dd->f_set_ib_loopback = qib_7322_set_loopback;
6828 dd->f_get_ib_table = qib_7322_get_ib_table;
6829 dd->f_set_ib_table = qib_7322_set_ib_table;
6830 dd->f_set_intr_state = qib_7322_set_intr_state;
6831 dd->f_setextled = qib_setup_7322_setextled;
6832 dd->f_txchk_change = qib_7322_txchk_change;
6833 dd->f_update_usrhead = qib_update_7322_usrhead;
6834 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6835 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6836 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6837 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6838 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6839 dd->f_writescratch = writescratch;
6840 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6841 /*
6842 * Do remaining PCIe setup and save PCIe values in dd.
6843 * Any error printing is already done by the init code.
6844 * On return, we have the chip mapped, but chip registers
6845 * are not set up until start of qib_init_7322_variables.
6846 */
6847 ret = qib_pcie_ddinit(dd, pdev, ent);
6848 if (ret < 0)
6849 goto bail_free;
6850
6851 /* initialize chip-specific variables */
6852 ret = qib_init_7322_variables(dd);
6853 if (ret)
6854 goto bail_cleanup;
6855
6856 if (qib_mini_init || !dd->num_pports)
6857 goto bail;
6858
6859 /*
6860 * Determine number of vectors we want; depends on port count
6861 * and number of configured kernel receive queues actually used.
6862 * Should also depend on whether sdma is enabled or not, but
6863 * that's such a rare testing case it's not worth worrying about.
6864 */
6865 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6866 for (i = 0; i < tabsize; i++)
6867 if ((i < ARRAY_SIZE(irq_table) &&
6868 irq_table[i].port <= dd->num_pports) ||
6869 (i >= ARRAY_SIZE(irq_table) &&
6870 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6871 actual_cnt++;
6872 tabsize = actual_cnt;
6873 dd->cspec->msix_entries = kmalloc(tabsize *
6874 sizeof(struct msix_entry), GFP_KERNEL);
6875 dd->cspec->msix_arg = kmalloc(tabsize *
6876 sizeof(void *), GFP_KERNEL);
6877 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6878 qib_dev_err(dd, "No memory for MSIx table\n");
6879 tabsize = 0;
6880 }
6881 for (i = 0; i < tabsize; i++)
6882 dd->cspec->msix_entries[i].entry = i;
6883
6884 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6885 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6886 "continuing anyway\n");
6887 /* may be less than we wanted, if not enough available */
6888 dd->cspec->num_msix_entries = tabsize;
6889
6890 /* setup interrupt handler */
6891 qib_setup_7322_interrupt(dd, 1);
6892
6893 /* clear diagctrl register, in case diags were running and crashed */
6894 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6895
6896#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
6897 ret = dca_add_requester(&pdev->dev);
6898 if (!ret) {
6899 dd->flags |= QIB_DCA_ENABLED;
6900 qib_setup_dca(dd);
6901 }
6902#endif
6903 goto bail;
6904
6905bail_cleanup:
6906 qib_pcie_ddcleanup(dd);
6907bail_free:
6908 qib_free_devdata(dd);
6909 dd = ERR_PTR(ret);
6910bail:
6911 return dd;
6912}
6913
6914/*
6915 * Set the table entry at the specified index from the table specifed.
6916 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6917 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6918 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6919 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6920 */
6921#define DDS_ENT_AMP_LSB 14
6922#define DDS_ENT_MAIN_LSB 9
6923#define DDS_ENT_POST_LSB 5
6924#define DDS_ENT_PRE_XTRA_LSB 3
6925#define DDS_ENT_PRE_LSB 0
6926
6927/*
6928 * Set one entry in the TxDDS table for spec'd port
6929 * ridx picks one of the entries, while tp points
6930 * to the appropriate table entry.
6931 */
6932static void set_txdds(struct qib_pportdata *ppd, int ridx,
6933 const struct txdds_ent *tp)
6934{
6935 struct qib_devdata *dd = ppd->dd;
6936 u32 pack_ent;
6937 int regidx;
6938
6939 /* Get correct offset in chip-space, and in source table */
6940 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6941 /*
6942 * We do not use qib_write_kreg_port() because it was intended
6943 * only for registers in the lower "port specific" pages.
6944 * So do index calculation by hand.
6945 */
6946 if (ppd->hw_pidx)
6947 regidx += (dd->palign / sizeof(u64));
6948
6949 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6950 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6951 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6952 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6953 qib_write_kreg(dd, regidx, pack_ent);
6954 /* Prevent back-to-back writes by hitting scratch */
6955 qib_write_kreg(ppd->dd, kr_scratch, 0);
6956}
6957
6958static const struct vendor_txdds_ent vendor_txdds[] = {
6959 { /* Amphenol 1m 30awg NoEq */
6960 { 0x41, 0x50, 0x48 }, "584470002 ",
6961 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6962 },
6963 { /* Amphenol 3m 28awg NoEq */
6964 { 0x41, 0x50, 0x48 }, "584470004 ",
6965 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6966 },
6967 { /* Finisar 3m OM2 Optical */
6968 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6969 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6970 },
6971 { /* Finisar 30m OM2 Optical */
6972 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6973 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6974 },
6975 { /* Finisar Default OM2 Optical */
6976 { 0x00, 0x90, 0x65 }, NULL,
6977 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6978 },
6979 { /* Gore 1m 30awg NoEq */
6980 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6981 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6982 },
6983 { /* Gore 2m 30awg NoEq */
6984 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6985 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6986 },
6987 { /* Gore 1m 28awg NoEq */
6988 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6989 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6990 },
6991 { /* Gore 3m 28awg NoEq */
6992 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6993 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6994 },
6995 { /* Gore 5m 24awg Eq */
6996 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6997 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6998 },
6999 { /* Gore 7m 24awg Eq */
7000 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
7001 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
7002 },
7003 { /* Gore 5m 26awg Eq */
7004 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
7005 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
7006 },
7007 { /* Gore 7m 26awg Eq */
7008 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
7009 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
7010 },
7011 { /* Intersil 12m 24awg Active */
7012 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
7013 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
7014 },
7015 { /* Intersil 10m 28awg Active */
7016 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
7017 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
7018 },
7019 { /* Intersil 7m 30awg Active */
7020 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
7021 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
7022 },
7023 { /* Intersil 5m 32awg Active */
7024 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
7025 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
7026 },
7027 { /* Intersil Default Active */
7028 { 0x00, 0x30, 0xB4 }, NULL,
7029 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
7030 },
7031 { /* Luxtera 20m Active Optical */
7032 { 0x00, 0x25, 0x63 }, NULL,
7033 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
7034 },
7035 { /* Molex 1M Cu loopback */
7036 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7037 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
7038 },
7039 { /* Molex 2m 28awg NoEq */
7040 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7041 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
7042 },
7043};
7044
7045static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
7046 /* amp, pre, main, post */
7047 { 2, 2, 15, 6 }, /* Loopback */
7048 { 0, 0, 0, 1 }, /* 2 dB */
7049 { 0, 0, 0, 2 }, /* 3 dB */
7050 { 0, 0, 0, 3 }, /* 4 dB */
7051 { 0, 0, 0, 4 }, /* 5 dB */
7052 { 0, 0, 0, 5 }, /* 6 dB */
7053 { 0, 0, 0, 6 }, /* 7 dB */
7054 { 0, 0, 0, 7 }, /* 8 dB */
7055 { 0, 0, 0, 8 }, /* 9 dB */
7056 { 0, 0, 0, 9 }, /* 10 dB */
7057 { 0, 0, 0, 10 }, /* 11 dB */
7058 { 0, 0, 0, 11 }, /* 12 dB */
7059 { 0, 0, 0, 12 }, /* 13 dB */
7060 { 0, 0, 0, 13 }, /* 14 dB */
7061 { 0, 0, 0, 14 }, /* 15 dB */
7062 { 0, 0, 0, 15 }, /* 16 dB */
7063};
7064
7065static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7066 /* amp, pre, main, post */
7067 { 2, 2, 15, 6 }, /* Loopback */
7068 { 0, 0, 0, 8 }, /* 2 dB */
7069 { 0, 0, 0, 8 }, /* 3 dB */
7070 { 0, 0, 0, 9 }, /* 4 dB */
7071 { 0, 0, 0, 9 }, /* 5 dB */
7072 { 0, 0, 0, 10 }, /* 6 dB */
7073 { 0, 0, 0, 10 }, /* 7 dB */
7074 { 0, 0, 0, 11 }, /* 8 dB */
7075 { 0, 0, 0, 11 }, /* 9 dB */
7076 { 0, 0, 0, 12 }, /* 10 dB */
7077 { 0, 0, 0, 12 }, /* 11 dB */
7078 { 0, 0, 0, 13 }, /* 12 dB */
7079 { 0, 0, 0, 13 }, /* 13 dB */
7080 { 0, 0, 0, 14 }, /* 14 dB */
7081 { 0, 0, 0, 14 }, /* 15 dB */
7082 { 0, 0, 0, 15 }, /* 16 dB */
7083};
7084
7085static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7086 /* amp, pre, main, post */
7087 { 2, 2, 15, 6 }, /* Loopback */
a77fcf89
RC		 7088 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7089 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
f931551b
RC		 7090 { 0, 1, 0, 11 }, /* 4 dB */
7091 { 0, 1, 0, 13 }, /* 5 dB */
7092 { 0, 1, 0, 15 }, /* 6 dB */
7093 { 0, 1, 3, 15 }, /* 7 dB */
7094 { 0, 1, 7, 15 }, /* 8 dB */
7095 { 0, 1, 7, 15 }, /* 9 dB */
7096 { 0, 1, 8, 15 }, /* 10 dB */
7097 { 0, 1, 9, 15 }, /* 11 dB */
7098 { 0, 1, 10, 15 }, /* 12 dB */
7099 { 0, 2, 6, 15 }, /* 13 dB */
7100 { 0, 2, 7, 15 }, /* 14 dB */
7101 { 0, 2, 8, 15 }, /* 15 dB */
7102 { 0, 2, 9, 15 }, /* 16 dB */
7103};
7104
a77fcf89
RC		 7105/*
7106 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7107 * These are mostly used for mez cards going through connectors
7108 * and backplane traces, but can be used to add other "unusual"
7109 * table values as well.
7110 */
7111static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7112 /* amp, pre, main, post */
7113 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7114 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7115 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7116 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7117 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7118 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7119 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7120 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7121 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7122 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7123 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7124};
7125
7126static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7127 /* amp, pre, main, post */
7128 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7129 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7130 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7131 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7132 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7133 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7134 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7135 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7136 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7137 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7138 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7139};
7140
7141static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7142 /* amp, pre, main, post */
7143 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7144 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7145 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7146 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7147 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7148 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7149 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7150 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7151 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7152 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7153 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7154};
7155
f931551b
RC		 7156static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7157 unsigned atten)
7158{
7159 /*
7160 * The attenuation table starts at 2dB for entry 1,
7161 * with entry 0 being the loopback entry.
7162 */
7163 if (atten <= 2)
7164 atten = 1;
7165 else if (atten > TXDDS_TABLE_SZ)
7166 atten = TXDDS_TABLE_SZ - 1;
7167 else
7168 atten--;
7169 return txdds + atten;
7170}
7171
7172/*
a77fcf89 7173 * if override is set, the module parameter txselect has a value
f931551b
RC		 7174 * for this specific port, so use it, rather than our normal mechanism.
7175 */
7176static void find_best_ent(struct qib_pportdata *ppd,
7177 const struct txdds_ent **sdr_dds,
7178 const struct txdds_ent **ddr_dds,
7179 const struct txdds_ent **qdr_dds, int override)
7180{
7181 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7182 int idx;
7183
7184 /* Search table of known cables */
7185 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7186 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7187
7188 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7189 (!v->partnum ||
7190 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7191 *sdr_dds = &v->sdr;
7192 *ddr_dds = &v->ddr;
7193 *qdr_dds = &v->qdr;
7194 return;
7195 }
7196 }
7197
7198 /* Lookup serdes setting by cable type and attenuation */
7199 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7200 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7201 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7202 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7203 return;
7204 }
7205
7206 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7207 qd->atten[1])) {
7208 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7209 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7210 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7211 return;
a77fcf89 7212 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
f931551b
RC		 7213 /*
7214 * If we have no (or incomplete) data from the cable
a77fcf89
RC		 7215 * EEPROM, or no QSFP, or override is set, use the
7216 * module parameter value to index into the attentuation
7217 * table.
f931551b 7218 */
a77fcf89
RC		 7219 idx = ppd->cpspec->no_eep;
7220 *sdr_dds = &txdds_sdr[idx];
7221 *ddr_dds = &txdds_ddr[idx];
7222 *qdr_dds = &txdds_qdr[idx];
7223 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7224 /* similar to above, but index into the "extra" table. */
7225 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7226 *sdr_dds = &txdds_extra_sdr[idx];
7227 *ddr_dds = &txdds_extra_ddr[idx];
7228 *qdr_dds = &txdds_extra_qdr[idx];
7229 } else {
7230 /* this shouldn't happen, it's range checked */
7231 *sdr_dds = txdds_sdr + qib_long_atten;
7232 *ddr_dds = txdds_ddr + qib_long_atten;
7233 *qdr_dds = txdds_qdr + qib_long_atten;
f931551b
RC		 7234 }
7235}
7236
7237static void init_txdds_table(struct qib_pportdata *ppd, int override)
7238{
7239 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7240 struct txdds_ent *dds;
7241 int idx;
7242 int single_ent = 0;
7243
a77fcf89
RC		 7244 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7245
7246 /* for mez cards or override, use the selected value for all entries */
7247 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
f931551b 7248 single_ent = 1;
f931551b
RC		 7249
7250 /* Fill in the first entry with the best entry found. */
7251 set_txdds(ppd, 0, sdr_dds);
7252 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7253 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
a77fcf89
RC		 7254 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7255 QIBL_LINKACTIVE)) {
7256 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7257 QIB_IB_QDR ? qdr_dds :
7258 (ppd->link_speed_active ==
7259 QIB_IB_DDR ? ddr_dds : sdr_dds));
7260 write_tx_serdes_param(ppd, dds);
7261 }
f931551b
RC		 7262
7263 /* Fill in the remaining entries with the default table values. */
7264 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7265 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7266 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7267 single_ent ? ddr_dds : txdds_ddr + idx);
7268 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7269 single_ent ? qdr_dds : txdds_qdr + idx);
7270 }
7271}
7272
7273#define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7274#define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7275#define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7276#define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7277#define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7278#define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7279#define AHB_TRANS_TRIES 10
7280
7281/*
7282 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7283 * 5=subsystem which is why most calls have "chan + chan >> 1"
7284 * for the channel argument.
7285 */
7286static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7287 u32 data, u32 mask)
7288{
7289 u32 rd_data, wr_data, sz_mask;
7290 u64 trans, acc, prev_acc;
7291 u32 ret = 0xBAD0BAD;
7292 int tries;
7293
7294 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7295 /* From this point on, make sure we return access */
7296 acc = (quad << 1) | 1;
7297 qib_write_kreg(dd, KR_AHB_ACC, acc);
7298
7299 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7300 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7301 if (trans & AHB_TRANS_RDY)
7302 break;
7303 }
7304 if (tries >= AHB_TRANS_TRIES) {
7305 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7306 goto bail;
7307 }
7308
7309 /* If mask is not all 1s, we need to read, but different SerDes
7310 * entities have different sizes
7311 */
7312 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7313 wr_data = data & mask & sz_mask;
7314 if ((~mask & sz_mask) != 0) {
7315 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7316 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7317
7318 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7319 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7320 if (trans & AHB_TRANS_RDY)
7321 break;
7322 }
7323 if (tries >= AHB_TRANS_TRIES) {
7324 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7325 AHB_TRANS_TRIES);
7326 goto bail;
7327 }
7328 /* Re-read in case host split reads and read data first */
7329 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7330 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7331 wr_data |= (rd_data & ~mask & sz_mask);
7332 }
7333
7334 /* If mask is not zero, we need to write. */
7335 if (mask & sz_mask) {
7336 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7337 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7338 trans |= AHB_WR;
7339 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7340
7341 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7342 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7343 if (trans & AHB_TRANS_RDY)
7344 break;
7345 }
7346 if (tries >= AHB_TRANS_TRIES) {
7347 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7348 AHB_TRANS_TRIES);
7349 goto bail;
7350 }
7351 }
7352 ret = wr_data;
7353bail:
7354 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7355 return ret;
7356}
7357
7358static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7359 unsigned mask)
7360{
7361 struct qib_devdata *dd = ppd->dd;
7362 int chan;
7363 u32 rbc;
7364
7365 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7366 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7367 data, mask);
7368 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7369 addr, 0, 0);
7370 }
7371}
7372
7373static int serdes_7322_init(struct qib_pportdata *ppd)
7374{
7375 u64 data;
7376 u32 le_val;
7377
7378 /*
7379 * Initialize the Tx DDS tables. Also done every QSFP event,
7380 * for adapters with QSFP
7381 */
7382 init_txdds_table(ppd, 0);
7383
a77fcf89
RC		 7384 /* ensure no tx overrides from earlier driver loads */
7385 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7386 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7387 reset_tx_deemphasis_override));
7388
f931551b
RC		 7389 /* Patch some SerDes defaults to "Better for IB" */
7390 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7391 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7392
7393 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7394 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7395 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7396 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7397
7398 /* May be overridden in qsfp_7322_event */
7399 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7400 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7401
7402 /* enable LE1 adaptation for all but QME, which is disabled */
7403 le_val = IS_QME(ppd->dd) ? 0 : 1;
7404 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7405
7406 /* Clear cmode-override, may be set from older driver */
7407 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7408
7409 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7410 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7411
7412 /* setup LoS params; these are subsystem, so chan == 5 */
7413 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7414 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7415 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7416 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7417 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7418
7419 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7420 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7421 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7422 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7423 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7424
7425 /* LoS filter select enabled */
7426 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7427
7428 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7429 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7430 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7431 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7432
7433 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7434 qib_write_kreg_port(ppd, krp_serdesctrl, data |
7435 SYM_MASK(IBSerdesCtrl_0, RXLOSEN));
7436
7437 /* rxbistena; set 0 to avoid effects of it switch later */
7438 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7439
7440 /* Configure 4 DFE taps, and only they adapt */
7441 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7442
7443 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7444 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7445 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7446
7447 /*
7448 * Set receive adaptation mode. SDR and DDR adaptation are
7449 * always on, and QDR is initially enabled; later disabled.
7450 */
7451 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7452 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7453 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7454 ppd->dd->cspec->r1 ?
7455 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7456 ppd->cpspec->qdr_dfe_on = 1;
7457
a77fcf89 7458 /* FLoop LOS gate: PPM filter enabled */
f931551b
RC		 7459 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7460
7461 /* rx offset center enabled */
7462 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7463
7464 if (!ppd->dd->cspec->r1) {
7465 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7466 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7467 }
7468
7469 /* Set the frequency loop bandwidth to 15 */
7470 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7471
7472 return 0;
7473}
7474
7475/* start adjust QMH serdes parameters */
7476
7477static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7478{
7479 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7480 9, code << 9, 0x3f << 9);
7481}
7482
7483static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7484 int enable, u32 tapenable)
7485{
7486 if (enable)
7487 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7488 1, 3 << 10, 0x1f << 10);
7489 else
7490 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7491 1, 0, 0x1f << 10);
7492}
7493
7494/* Set clock to 1, 0, 1, 0 */
7495static void clock_man(struct qib_pportdata *ppd, int chan)
7496{
7497 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7498 4, 0x4000, 0x4000);
7499 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7500 4, 0, 0x4000);
7501 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7502 4, 0x4000, 0x4000);
7503 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7504 4, 0, 0x4000);
7505}
7506
7507/*
7508 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7509 * The caller must pass the settings appropriate for the current speed,
7510 * or not care if they are correct for the current speed.
7511 */
7512static void write_tx_serdes_param(struct qib_pportdata *ppd,
7513 struct txdds_ent *txdds)
7514{
7515 u64 deemph;
7516
7517 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7518 /* field names for amp, main, post, pre, respectively */
7519 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7520 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7521 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7522 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
a77fcf89
RC		 7523
7524 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7525 tx_override_deemphasis_select);
7526 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7527 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7528 txampcntl_d2a);
7529 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7530 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7531 txc0_ena);
7532 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7533 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7534 txcp1_ena);
7535 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7536 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
f931551b
RC		 7537 txcn1_ena);
7538 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7539}
7540
7541/*
a77fcf89
RC		 7542 * Set the parameters for mez cards on link bounce, so they are
7543 * always exactly what was requested. Similar logic to init_txdds
7544 * but does just the serdes.
f931551b
RC		 7545 */
7546static void adj_tx_serdes(struct qib_pportdata *ppd)
7547{
a77fcf89
RC		 7548 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7549 struct txdds_ent *dds;
f931551b 7550
a77fcf89
RC		 7551 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7552 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7553 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7554 ddr_dds : sdr_dds));
7555 write_tx_serdes_param(ppd, dds);
f931551b
RC		 7556}
7557
7558/* set QDR forced value for H1, if needed */
7559static void force_h1(struct qib_pportdata *ppd)
7560{
7561 int chan;
7562
7563 ppd->cpspec->qdr_reforce = 0;
7564 if (!ppd->dd->cspec->r1)
7565 return;
7566
7567 for (chan = 0; chan < SERDES_CHANS; chan++) {
7568 set_man_mode_h1(ppd, chan, 1, 0);
7569 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7570 clock_man(ppd, chan);
7571 set_man_mode_h1(ppd, chan, 0, 0);
7572 }
7573}
7574
f931551b
RC		 7575#define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7576#define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7577
7578#define R_OPCODE_LSB 3
7579#define R_OP_NOP 0
7580#define R_OP_SHIFT 2
7581#define R_OP_UPDATE 3
7582#define R_TDI_LSB 2
7583#define R_TDO_LSB 1
7584#define R_RDY 1
7585
7586static int qib_r_grab(struct qib_devdata *dd)
7587{
7588 u64 val;
7589 val = SJA_EN;
7590 qib_write_kreg(dd, kr_r_access, val);
7591 qib_read_kreg32(dd, kr_scratch);
7592 return 0;
7593}
7594
7595/* qib_r_wait_for_rdy() not only waits for the ready bit, it
7596 * returns the current state of R_TDO
7597 */
7598static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7599{
7600 u64 val;
7601 int timeout;
7602 for (timeout = 0; timeout < 100 ; ++timeout) {
7603 val = qib_read_kreg32(dd, kr_r_access);
7604 if (val & R_RDY)
7605 return (val >> R_TDO_LSB) & 1;
7606 }
7607 return -1;
7608}
7609
7610static int qib_r_shift(struct qib_devdata *dd, int bisten,
7611 int len, u8 *inp, u8 *outp)
7612{
7613 u64 valbase, val;
7614 int ret, pos;
7615
7616 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7617 (R_OP_SHIFT << R_OPCODE_LSB);
7618 ret = qib_r_wait_for_rdy(dd);
7619 if (ret < 0)
7620 goto bail;
7621 for (pos = 0; pos < len; ++pos) {
7622 val = valbase;
7623 if (outp) {
7624 outp[pos >> 3] &= ~(1 << (pos & 7));
7625 outp[pos >> 3] |= (ret << (pos & 7));
7626 }
7627 if (inp) {
7628 int tdi = inp[pos >> 3] >> (pos & 7);
7629 val |= ((tdi & 1) << R_TDI_LSB);
7630 }
7631 qib_write_kreg(dd, kr_r_access, val);
7632 qib_read_kreg32(dd, kr_scratch);
7633 ret = qib_r_wait_for_rdy(dd);
7634 if (ret < 0)
7635 break;
7636 }
7637 /* Restore to NOP between operations. */
7638 val = SJA_EN | (bisten << BISTEN_LSB);
7639 qib_write_kreg(dd, kr_r_access, val);
7640 qib_read_kreg32(dd, kr_scratch);
7641 ret = qib_r_wait_for_rdy(dd);
7642
7643 if (ret >= 0)
7644 ret = pos;
7645bail:
7646 return ret;
7647}
7648
7649static int qib_r_update(struct qib_devdata *dd, int bisten)
7650{
7651 u64 val;
7652 int ret;
7653
7654 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7655 ret = qib_r_wait_for_rdy(dd);
7656 if (ret >= 0) {
7657 qib_write_kreg(dd, kr_r_access, val);
7658 qib_read_kreg32(dd, kr_scratch);
7659 }
7660 return ret;
7661}
7662
7663#define BISTEN_PORT_SEL 15
7664#define LEN_PORT_SEL 625
7665#define BISTEN_AT 17
7666#define LEN_AT 156
7667#define BISTEN_ETM 16
7668#define LEN_ETM 632
7669
7670#define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7671
7672/* these are common for all IB port use cases. */
7673static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7674 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7676};
7677static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7678 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7679 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7680 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7681 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7682 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7683 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7684 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7685 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7686};
7687static u8 at[BIT2BYTE(LEN_AT)] = {
7688 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7689 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7690};
7691
7692/* used for IB1 or IB2, only one in use */
7693static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7694 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7696 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7697 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7698 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7699 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7700 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7701 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7702};
7703
7704/* used when both IB1 and IB2 are in use */
7705static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7706 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7707 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7708 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7709 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7710 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7711 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7712 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7713 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7714};
7715
7716/* used when only IB1 is in use */
7717static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
7718 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7719 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7720 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7721 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7722 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7723 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7724 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7725 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7726};
7727
7728/* used when only IB2 is in use */
7729static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
7730 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7731 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7732 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7733 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7734 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7735 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7736 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7737 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7738};
7739
7740/* used when both IB1 and IB2 are in use */
7741static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
7742 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7743 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7744 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7745 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7746 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7747 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7748 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7749 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7750};
7751
7752/*
7753 * Do setup to properly handle IB link recovery; if port is zero, we
7754 * are initializing to cover both ports; otherwise we are initializing
7755 * to cover a single port card, or the port has reached INIT and we may
7756 * need to switch coverage types.
7757 */
7758static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
7759{
7760 u8 *portsel, *etm;
7761 struct qib_devdata *dd = ppd->dd;
7762
7763 if (!ppd->dd->cspec->r1)
7764 return;
7765 if (!both) {
7766 dd->cspec->recovery_ports_initted++;
7767 ppd->cpspec->recovery_init = 1;
7768 }
7769 if (!both && dd->cspec->recovery_ports_initted == 1) {
7770 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
7771 etm = atetm_1port;
7772 } else {
7773 portsel = portsel_2port;
7774 etm = atetm_2port;
7775 }
7776
7777 if (qib_r_grab(dd) < 0 ||
7778 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
7779 qib_r_update(dd, BISTEN_ETM) < 0 ||
7780 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
7781 qib_r_update(dd, BISTEN_AT) < 0 ||
7782 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
7783 portsel, NULL) < 0 ||
7784 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
7785 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
7786 qib_r_update(dd, BISTEN_AT) < 0 ||
7787 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
7788 qib_r_update(dd, BISTEN_ETM) < 0)
7789 qib_dev_err(dd, "Failed IB link recovery setup\n");
7790}
7791
7792static void check_7322_rxe_status(struct qib_pportdata *ppd)
7793{
7794 struct qib_devdata *dd = ppd->dd;
7795 u64 fmask;
7796
7797 if (dd->cspec->recovery_ports_initted != 1)
7798 return; /* rest doesn't apply to dualport */
7799 qib_write_kreg(dd, kr_control, dd->control |
7800 SYM_MASK(Control, FreezeMode));
7801 (void)qib_read_kreg64(dd, kr_scratch);
7802 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
7803 fmask = qib_read_kreg64(dd, kr_act_fmask);
7804 if (!fmask) {
7805 /*
7806 * require a powercycle before we'll work again, and make
7807 * sure we get no more interrupts, and don't turn off
7808 * freeze.
7809 */
7810 ppd->dd->cspec->stay_in_freeze = 1;
7811 qib_7322_set_intr_state(ppd->dd, 0);
7812 qib_write_kreg(dd, kr_fmask, 0ULL);
7813 qib_dev_err(dd, "HCA unusable until powercycled\n");
7814 return; /* eventually reset */
7815 }
7816
7817 qib_write_kreg(ppd->dd, kr_hwerrclear,
7818 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
7819
7820 /* don't do the full clear_freeze(), not needed for this */
7821 qib_write_kreg(dd, kr_control, dd->control);
7822 qib_read_kreg32(dd, kr_scratch);
7823 /* take IBC out of reset */
7824 if (ppd->link_speed_supported) {
7825 ppd->cpspec->ibcctrl_a &=
7826 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
7827 qib_write_kreg_port(ppd, krp_ibcctrl_a,
7828 ppd->cpspec->ibcctrl_a);
7829 qib_read_kreg32(dd, kr_scratch);
7830 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
7831 qib_set_ib_7322_lstate(ppd, 0,
7832 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
7833 }
7834}
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