[linux.git] / drivers / edac / x38_edac.c

/*
 * Intel X38 Memory Controller kernel module
 * Copyright (C) 2008 Cluster Computing, Inc.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * This file is based on i3200_edac.c
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>

#include <asm-generic/io-64-nonatomic-lo-hi.h>
#include "edac_core.h"

#define X38_REVISION		"1.1"

#define EDAC_MOD_STR		"x38_edac"

#define PCI_DEVICE_ID_INTEL_X38_HB	0x29e0

#define X38_RANKS		8
#define X38_RANKS_PER_CHANNEL	4
#define X38_CHANNELS		2

/* Intel X38 register addresses - device 0 function 0 - DRAM Controller */

#define X38_MCHBAR_LOW	0x48	/* MCH Memory Mapped Register BAR */
#define X38_MCHBAR_HIGH	0x4c
#define X38_MCHBAR_MASK	0xfffffc000ULL	/* bits 35:14 */
#define X38_MMR_WINDOW_SIZE	16384

#define X38_TOM	0xa0	/* Top of Memory (16b)
				 *
				 * 15:10 reserved
				 *  9:0  total populated physical memory
				 */
#define X38_TOM_MASK	0x3ff	/* bits 9:0 */
#define X38_TOM_SHIFT 26	/* 64MiB grain */

#define X38_ERRSTS	0xc8	/* Error Status Register (16b)
				 *
				 * 15    reserved
				 * 14    Isochronous TBWRR Run Behind FIFO Full
				 *       (ITCV)
				 * 13    Isochronous TBWRR Run Behind FIFO Put
				 *       (ITSTV)
				 * 12    reserved
				 * 11    MCH Thermal Sensor Event
				 *       for SMI/SCI/SERR (GTSE)
				 * 10    reserved
				 *  9    LOCK to non-DRAM Memory Flag (LCKF)
				 *  8    reserved
				 *  7    DRAM Throttle Flag (DTF)
				 *  6:2  reserved
				 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
				 *  0    Single-bit DRAM ECC Error Flag (DSERR)
				 */
#define X38_ERRSTS_UE		0x0002
#define X38_ERRSTS_CE		0x0001
#define X38_ERRSTS_BITS	(X38_ERRSTS_UE | X38_ERRSTS_CE)


/* Intel  MMIO register space - device 0 function 0 - MMR space */

#define X38_C0DRB	0x200	/* Channel 0 DRAM Rank Boundary (16b x 4)
				 *
				 * 15:10 reserved
				 *  9:0  Channel 0 DRAM Rank Boundary Address
				 */
#define X38_C1DRB	0x600	/* Channel 1 DRAM Rank Boundary (16b x 4) */
#define X38_DRB_MASK	0x3ff	/* bits 9:0 */
#define X38_DRB_SHIFT 26	/* 64MiB grain */

#define X38_C0ECCERRLOG 0x280	/* Channel 0 ECC Error Log (64b)
				 *
				 * 63:48 Error Column Address (ERRCOL)
				 * 47:32 Error Row Address (ERRROW)
				 * 31:29 Error Bank Address (ERRBANK)
				 * 28:27 Error Rank Address (ERRRANK)
				 * 26:24 reserved
				 * 23:16 Error Syndrome (ERRSYND)
				 * 15: 2 reserved
				 *    1  Multiple Bit Error Status (MERRSTS)
				 *    0  Correctable Error Status (CERRSTS)
				 */
#define X38_C1ECCERRLOG 0x680	/* Channel 1 ECC Error Log (64b) */
#define X38_ECCERRLOG_CE	0x1
#define X38_ECCERRLOG_UE	0x2
#define X38_ECCERRLOG_RANK_BITS	0x18000000
#define X38_ECCERRLOG_SYNDROME_BITS	0xff0000

#define X38_CAPID0 0xe0	/* see P.94 of spec for details */

static int x38_channel_num;

static int how_many_channel(struct pci_dev *pdev)
{
	unsigned char capid0_8b; /* 8th byte of CAPID0 */

	pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b);
	if (capid0_8b & 0x20) {	/* check DCD: Dual Channel Disable */
		edac_dbg(0, "In single channel mode\n");
		x38_channel_num = 1;
	} else {
		edac_dbg(0, "In dual channel mode\n");
		x38_channel_num = 2;
	}

	return x38_channel_num;
}

static unsigned long eccerrlog_syndrome(u64 log)
{
	return (log & X38_ECCERRLOG_SYNDROME_BITS) >> 16;
}

static int eccerrlog_row(int channel, u64 log)
{
	return ((log & X38_ECCERRLOG_RANK_BITS) >> 27) |
		(channel * X38_RANKS_PER_CHANNEL);
}

enum x38_chips {
	X38 = 0,
};

struct x38_dev_info {
	const char *ctl_name;
};

struct x38_error_info {
	u16 errsts;
	u16 errsts2;
	u64 eccerrlog[X38_CHANNELS];
};

static const struct x38_dev_info x38_devs[] = {
	[X38] = {
		.ctl_name = "x38"},
};

static struct pci_dev *mci_pdev;
static int x38_registered = 1;


static void x38_clear_error_info(struct mem_ctl_info *mci)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);

	/*
	 * Clear any error bits.
	 * (Yes, we really clear bits by writing 1 to them.)
	 */
	pci_write_bits16(pdev, X38_ERRSTS, X38_ERRSTS_BITS,
			 X38_ERRSTS_BITS);
}

static void x38_get_and_clear_error_info(struct mem_ctl_info *mci,
				 struct x38_error_info *info)
{
	struct pci_dev *pdev;
	void __iomem *window = mci->pvt_info;

	pdev = to_pci_dev(mci->pdev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, X38_ERRSTS, &info->errsts);
	if (!(info->errsts & X38_ERRSTS_BITS))
		return;

	info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);
	if (x38_channel_num == 2)
		info->eccerrlog[1] = lo_hi_readq(window + X38_C1ECCERRLOG);

	pci_read_config_word(pdev, X38_ERRSTS, &info->errsts2);

	/*
	 * If the error is the same for both reads then the first set
	 * of reads is valid.  If there is a change then there is a CE
	 * with no info and the second set of reads is valid and
	 * should be UE info.
	 */
	if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
		info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);
		if (x38_channel_num == 2)
			info->eccerrlog[1] =
				lo_hi_readq(window + X38_C1ECCERRLOG);
	}

	x38_clear_error_info(mci);
}

static void x38_process_error_info(struct mem_ctl_info *mci,
				struct x38_error_info *info)
{
	int channel;
	u64 log;

	if (!(info->errsts & X38_ERRSTS_BITS))
		return;

	if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
				     -1, -1, -1,
				     "UE overwrote CE", "");
		info->errsts = info->errsts2;
	}

	for (channel = 0; channel < x38_channel_num; channel++) {
		log = info->eccerrlog[channel];
		if (log & X38_ECCERRLOG_UE) {
			edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
					     0, 0, 0,
					     eccerrlog_row(channel, log),
					     -1, -1,
					     "x38 UE", "");
		} else if (log & X38_ECCERRLOG_CE) {
			edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
					     0, 0, eccerrlog_syndrome(log),
					     eccerrlog_row(channel, log),
					     -1, -1,
					     "x38 CE", "");
		}
	}
}

static void x38_check(struct mem_ctl_info *mci)
{
	struct x38_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	x38_get_and_clear_error_info(mci, &info);
	x38_process_error_info(mci, &info);
}

static void __iomem *x38_map_mchbar(struct pci_dev *pdev)
{
	union {
		u64 mchbar;
		struct {
			u32 mchbar_low;
			u32 mchbar_high;
		};
	} u;
	void __iomem *window;

	pci_read_config_dword(pdev, X38_MCHBAR_LOW, &u.mchbar_low);
	pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low | 0x1);
	pci_read_config_dword(pdev, X38_MCHBAR_HIGH, &u.mchbar_high);
	u.mchbar &= X38_MCHBAR_MASK;

	if (u.mchbar != (resource_size_t)u.mchbar) {
		printk(KERN_ERR
			"x38: mmio space beyond accessible range (0x%llx)\n",
			(unsigned long long)u.mchbar);
		return NULL;
	}

	window = ioremap_nocache(u.mchbar, X38_MMR_WINDOW_SIZE);
	if (!window)
		printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n",
			(unsigned long long)u.mchbar);

	return window;
}


static void x38_get_drbs(void __iomem *window,
			u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
{
	int i;

	for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) {
		drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK;
		drbs[1][i] = readw(window + X38_C1DRB + 2*i) & X38_DRB_MASK;
	}
}

static bool x38_is_stacked(struct pci_dev *pdev,
			u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
{
	u16 tom;

	pci_read_config_word(pdev, X38_TOM, &tom);
	tom &= X38_TOM_MASK;

	return drbs[X38_CHANNELS - 1][X38_RANKS_PER_CHANNEL - 1] == tom;
}

static unsigned long drb_to_nr_pages(
			u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL],
			bool stacked, int channel, int rank)
{
	int n;

	n = drbs[channel][rank];
	if (rank > 0)
		n -= drbs[channel][rank - 1];
	if (stacked && (channel == 1) && drbs[channel][rank] ==
				drbs[channel][X38_RANKS_PER_CHANNEL - 1]) {
		n -= drbs[0][X38_RANKS_PER_CHANNEL - 1];
	}

	n <<= (X38_DRB_SHIFT - PAGE_SHIFT);
	return n;
}

static int x38_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc;
	int i, j;
	struct mem_ctl_info *mci = NULL;
	struct edac_mc_layer layers[2];
	u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL];
	bool stacked;
	void __iomem *window;

	edac_dbg(0, "MC:\n");

	window = x38_map_mchbar(pdev);
	if (!window)
		return -ENODEV;

	x38_get_drbs(window, drbs);

	how_many_channel(pdev);

	/* FIXME: unconventional pvt_info usage */
	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = X38_RANKS;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = x38_channel_num;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
	if (!mci)
		return -ENOMEM;

	edac_dbg(3, "MC: init mci\n");

	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR2;

	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = X38_REVISION;
	mci->ctl_name = x38_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = x38_check;
	mci->ctl_page_to_phys = NULL;
	mci->pvt_info = window;

	stacked = x38_is_stacked(pdev, drbs);

	/*
	 * The dram rank boundary (DRB) reg values are boundary addresses
	 * for each DRAM rank with a granularity of 64MB.  DRB regs are
	 * cumulative; the last one will contain the total memory
	 * contained in all ranks.
	 */
	for (i = 0; i < mci->nr_csrows; i++) {
		unsigned long nr_pages;
		struct csrow_info *csrow = mci->csrows[i];

		nr_pages = drb_to_nr_pages(drbs, stacked,
			i / X38_RANKS_PER_CHANNEL,
			i % X38_RANKS_PER_CHANNEL);

		if (nr_pages == 0)
			continue;

		for (j = 0; j < x38_channel_num; j++) {
			struct dimm_info *dimm = csrow->channels[j]->dimm;

			dimm->nr_pages = nr_pages / x38_channel_num;
			dimm->grain = nr_pages << PAGE_SHIFT;
			dimm->mtype = MEM_DDR2;
			dimm->dtype = DEV_UNKNOWN;
			dimm->edac_mode = EDAC_UNKNOWN;
		}
	}

	x38_clear_error_info(mci);

	rc = -ENODEV;
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* get this far and it's successful */
	edac_dbg(3, "MC: success\n");
	return 0;

fail:
	iounmap(window);
	if (mci)
		edac_mc_free(mci);

	return rc;
}

static int x38_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	int rc;

	edac_dbg(0, "MC:\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = x38_probe1(pdev, ent->driver_data);
	if (!mci_pdev)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void x38_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	mci = edac_mc_del_mc(&pdev->dev);
	if (!mci)
		return;

	iounmap(mci->pvt_info);

	edac_mc_free(mci);
}

static const struct pci_device_id x38_pci_tbl[] = {
	{
	 PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 X38},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, x38_pci_tbl);

static struct pci_driver x38_driver = {
	.name = EDAC_MOD_STR,
	.probe = x38_init_one,
	.remove = x38_remove_one,
	.id_table = x38_pci_tbl,
};

static int __init x38_init(void)
{
	int pci_rc;

	edac_dbg(3, "MC:\n");

	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	opstate_init();

	pci_rc = pci_register_driver(&x38_driver);
	if (pci_rc < 0)
		goto fail0;

	if (!mci_pdev) {
		x38_registered = 0;
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_X38_HB, NULL);
		if (!mci_pdev) {
			edac_dbg(0, "x38 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = x38_init_one(mci_pdev, x38_pci_tbl);
		if (pci_rc < 0) {
			edac_dbg(0, "x38 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&x38_driver);

fail0:
	pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit x38_exit(void)
{
	edac_dbg(3, "MC:\n");

	pci_unregister_driver(&x38_driver);
	if (!x38_registered) {
		x38_remove_one(mci_pdev);
		pci_dev_put(mci_pdev);
	}
}

module_init(x38_init);
module_exit(x38_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Cluster Computing, Inc. Hitoshi Mitake");
MODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
df8bc08c HM	1	/*
	2	* Intel X38 Memory Controller kernel module
	3	* Copyright (C) 2008 Cluster Computing, Inc.
	4	*
	5	* This file may be distributed under the terms of the
	6	* GNU General Public License.
	7	*
	8	* This file is based on i3200_edac.c
	9	*
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
df8bc08c	16	#include <linux/edac.h>
a21e98ce JB	17
a21e98ce JB	18	#include <asm-generic/io-64-nonatomic-lo-hi.h>
df8bc08c HM	19	#include "edac_core.h"
	20
	21	#define X38_REVISION "1.1"
	22
	23	#define EDAC_MOD_STR "x38_edac"
	24
	25	#define PCI_DEVICE_ID_INTEL_X38_HB 0x29e0
	26
	27	#define X38_RANKS 8
	28	#define X38_RANKS_PER_CHANNEL 4
	29	#define X38_CHANNELS 2
	30
	31	/* Intel X38 register addresses - device 0 function 0 - DRAM Controller */
	32
	33	#define X38_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
3d768213	34	#define X38_MCHBAR_HIGH 0x4c
df8bc08c HM	35	#define X38_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */
	36	#define X38_MMR_WINDOW_SIZE 16384
	37
	38	#define X38_TOM 0xa0 /* Top of Memory (16b)
	39	*
	40	* 15:10 reserved
	41	* 9:0 total populated physical memory
	42	*/
	43	#define X38_TOM_MASK 0x3ff /* bits 9:0 */
	44	#define X38_TOM_SHIFT 26 /* 64MiB grain */
	45
	46	#define X38_ERRSTS 0xc8 /* Error Status Register (16b)
	47	*
	48	* 15 reserved
	49	* 14 Isochronous TBWRR Run Behind FIFO Full
	50	* (ITCV)
	51	* 13 Isochronous TBWRR Run Behind FIFO Put
	52	* (ITSTV)
	53	* 12 reserved
	54	* 11 MCH Thermal Sensor Event
	55	* for SMI/SCI/SERR (GTSE)
	56	* 10 reserved
	57	* 9 LOCK to non-DRAM Memory Flag (LCKF)
	58	* 8 reserved
	59	* 7 DRAM Throttle Flag (DTF)
	60	* 6:2 reserved
	61	* 1 Multi-bit DRAM ECC Error Flag (DMERR)
	62	* 0 Single-bit DRAM ECC Error Flag (DSERR)
	63	*/
	64	#define X38_ERRSTS_UE 0x0002
	65	#define X38_ERRSTS_CE 0x0001
	66	#define X38_ERRSTS_BITS (X38_ERRSTS_UE \| X38_ERRSTS_CE)
	67
	68
	69	/* Intel MMIO register space - device 0 function 0 - MMR space */
	70
	71	#define X38_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
	72	*
	73	* 15:10 reserved
	74	* 9:0 Channel 0 DRAM Rank Boundary Address
	75	*/
	76	#define X38_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */
	77	#define X38_DRB_MASK 0x3ff /* bits 9:0 */
	78	#define X38_DRB_SHIFT 26 /* 64MiB grain */
	79
	80	#define X38_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b)
	81	*
	82	* 63:48 Error Column Address (ERRCOL)
	83	* 47:32 Error Row Address (ERRROW)
	84	* 31:29 Error Bank Address (ERRBANK)
	85	* 28:27 Error Rank Address (ERRRANK)
	86	* 26:24 reserved
	87	* 23:16 Error Syndrome (ERRSYND)
	88	* 15: 2 reserved
	89	* 1 Multiple Bit Error Status (MERRSTS)
	90	* 0 Correctable Error Status (CERRSTS)
	91	*/
	92	#define X38_C1ECCERRLOG 0x680 /* Channel 1 ECC Error Log (64b) */
	93	#define X38_ECCERRLOG_CE 0x1
	94	#define X38_ECCERRLOG_UE 0x2
	95	#define X38_ECCERRLOG_RANK_BITS 0x18000000
	96	#define X38_ECCERRLOG_SYNDROME_BITS 0xff0000
	97
	98	#define X38_CAPID0 0xe0 /* see P.94 of spec for details */
99
100	static int x38_channel_num;
101
102	static int how_many_channel(struct pci_dev *pdev)
103	{
104	unsigned char capid0_8b; /* 8th byte of CAPID0 */
105
106	pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b);
107	if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
956b9ba1	108	edac_dbg(0, "In single channel mode\n");
df8bc08c HM	109	x38_channel_num = 1;
df8bc08c HM	110	} else {
956b9ba1	111	edac_dbg(0, "In dual channel mode\n");
df8bc08c HM	112	x38_channel_num = 2;
	113	}
	114
	115	return x38_channel_num;
	116	}
	117
	118	static unsigned long eccerrlog_syndrome(u64 log)
	119	{
	120	return (log & X38_ECCERRLOG_SYNDROME_BITS) >> 16;
	121	}
	122
	123	static int eccerrlog_row(int channel, u64 log)
	124	{
	125	return ((log & X38_ECCERRLOG_RANK_BITS) >> 27) \|
	126	(channel * X38_RANKS_PER_CHANNEL);
	127	}
	128
	129	enum x38_chips {
	130	X38 = 0,
	131	};
	132
	133	struct x38_dev_info {
	134	const char *ctl_name;
	135	};
	136
	137	struct x38_error_info {
	138	u16 errsts;
	139	u16 errsts2;
	140	u64 eccerrlog[X38_CHANNELS];
	141	};
	142
	143	static const struct x38_dev_info x38_devs[] = {
	144	[X38] = {
	145	.ctl_name = "x38"},
	146	};
	147
	148	static struct pci_dev *mci_pdev;
	149	static int x38_registered = 1;
	150
	151
	152	static void x38_clear_error_info(struct mem_ctl_info *mci)
	153	{
	154	struct pci_dev *pdev;
	155
fd687502	156	pdev = to_pci_dev(mci->pdev);
df8bc08c HM	157
	158	/*
	159	* Clear any error bits.
	160	* (Yes, we really clear bits by writing 1 to them.)
	161	*/
	162	pci_write_bits16(pdev, X38_ERRSTS, X38_ERRSTS_BITS,
	163	X38_ERRSTS_BITS);
	164	}
	165
df8bc08c HM	166	static void x38_get_and_clear_error_info(struct mem_ctl_info *mci,
	167	struct x38_error_info *info)
	168	{
	169	struct pci_dev *pdev;
	170	void __iomem *window = mci->pvt_info;
	171
fd687502	172	pdev = to_pci_dev(mci->pdev);
df8bc08c HM	173
	174	/*
	175	* This is a mess because there is no atomic way to read all the
	176	* registers at once and the registers can transition from CE being
	177	* overwritten by UE.
	178	*/
	179	pci_read_config_word(pdev, X38_ERRSTS, &info->errsts);
	180	if (!(info->errsts & X38_ERRSTS_BITS))
	181	return;
	182
a21e98ce	183	info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);
df8bc08c	184	if (x38_channel_num == 2)
a21e98ce	185	info->eccerrlog[1] = lo_hi_readq(window + X38_C1ECCERRLOG);
df8bc08c HM	186
	187	pci_read_config_word(pdev, X38_ERRSTS, &info->errsts2);
	188
	189	/*
	190	* If the error is the same for both reads then the first set
	191	* of reads is valid. If there is a change then there is a CE
	192	* with no info and the second set of reads is valid and
	193	* should be UE info.
	194	*/
	195	if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
a21e98ce	196	info->eccerrlog[0] = lo_hi_readq(window + X38_C0ECCERRLOG);
df8bc08c HM	197	if (x38_channel_num == 2)
df8bc08c HM	198	info->eccerrlog[1] =
a21e98ce	199	lo_hi_readq(window + X38_C1ECCERRLOG);
df8bc08c HM	200	}
	201
	202	x38_clear_error_info(mci);
	203	}
	204
	205	static void x38_process_error_info(struct mem_ctl_info *mci,
	206	struct x38_error_info *info)
	207	{
	208	int channel;
	209	u64 log;
	210
	211	if (!(info->errsts & X38_ERRSTS_BITS))
	212	return;
	213
	214	if ((info->errsts ^ info->errsts2) & X38_ERRSTS_BITS) {
9eb07a7f	215	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
e2acc357	216	-1, -1, -1,
03f7eae8	217	"UE overwrote CE", "");
df8bc08c HM	218	info->errsts = info->errsts2;
	219	}
	220
	221	for (channel = 0; channel < x38_channel_num; channel++) {
	222	log = info->eccerrlog[channel];
	223	if (log & X38_ECCERRLOG_UE) {
9eb07a7f	224	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
e2acc357 MCC	225	0, 0, 0,
	226	eccerrlog_row(channel, log),
	227	-1, -1,
03f7eae8	228	"x38 UE", "");
df8bc08c	229	} else if (log & X38_ECCERRLOG_CE) {
9eb07a7f	230	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
e2acc357 MCC	231	0, 0, eccerrlog_syndrome(log),
	232	eccerrlog_row(channel, log),
	233	-1, -1,
03f7eae8	234	"x38 CE", "");
df8bc08c HM	235	}
	236	}
	237	}
	238
	239	static void x38_check(struct mem_ctl_info *mci)
	240	{
	241	struct x38_error_info info;
	242
956b9ba1	243	edac_dbg(1, "MC%d\n", mci->mc_idx);
df8bc08c HM	244	x38_get_and_clear_error_info(mci, &info);
	245	x38_process_error_info(mci, &info);
	246	}
	247
e0d391ab	248	static void __iomem x38_map_mchbar(struct pci_dev pdev)
df8bc08c HM	249	{
	250	union {
	251	u64 mchbar;
	252	struct {
	253	u32 mchbar_low;
	254	u32 mchbar_high;
	255	};
	256	} u;
	257	void __iomem *window;
	258
	259	pci_read_config_dword(pdev, X38_MCHBAR_LOW, &u.mchbar_low);
	260	pci_write_config_dword(pdev, X38_MCHBAR_LOW, u.mchbar_low \| 0x1);
	261	pci_read_config_dword(pdev, X38_MCHBAR_HIGH, &u.mchbar_high);
	262	u.mchbar &= X38_MCHBAR_MASK;
	263
	264	if (u.mchbar != (resource_size_t)u.mchbar) {
	265	printk(KERN_ERR
	266	"x38: mmio space beyond accessible range (0x%llx)\n",
	267	(unsigned long long)u.mchbar);
	268	return NULL;
	269	}
	270
	271	window = ioremap_nocache(u.mchbar, X38_MMR_WINDOW_SIZE);
	272	if (!window)
	273	printk(KERN_ERR "x38: cannot map mmio space at 0x%llx\n",
	274	(unsigned long long)u.mchbar);
	275
	276	return window;
	277	}
	278
	279
	280	static void x38_get_drbs(void __iomem *window,
	281	u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
	282	{
	283	int i;
	284
	285	for (i = 0; i < X38_RANKS_PER_CHANNEL; i++) {
	286	drbs[0][i] = readw(window + X38_C0DRB + 2*i) & X38_DRB_MASK;
	287	drbs[1][i] = readw(window + X38_C1DRB + 2*i) & X38_DRB_MASK;
	288	}
	289	}
	290
	291	static bool x38_is_stacked(struct pci_dev *pdev,
	292	u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL])
	293	{
	294	u16 tom;
	295
	296	pci_read_config_word(pdev, X38_TOM, &tom);
	297	tom &= X38_TOM_MASK;
	298
	299	return drbs[X38_CHANNELS - 1][X38_RANKS_PER_CHANNEL - 1] == tom;
	300	}
	301
	302	static unsigned long drb_to_nr_pages(
	303	u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL],
	304	bool stacked, int channel, int rank)
	305	{
	306	int n;
	307
	308	n = drbs[channel][rank];
	309	if (rank > 0)
	310	n -= drbs[channel][rank - 1];
	311	if (stacked && (channel == 1) && drbs[channel][rank] ==
	312	drbs[channel][X38_RANKS_PER_CHANNEL - 1]) {
313	n -= drbs[0][X38_RANKS_PER_CHANNEL - 1];
314	}
315
316	n <<= (X38_DRB_SHIFT - PAGE_SHIFT);
317	return n;
318	}
319
320	static int x38_probe1(struct pci_dev *pdev, int dev_idx)
321	{
322	int rc;
084a4fcc	323	int i, j;
df8bc08c	324	struct mem_ctl_info *mci = NULL;
e2acc357	325	struct edac_mc_layer layers[2];
df8bc08c HM	326	u16 drbs[X38_CHANNELS][X38_RANKS_PER_CHANNEL];
	327	bool stacked;
	328	void __iomem *window;
	329
956b9ba1	330	edac_dbg(0, "MC:\n");
df8bc08c HM	331
	332	window = x38_map_mchbar(pdev);
	333	if (!window)
	334	return -ENODEV;
	335
	336	x38_get_drbs(window, drbs);
	337
	338	how_many_channel(pdev);
	339
	340	/* FIXME: unconventional pvt_info usage */
e2acc357 MCC	341	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	342	layers[0].size = X38_RANKS;
	343	layers[0].is_virt_csrow = true;
	344	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	345	layers[1].size = x38_channel_num;
	346	layers[1].is_virt_csrow = false;
ca0907b9	347	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
df8bc08c HM	348	if (!mci)
	349	return -ENOMEM;
	350
956b9ba1	351	edac_dbg(3, "MC: init mci\n");
df8bc08c	352
fd687502	353	mci->pdev = &pdev->dev;
df8bc08c HM	354	mci->mtype_cap = MEM_FLAG_DDR2;
	355
	356	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	357	mci->edac_cap = EDAC_FLAG_SECDED;
	358
	359	mci->mod_name = EDAC_MOD_STR;
	360	mci->mod_ver = X38_REVISION;
	361	mci->ctl_name = x38_devs[dev_idx].ctl_name;
	362	mci->dev_name = pci_name(pdev);
	363	mci->edac_check = x38_check;
	364	mci->ctl_page_to_phys = NULL;
	365	mci->pvt_info = window;
	366
	367	stacked = x38_is_stacked(pdev, drbs);
	368
	369	/*
	370	* The dram rank boundary (DRB) reg values are boundary addresses
	371	* for each DRAM rank with a granularity of 64MB. DRB regs are
	372	* cumulative; the last one will contain the total memory
	373	* contained in all ranks.
	374	*/
df8bc08c HM	375	for (i = 0; i < mci->nr_csrows; i++) {
df8bc08c HM	376	unsigned long nr_pages;
de3910eb	377	struct csrow_info *csrow = mci->csrows[i];
df8bc08c HM	378
	379	nr_pages = drb_to_nr_pages(drbs, stacked,
	380	i / X38_RANKS_PER_CHANNEL,
	381	i % X38_RANKS_PER_CHANNEL);
	382
084a4fcc	383	if (nr_pages == 0)
df8bc08c	384	continue;
df8bc08c	385
084a4fcc	386	for (j = 0; j < x38_channel_num; j++) {
de3910eb	387	struct dimm_info *dimm = csrow->channels[j]->dimm;
a895bf8b MCC	388
a895bf8b MCC	389	dimm->nr_pages = nr_pages / x38_channel_num;
084a4fcc MCC	390	dimm->grain = nr_pages << PAGE_SHIFT;
	391	dimm->mtype = MEM_DDR2;
	392	dimm->dtype = DEV_UNKNOWN;
	393	dimm->edac_mode = EDAC_UNKNOWN;
	394	}
df8bc08c HM	395	}
	396
	397	x38_clear_error_info(mci);
	398
	399	rc = -ENODEV;
	400	if (edac_mc_add_mc(mci)) {
956b9ba1	401	edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
df8bc08c HM	402	goto fail;
	403	}
	404
	405	/* get this far and it's successful */
956b9ba1	406	edac_dbg(3, "MC: success\n");
df8bc08c HM	407	return 0;
	408
	409	fail:
	410	iounmap(window);
	411	if (mci)
	412	edac_mc_free(mci);
	413
	414	return rc;
	415	}
	416
9b3c6e85	417	static int x38_init_one(struct pci_dev pdev, const struct pci_device_id ent)
df8bc08c HM	418	{
	419	int rc;
	420
956b9ba1	421	edac_dbg(0, "MC:\n");
df8bc08c HM	422
	423	if (pci_enable_device(pdev) < 0)
	424	return -EIO;
	425
	426	rc = x38_probe1(pdev, ent->driver_data);
	427	if (!mci_pdev)
	428	mci_pdev = pci_dev_get(pdev);
	429
	430	return rc;
	431	}
	432
9b3c6e85	433	static void x38_remove_one(struct pci_dev *pdev)
df8bc08c HM	434	{
	435	struct mem_ctl_info *mci;
	436
956b9ba1	437	edac_dbg(0, "\n");
df8bc08c HM	438
	439	mci = edac_mc_del_mc(&pdev->dev);
	440	if (!mci)
	441	return;
	442
	443	iounmap(mci->pvt_info);
	444
	445	edac_mc_free(mci);
	446	}
	447
ba935f40	448	static const struct pci_device_id x38_pci_tbl[] = {
df8bc08c HM	449	{
	450	PCI_VEND_DEV(INTEL, X38_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	451	X38},
	452	{
	453	0,
	454	} /* 0 terminated list. */
	455	};
	456
	457	MODULE_DEVICE_TABLE(pci, x38_pci_tbl);
	458
	459	static struct pci_driver x38_driver = {
	460	.name = EDAC_MOD_STR,
	461	.probe = x38_init_one,
9b3c6e85	462	.remove = x38_remove_one,
df8bc08c HM	463	.id_table = x38_pci_tbl,
	464	};
	465
	466	static int __init x38_init(void)
	467	{
	468	int pci_rc;
	469
956b9ba1	470	edac_dbg(3, "MC:\n");
df8bc08c HM	471
	472	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	473	opstate_init();
	474
	475	pci_rc = pci_register_driver(&x38_driver);
	476	if (pci_rc < 0)
	477	goto fail0;
	478
	479	if (!mci_pdev) {
	480	x38_registered = 0;
	481	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
	482	PCI_DEVICE_ID_INTEL_X38_HB, NULL);
	483	if (!mci_pdev) {
956b9ba1	484	edac_dbg(0, "x38 pci_get_device fail\n");
df8bc08c HM	485	pci_rc = -ENODEV;
	486	goto fail1;
	487	}
	488
	489	pci_rc = x38_init_one(mci_pdev, x38_pci_tbl);
	490	if (pci_rc < 0) {
956b9ba1	491	edac_dbg(0, "x38 init fail\n");
df8bc08c HM	492	pci_rc = -ENODEV;
	493	goto fail1;
	494	}
	495	}
	496
	497	return 0;
	498
	499	fail1:
	500	pci_unregister_driver(&x38_driver);
	501
	502	fail0:
0a98babd	503	pci_dev_put(mci_pdev);
df8bc08c HM	504
	505	return pci_rc;
	506	}
	507
	508	static void __exit x38_exit(void)
	509	{
956b9ba1	510	edac_dbg(3, "MC:\n");
df8bc08c HM	511
	512	pci_unregister_driver(&x38_driver);
	513	if (!x38_registered) {
	514	x38_remove_one(mci_pdev);
	515	pci_dev_put(mci_pdev);
	516	}
	517	}
	518
	519	module_init(x38_init);
	520	module_exit(x38_exit);
	521
	522	MODULE_LICENSE("GPL");
	523	MODULE_AUTHOR("Cluster Computing, Inc. Hitoshi Mitake");
	524	MODULE_DESCRIPTION("MC support for Intel X38 memory hub controllers");
	525
	526	module_param(edac_op_state, int, 0444);
	527	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");