[linux.git] / arch / openrisc / Kconfig

#
# For a description of the syntax of this configuration file,
# see Documentation/kbuild/kconfig-language.txt.
#

config OPENRISC
	def_bool y
	select OF
	select OF_EARLY_FLATTREE
	select IRQ_DOMAIN
	select HAVE_MEMBLOCK
	select ARCH_REQUIRE_GPIOLIB
        select HAVE_ARCH_TRACEHOOK
	select GENERIC_IRQ_CHIP
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
	select GENERIC_IOMAP
	select GENERIC_CPU_DEVICES
	select GENERIC_ATOMIC64
	select GENERIC_CLOCKEVENTS
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
	select MODULES_USE_ELF_RELA
	select HAVE_DEBUG_STACKOVERFLOW

config MMU
	def_bool y

config HAVE_DMA_ATTRS
	def_bool y

config UID16
	def_bool y

config RWSEM_GENERIC_SPINLOCK
	def_bool y

config RWSEM_XCHGADD_ALGORITHM
	def_bool n

config GENERIC_HWEIGHT
	def_bool y

config NO_IOPORT
	def_bool y

config TRACE_IRQFLAGS_SUPPORT
        def_bool y

# For now, use generic checksum functions
#These can be reimplemented in assembly later if so inclined
config GENERIC_CSUM
        def_bool y

source "init/Kconfig"

source "kernel/Kconfig.freezer"

menu "Processor type and features"

choice
	prompt "Subarchitecture"
	default OR1K_1200

config OR1K_1200
	bool "OR1200"
	help
	  Generic OpenRISC 1200 architecture

endchoice

config OPENRISC_BUILTIN_DTB
        string "Builtin DTB"
        default ""

menu "Class II Instructions"

config OPENRISC_HAVE_INST_FF1
	bool "Have instruction l.ff1"
	default y
	help
	  Select this if your implementation has the Class II instruction l.ff1

config OPENRISC_HAVE_INST_FL1
	bool "Have instruction l.fl1"
	default y
	help
	  Select this if your implementation has the Class II instruction l.fl1

config OPENRISC_HAVE_INST_MUL
	bool "Have instruction l.mul for hardware multiply"
	default y
	help
	  Select this if your implementation has a hardware multiply instruction

config OPENRISC_HAVE_INST_DIV
	bool "Have instruction l.div for hardware divide"
	default y
	help
	  Select this if your implementation has a hardware divide instruction
endmenu


source kernel/Kconfig.hz
source kernel/Kconfig.preempt
source "mm/Kconfig"

config OPENRISC_NO_SPR_SR_DSX
	bool "use SPR_SR_DSX software emulation" if OR1K_1200
	default y
	help
	  SPR_SR_DSX bit is status register bit indicating whether
	  the last exception has happened in delay slot.

	  OpenRISC architecture makes it optional to have it implemented
	  in hardware and the OR1200 does not have it.

	  Say N here if you know that your OpenRISC processor has
	  SPR_SR_DSX bit implemented. Say Y if you are unsure.

config CMDLINE
        string "Default kernel command string"
        default ""
        help
          On some architectures there is currently no way for the boot loader
          to pass arguments to the kernel. For these architectures, you should
          supply some command-line options at build time by entering them
          here.

menu "Debugging options"

config JUMP_UPON_UNHANDLED_EXCEPTION
	bool "Try to die gracefully"
	default y
	help
	  Now this puts kernel into infinite loop after first oops. Till
	  your kernel crashes this doesn't have any influence.

	  Say Y if you are unsure.

config OPENRISC_ESR_EXCEPTION_BUG_CHECK
	bool "Check for possible ESR exception bug"
	default n
	help
	  This option enables some checks that might expose some problems
          in kernel.

	  Say N if you are unsure.

endmenu

endmenu

menu "Executable file formats"

source "fs/Kconfig.binfmt"

endmenu

source "net/Kconfig"

source "drivers/Kconfig"

source "fs/Kconfig"

source "security/Kconfig"

source "crypto/Kconfig"

source "lib/Kconfig"

menu "Kernel hacking"

source "lib/Kconfig.debug"

endmenu
Commit	Line	Data
f8c4a270 JB	1	#
f8c4a270 JB	2	# For a description of the syntax of this configuration file,
395cf969	3	# see Documentation/kbuild/kconfig-language.txt.
f8c4a270 JB	4	#
	5
	6	config OPENRISC
	7	def_bool y
	8	select OF
	9	select OF_EARLY_FLATTREE
b4c4c6ee	10	select IRQ_DOMAIN
f8c4a270	11	select HAVE_MEMBLOCK
d4cb776f	12	select ARCH_REQUIRE_GPIOLIB
f8c4a270	13	select HAVE_ARCH_TRACEHOOK
f8c4a270 JB	14	select GENERIC_IRQ_CHIP
	15	select GENERIC_IRQ_PROBE
	16	select GENERIC_IRQ_SHOW
	17	select GENERIC_IOMAP
9f13a1fd	18	select GENERIC_CPU_DEVICES
0662d33a	19	select GENERIC_ATOMIC64
5bf8f6bf	20	select GENERIC_CLOCKEVENTS
603d6637	21	select GENERIC_STRNCPY_FROM_USER
b48b2c3e	22	select GENERIC_STRNLEN_USER
786d35d4	23	select MODULES_USE_ELF_RELA
d1a1dc0b	24	select HAVE_DEBUG_STACKOVERFLOW
f8c4a270 JB	25
	26	config MMU
	27	def_bool y
	28
f8c4a270 JB	29	config HAVE_DMA_ATTRS
	30	def_bool y
	31
	32	config UID16
	33	def_bool y
	34
	35	config RWSEM_GENERIC_SPINLOCK
	36	def_bool y
	37
	38	config RWSEM_XCHGADD_ALGORITHM
	39	def_bool n
	40
	41	config GENERIC_HWEIGHT
	42	def_bool y
	43
f8c4a270 JB	44	config NO_IOPORT
	45	def_bool y
	46
f8c4a270 JB	47	config TRACE_IRQFLAGS_SUPPORT
	48	def_bool y
	49
	50	# For now, use generic checksum functions
	51	#These can be reimplemented in assembly later if so inclined
	52	config GENERIC_CSUM
	53	def_bool y
	54
f8c4a270 JB	55	source "init/Kconfig"
f8c4a270 JB	56
57a1a197	57	source "kernel/Kconfig.freezer"
f8c4a270 JB	58
	59	menu "Processor type and features"
	60
	61	choice
	62	prompt "Subarchitecture"
	63	default OR1K_1200
	64
	65	config OR1K_1200
	66	bool "OR1200"
	67	help
	68	Generic OpenRISC 1200 architecture
	69
	70	endchoice
	71
	72	config OPENRISC_BUILTIN_DTB
	73	string "Builtin DTB"
	74	default ""
	75
	76	menu "Class II Instructions"
	77
	78	config OPENRISC_HAVE_INST_FF1
	79	bool "Have instruction l.ff1"
	80	default y
	81	help
	82	Select this if your implementation has the Class II instruction l.ff1
	83
	84	config OPENRISC_HAVE_INST_FL1
	85	bool "Have instruction l.fl1"
	86	default y
	87	help
	88	Select this if your implementation has the Class II instruction l.fl1
	89
	90	config OPENRISC_HAVE_INST_MUL
	91	bool "Have instruction l.mul for hardware multiply"
	92	default y
	93	help
	94	Select this if your implementation has a hardware multiply instruction
	95
	96	config OPENRISC_HAVE_INST_DIV
	97	bool "Have instruction l.div for hardware divide"
	98	default y
	99	help
	100	Select this if your implementation has a hardware divide instruction
	101	endmenu
	102
	103
f8c4a270 JB	104	source kernel/Kconfig.hz
	105	source kernel/Kconfig.preempt
	106	source "mm/Kconfig"
	107
	108	config OPENRISC_NO_SPR_SR_DSX
	109	bool "use SPR_SR_DSX software emulation" if OR1K_1200
	110	default y
	111	help
	112	SPR_SR_DSX bit is status register bit indicating whether
	113	the last exception has happened in delay slot.
	114
	115	OpenRISC architecture makes it optional to have it implemented
	116	in hardware and the OR1200 does not have it.
	117
	118	Say N here if you know that your OpenRISC processor has
	119	SPR_SR_DSX bit implemented. Say Y if you are unsure.
	120
	121	config CMDLINE
	122	string "Default kernel command string"
	123	default ""
	124	help
	125	On some architectures there is currently no way for the boot loader
	126	to pass arguments to the kernel. For these architectures, you should
	127	supply some command-line options at build time by entering them
	128	here.
	129
	130	menu "Debugging options"
	131
f8c4a270 JB	132	config JUMP_UPON_UNHANDLED_EXCEPTION
	133	bool "Try to die gracefully"
	134	default y
	135	help
	136	Now this puts kernel into infinite loop after first oops. Till
	137	your kernel crashes this doesn't have any influence.
	138
	139	Say Y if you are unsure.
	140
f8c4a270 JB	141	config OPENRISC_ESR_EXCEPTION_BUG_CHECK
	142	bool "Check for possible ESR exception bug"
	143	default n
	144	help
	145	This option enables some checks that might expose some problems
	146	in kernel.
	147
	148	Say N if you are unsure.
	149
	150	endmenu
	151
	152	endmenu
	153
	154	menu "Executable file formats"
	155
	156	source "fs/Kconfig.binfmt"
	157
	158	endmenu
	159
	160	source "net/Kconfig"
	161
	162	source "drivers/Kconfig"
	163
	164	source "fs/Kconfig"
	165
	166	source "security/Kconfig"
	167
	168	source "crypto/Kconfig"
	169
	170	source "lib/Kconfig"
	171
	172	menu "Kernel hacking"
	173
	174	source "lib/Kconfig.debug"
	175
	176	endmenu