[linux.git] / arch / mn10300 / mm / Kconfig.cache

#
# MN10300 CPU cache options
#

choice
	prompt "CPU Caching mode"
	default MN10300_CACHE_WBACK
	help
	  This option determines the caching mode for the kernel.

	  Write-Back caching mode involves the all reads and writes causing
	  the affected cacheline to be read into the cache first before being
	  operated upon. Memory is not then updated by a write until the cache
	  is filled and a cacheline needs to be displaced from the cache to
	  make room. Only at that point is it written back.

	  Write-Through caching only fetches cachelines from memory on a
	  read. Writes always get written directly to memory. If the affected
	  cacheline is also in cache, it will be updated too.

	  The final option is to turn of caching entirely.

config MN10300_CACHE_WBACK
	bool "Write-Back"
	help
	  The dcache operates in delayed write-back mode.  It must be manually
	  flushed if writes are made that subsequently need to be executed or
	  to be DMA'd by a device.

config MN10300_CACHE_WTHRU
	bool "Write-Through"
	help
	  The dcache operates in immediate write-through mode.  Writes are
	  committed to RAM immediately in addition to being stored in the
	  cache.  This means that the written data is immediately available for
	  execution or DMA.

	  This is not available for use with an SMP kernel if cache flushing
	  and invalidation by automatic purge register is not selected.

config MN10300_CACHE_DISABLED
	bool "Disabled"
	help
	  The icache and dcache are disabled.

endchoice

config MN10300_CACHE_ENABLED
	def_bool y if !MN10300_CACHE_DISABLED


choice
	prompt "CPU cache flush/invalidate method"
	default MN10300_CACHE_MANAGE_BY_TAG if !AM34_2
	default MN10300_CACHE_MANAGE_BY_REG if AM34_2
	depends on MN10300_CACHE_ENABLED
	help
	  This determines the method by which CPU cache flushing and
	  invalidation is performed.

config MN10300_CACHE_MANAGE_BY_TAG
	bool "Use the cache tag registers directly"
	depends on !(SMP && MN10300_CACHE_WTHRU)

config MN10300_CACHE_MANAGE_BY_REG
	bool "Flush areas by way of automatic purge registers (AM34 only)"
	depends on AM34_2

endchoice

config MN10300_CACHE_INV_BY_TAG
	def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED

config MN10300_CACHE_INV_BY_REG
	def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_ENABLED

config MN10300_CACHE_FLUSH_BY_TAG
	def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK

config MN10300_CACHE_FLUSH_BY_REG
	def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK


config MN10300_HAS_CACHE_SNOOP
	def_bool n

config MN10300_CACHE_SNOOP
	bool "Use CPU Cache Snooping"
	depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP
	default y

config MN10300_CACHE_FLUSH_ICACHE
	def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP
	help
	  Set if we need the dcache flushing before the icache is invalidated.

config MN10300_CACHE_INV_ICACHE
	def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP
	help
	  Set if we need the icache to be invalidated, even if the dcache is in
	  write-through mode and doesn't need flushing.

#
# The kernel debugger gets its own separate cache flushing functions
#
config MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG
	def_bool y if KERNEL_DEBUGGER && \
			MN10300_CACHE_WBACK && \
			!MN10300_CACHE_SNOOP && \
			MN10300_CACHE_MANAGE_BY_TAG
	help
	  Set if the debugger needs to flush the dcache and invalidate the
	  icache using the cache tag registers to make breakpoints work.

config MN10300_DEBUGGER_CACHE_FLUSH_BY_REG
	def_bool y if KERNEL_DEBUGGER && \
			MN10300_CACHE_WBACK && \
			!MN10300_CACHE_SNOOP && \
			MN10300_CACHE_MANAGE_BY_REG
	help
	  Set if the debugger needs to flush the dcache and invalidate the
	  icache using automatic purge registers to make breakpoints work.

config MN10300_DEBUGGER_CACHE_INV_BY_TAG
	def_bool y if KERNEL_DEBUGGER && \
			MN10300_CACHE_WTHRU && \
			!MN10300_CACHE_SNOOP && \
			MN10300_CACHE_MANAGE_BY_TAG
	help
	  Set if the debugger needs to invalidate the icache using the cache
	  tag registers to make breakpoints work.

config MN10300_DEBUGGER_CACHE_INV_BY_REG
	def_bool y if KERNEL_DEBUGGER && \
			MN10300_CACHE_WTHRU && \
			!MN10300_CACHE_SNOOP && \
			MN10300_CACHE_MANAGE_BY_REG
	help
	  Set if the debugger needs to invalidate the icache using automatic
	  purge registers to make breakpoints work.

config MN10300_DEBUGGER_CACHE_NO_FLUSH
	def_bool y if KERNEL_DEBUGGER && \
			(MN10300_CACHE_DISABLED || MN10300_CACHE_SNOOP)
	help
	  Set if the debugger does not need to flush the dcache and/or
	  invalidate the icache to make breakpoints work.
Commit	Line	Data
0bc42d7f DH	1	#
	2	# MN10300 CPU cache options
	3	#
	4
	5	choice
	6	prompt "CPU Caching mode"
	7	default MN10300_CACHE_WBACK
	8	help
	9	This option determines the caching mode for the kernel.
	10
	11	Write-Back caching mode involves the all reads and writes causing
	12	the affected cacheline to be read into the cache first before being
	13	operated upon. Memory is not then updated by a write until the cache
	14	is filled and a cacheline needs to be displaced from the cache to
	15	make room. Only at that point is it written back.
	16
	17	Write-Through caching only fetches cachelines from memory on a
	18	read. Writes always get written directly to memory. If the affected
	19	cacheline is also in cache, it will be updated too.
	20
	21	The final option is to turn of caching entirely.
	22
	23	config MN10300_CACHE_WBACK
	24	bool "Write-Back"
b478491f DH	25	help
	26	The dcache operates in delayed write-back mode. It must be manually
	27	flushed if writes are made that subsequently need to be executed or
	28	to be DMA'd by a device.
0bc42d7f DH	29
	30	config MN10300_CACHE_WTHRU
	31	bool "Write-Through"
b478491f DH	32	help
	33	The dcache operates in immediate write-through mode. Writes are
	34	committed to RAM immediately in addition to being stored in the
	35	cache. This means that the written data is immediately available for
	36	execution or DMA.
	37
	38	This is not available for use with an SMP kernel if cache flushing
	39	and invalidation by automatic purge register is not selected.
0bc42d7f DH	40
	41	config MN10300_CACHE_DISABLED
	42	bool "Disabled"
b478491f DH	43	help
b478491f DH	44	The icache and dcache are disabled.
0bc42d7f DH	45
0bc42d7f DH	46	endchoice
344af921 DH	47
	48	config MN10300_CACHE_ENABLED
	49	def_bool y if !MN10300_CACHE_DISABLED
518d4bb7 DH	50
	51
	52	choice
	53	prompt "CPU cache flush/invalidate method"
9731d237 AT	54	default MN10300_CACHE_MANAGE_BY_TAG if !AM34_2
9731d237 AT	55	default MN10300_CACHE_MANAGE_BY_REG if AM34_2
518d4bb7 DH	56	depends on MN10300_CACHE_ENABLED
	57	help
	58	This determines the method by which CPU cache flushing and
	59	invalidation is performed.
	60
	61	config MN10300_CACHE_MANAGE_BY_TAG
	62	bool "Use the cache tag registers directly"
8be06289	63	depends on !(SMP && MN10300_CACHE_WTHRU)
518d4bb7	64
9731d237 AT	65	config MN10300_CACHE_MANAGE_BY_REG
	66	bool "Flush areas by way of automatic purge registers (AM34 only)"
	67	depends on AM34_2
	68
518d4bb7 DH	69	endchoice
	70
	71	config MN10300_CACHE_INV_BY_TAG
	72	def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED
	73
9731d237 AT	74	config MN10300_CACHE_INV_BY_REG
	75	def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_ENABLED
	76
518d4bb7 DH	77	config MN10300_CACHE_FLUSH_BY_TAG
518d4bb7 DH	78	def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK
9731d237 AT	79
	80	config MN10300_CACHE_FLUSH_BY_REG
	81	def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK
b478491f DH	82
	83
	84	config MN10300_HAS_CACHE_SNOOP
	85	def_bool n
	86
	87	config MN10300_CACHE_SNOOP
	88	bool "Use CPU Cache Snooping"
	89	depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP
	90	default y
	91
	92	config MN10300_CACHE_FLUSH_ICACHE
	93	def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP
	94	help
	95	Set if we need the dcache flushing before the icache is invalidated.
	96
	97	config MN10300_CACHE_INV_ICACHE
	98	def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP
	99	help
	100	Set if we need the icache to be invalidated, even if the dcache is in
	101	write-through mode and doesn't need flushing.
7f386ac3 DH	102
	103	#
	104	# The kernel debugger gets its own separate cache flushing functions
	105	#
	106	config MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG
	107	def_bool y if KERNEL_DEBUGGER && \
	108	MN10300_CACHE_WBACK && \
	109	!MN10300_CACHE_SNOOP && \
	110	MN10300_CACHE_MANAGE_BY_TAG
	111	help
	112	Set if the debugger needs to flush the dcache and invalidate the
	113	icache using the cache tag registers to make breakpoints work.
	114
	115	config MN10300_DEBUGGER_CACHE_FLUSH_BY_REG
	116	def_bool y if KERNEL_DEBUGGER && \
	117	MN10300_CACHE_WBACK && \
	118	!MN10300_CACHE_SNOOP && \
	119	MN10300_CACHE_MANAGE_BY_REG
	120	help
	121	Set if the debugger needs to flush the dcache and invalidate the
	122	icache using automatic purge registers to make breakpoints work.
	123
	124	config MN10300_DEBUGGER_CACHE_INV_BY_TAG
	125	def_bool y if KERNEL_DEBUGGER && \
	126	MN10300_CACHE_WTHRU && \
	127	!MN10300_CACHE_SNOOP && \
	128	MN10300_CACHE_MANAGE_BY_TAG
	129	help
	130	Set if the debugger needs to invalidate the icache using the cache
	131	tag registers to make breakpoints work.
	132
	133	config MN10300_DEBUGGER_CACHE_INV_BY_REG
	134	def_bool y if KERNEL_DEBUGGER && \
	135	MN10300_CACHE_WTHRU && \
	136	!MN10300_CACHE_SNOOP && \
	137	MN10300_CACHE_MANAGE_BY_REG
	138	help
	139	Set if the debugger needs to invalidate the icache using automatic
	140	purge registers to make breakpoints work.
	141
	142	config MN10300_DEBUGGER_CACHE_NO_FLUSH
	143	def_bool y if KERNEL_DEBUGGER && \
	144	(MN10300_CACHE_DISABLED \|\| MN10300_CACHE_SNOOP)
	145	help
	146	Set if the debugger does not need to flush the dcache and/or
	147	invalidate the icache to make breakpoints work.